PIPELINE INTERRUPTS

PIPELINE INTERRUPTS

MOOKAMBIGAI COLLEGE OF ENGINEERING

M.R.KARTHIKIII rd Year Department of Electronics & Communication Engineering

OVERVIEW OF PIPELININGPipelining is widely used in modern

processors.Pipelining improves system performance

in terms of throughput.Pipelined organization requires

sophisticated compilation techniques.

What is interrupt ?An interrupt is a signal to the processor emitted by

hardware or software indicating an event that needs immediate attention.

An interrupt alerts the processor to a high-priority condition requiring the interruption of the current code the processor is executing .

The processor responds by suspending its current activities, saving its state, and executing a function called interrupt handler (or interrupt service routine, ISR) to deal with the event.

This interruption is temporary, and after the interrupt handler finishes, the processor resumes execution of the previous thread.

CONCEPTS OF PIPELINING

Pipeline ConceptLaundry Exampleann, Brian, Cathy, Dave

each have one load of clothes to wash, dry, and fold

Washer takes 30 minutes

Dryer takes 40 minutes

“Folder” takes 20 minutes

A B C D

Sequential method

A

B

C

D

30 40 20 30 40 20 30 40 20 30 40 20

6 PM 7 8 9 10 11 Midnight

Time

Sequential laundry takes 6 hours for 4 loads

If they learned pipelining, how long would laundry take?

Pipeline ConceptPipelined laundry

takes 3.5 hours for 4 loads

Pipelining doesn’t help latency of single task, it helps throughput of entire workload

Unbalanced lengths of pipe stages reduces speedup

A

B

C

D

6 PM 7 8 9

T

a

s

k

O

r

d

e

r

Time

30 40 40 40 40 20

Use the Idea of Pipelining in a Computer

F1

E1

F2

E2

F3

E3

I1 I2 I3

(a) Sequential execution

Instructionfetchunit

Executionunit

Interstage bufferB1

(b) Hardware organization

T ime

F1 E1

F2 E2

F3 E3

I1

I2

I3

Instruction

(c) Pipelined execution

Figure 8.1. Basic idea of instruction pipelining.

Clock cycle 1 2 3 4Time

Fetch + Execution

Shows maximum throughput .

Where the first add instruction (Add1) is completed before the multiply instruction.

Suppose that add instruction generate an interrupt the cpu in execution (EX) stage corresponding to cycle 4.

CPU suspends its current activity , then cntrl is transferred to interrupt handler.

It is possible to generate another interrupt by mul instruction ,say cycle . Once again CPU changes its state .

Alternative solution is to introduce a small register set known as history buffer (HB )

It stores initial state temporarily

Fault Tolerance

It is defined as the ability of a system to execute specified algorithm correctly regardless of hardware failures and program errors.

RedundancyWhen a one unit fails , its duties must be taken over by other unit of the system.

These units are used to improve the system and to avoid computation error. They are termed as redundancy

Redundancy can be introduce in several ways, they are

Hardware Redundancy : Having multiple hardware unitsSoftware Redundancy : Multiple version of programs for critical operation Information Redundancy: error detecting code Time Redundancy : Retrying critical operations .

Fault- Tolerant System Design There are two basic approch in designing

fault tolerant system, they are 1) Static redundancy2) Dynamic redundancy

Static redundancyStatic redundancy means use of redundant

hardware or software components, which forms a permanent part of the system .

To understand static redundancy consider triple modular redundancy ( TMR)

Dynamic redundancyThe fault can be tolerated by reorganizing

the system so that the function of fault unit are transferred to fault free unit .

The re-organization can achieved in 3 steps Fault diagnoses Fault elimination Recovery

Dynamic redundancy