RISC vs CISC

Department of Electrical Engineering and Computer Science

RISC vs. CISC

Chetan Patilhttp://chetanpatil.info/

Few Slides Adapted From : Power Struggles: Revisiting the RISC vs. CISC Debate on Contemporary

ARM and x86 Architectures (HPCA 2013)

PAPERS

• D. Bhandarkar and D. W. Clark. Performance from architecture: comparing a RISC and a CISC with similar hardware organization. In ASPLOS '91. [LINK]

• Power Struggles: Revisiting the RISC vs. CISC Debate on Contemporary ARM and x86 Architectures. In HPCA '13. [LINK]

OVERVIEW

• What is RISC & CISC?

• Methods

• Evaluation & Key Findings

• Conclusion

What is CISC & RISC?CISC Approach :

MUL 2:3, 5:2

RISC Approach :

LOAD A, 2:3LOAD B, 5:2PROD A, BSTORE 2:3, A

1991 : METHOD

MIPS M/200 vs VAX 8700

SPECIFICATIONS

1991 : EVALUATION & KEY FINDINGS

METHODOLOGY

RESULT DISCUSSION

Result: Instructions & CPI

• Instruction Ratio: Ratio of MIPS instruction extentions to VAX.• RISC factor: Ratio of number of cycles per program on the VAX compared to MIPS

Result: Operation Counts

Result: Cache Behavior

• VAS cache results from hardware monitor.• MIPS cache results from simulator.

Discussion: Architectural Factors

Favoring MIPS:

• Operand specified decoding • Number of registers.• Floating-point hardware and instruction overlap.• Simple jumps and braches.• Fancy VAX instructions.• Instruction scheduling.• Translation buffers.• Branch displacement size.

Favoring VAX:• Big I-Stream constants. • Not-taken branches.

1991 : CONCLUSION

From architectural point of view: RISC as exmplified by MIPS offer a significant processor performance advantage over a VAX (CISC) of

comparable hardware organization.

Drawbacks:

• Compiler.• Number of bechmarks.• Application-level processor performance only. Not systems level.

2013 : METHOD

BeagleBoard ARM Cortex A8

Intel Atom N450

PandaBoard ARM Cortex A9

Intel Sandy BridgeCore i7

Linux 2.6

SPEC CPU2006

Desktop

CoreMarkWebKit

MobileLighttpdCLucene

Database kernels

Server

• Performance measurement on real hardware

• Extensive use of performance counters• Cycles, instructions, cache misses, branch misses…

• Power measurements using Wattsup meters

2013 : EVALUATION & KEY FINDINGS

METHODOLOGY

PERFORMANCE

POWER &

ENERGY

TRADE OFF

METHODOLOGY

PERFORMANCE

POWER &

ENERGY

TRADE OFF

METHODOLOGY

PERFORMANCE POWER & ENERGY TRADE OFF

Performance Analysis Flow:

• Present execution time for each benchmark.

• Normalize frequency’s impact using cycle counts.

• To understand differences in cycle count and the influence of the ISA, present the dynamic instruction count measures, measured in both macro-ops and micro-ops.

• Use instruction mix, code binary size, and average dynamic instruction length to understand ISA’s influence.

• To understand performance differences not attributable to ISA, look at detailed microarchitecture events.

• Attribute performance gaps to frequency, ISA, or ISAindependent microarchitecture features. Qualitatively reason about whether the ISA forces microarchitecture features.

Performance Analysis: Key Finding 1 Execution Time

• Large performance gaps exist across the four platforms studied, as expected, since frequency ranges from 600 MHz to 3.4 GHz and microarchitectures are very different.

Performance Analysis: Key Finding 2 Cycle-Count

• Performance gaps, when normalized to cycle counts, are less than 2:5 when comparing in-order cores to each other and out-of-order cores to each other.

Performance Analysis: Key Finding 3 Instruction Count

• Instruction and cycle counts imply CPI is less on x86 implementations: geometric mean CPI is 3.4 for A8, 2.2 for A9, 2.1 for Atom, and 0.7 for i7 across all suites. x86 ISA overheads, if any, are overcome by microarchitecture.

Performance Analysis: Key Finding 4 Instruction Format & Mix

• Combining the instruction-count and mixfindings, conclude that ISA effects are indistinguishable between x86 and ARM implementations.

Performance Analysis: Key Finding 5 Microarchitecture

Performance Analysis: Key Finding 5 Microarchitecture Contd.

•The microarchitecture has significant impact on performance. The ARM and x86 architectures have similar instruction counts. The highly accurate branch predictor and large caches, in particular, effectively allow x86 architectures to sustain high performance. x86 performance inefficiencies, if any, are not observed. The microarchitecture, not the ISA, is responsible for performance differences.

Performance Analysis: Key Finding 6 ISA Influence on Microarchitecture

• Beyond the translation to microops, pipelined implementation of an x86 ISA introduces no additional overheads over an ARM ISA for these performance levels.

Power and Energy Analysis Flow:

• Present per benchmark raw power measurements.

• To factor out the impact of technology, present technology-independent power by scaling all processors to 45nm and normalizing the frequency to 1 GHz.

• To understand the interplay between power and performance, examine raw energy.

• Qualitatively reason about the ISA influence on microarchitecture in terms of energy.

Power and Energy Analysis: Key Finding 7 Average Power

• Overall x86 implementations consume significantly more power than ARM implementations.

Power and Energy Analysis: Key Finding 8 Average Technology Independent Power

• The choice of power or performance optimized core designs impacts core power use more than ISA.

Power and Energy Analysis: Key Finding 9 Average Energy

• The choice of power or performance optimized core designs impacts core power use more than ISA.

Trade-off Analysis Flow:

• Combining the performance and power measures, compare the processor implementations using Pareto-frontiers.

• Compare measured and synthetic processor implementations using Energy-Performance Pareto-frontiers.

Trade-off Analysis: Key Finding 10 Power-Performance Trade-offs

• Regardless of ISA or energy-efficiency, high-performance processors require more power than lower performance processors. They follow well established cubic power/performance trade-offs.

Trade-off Analysis: Key Finding 11 Energy-Performance Trade-offs

• It is the microarchitecture and design methodologies that really matter.

2013: CONCLUSION

ISA being RISC or CISC does not matter for power and performance of modern

processors.

What is the ISA’s role?

• Supporting specialization•AVX crypto, Virtualization extensions•Jazelle DBX, ARM Trustzone…

• Exposing more workload-specific semantic information to the substrate•Transactional Memory support •Reliability-oriented extensions•Many more…

Questions?are guaranteed in life, answers aren't.

Thank You

http://chetanpatil.info/talks.html

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