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SiP Summit, Semicon Taiwan, Taipei, Taiwan, Sep. 9th, 2016
Douglas Yu
TSMC R&D, chyu@tsmc.com
WLSI Extends Si Processing and Supports Moore’s Law
Security C –
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TSMC Property
Introduction Moore’s Law Challenges
Heterogeneous Integration
WLSI Innovation and Implementation WLSI for HPC
WLSI for Mobile and others
Si Process and Moore’s Law Si Process Extend from IC to System
Moore’s Law Extension from SoC to SiP
Conclusion
WLSI Outline
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TSMC Property
Credit: Economist, 2016
Moore’s Law Challenges
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TSMC Property
Cost Saving
Process Cost depends on intrinsic cost and yield.
Chip-partition/Split-dies into smaller dies reduce cost.
Yield (cost) difference increases with D0 / chip size.
73.98
66.98
54.96
90.40
30.70
0
20
40
60
80
100
120
0.60 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.01
30mm^2 (0.25X)
40mm^2 (0.33X)
60mm^2 (0.5X)
120mm^2 (1X)
Yie
ld →
D0 →
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TSMC Property
From SoC- to SiP-Scaling WLSI Extends Moore’s Law
Advantages
Shorter interconnect, higher performance/power
Smaller form factor
Cost and cycle-time reduction
A
C B
E 2D
3D
D
SoC SiP
A B
C
D E
A
C B
D E
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Introduction Moore’s Law Challenges
Heterogeneous Integration
WLSI Innovation and Implementation WLSI for HPC
WLSI for Mobile and others
Si Process and Moore’s Law Si Process Extend from IC to System
Moore’s Law Extension from SoC to SiP
Conclusion
WLSI Outline
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I/O
to
Su
bstr
ate
an
d/o
r P
CB
Die/PKG size (mm2)
TSMC WLSI Technology Sets Industry SiP New Trends
→
→
CoWoSTM 2.5D/3D
HPC, SoC partition
Very high memory BW
Wide envelope
InFO (FOWLP)
Mobile, Consumer, HPC
Small form-factor
Cost competitive
UFI (WLCSP)
CoWoS- D. Yu, 2011 Semicon Taiwan, 3D-IC Technology Forum InFO- D. Yu, 2012 iMAPS Device Package Conference, Scottsdale, Az UFI: D. Yu, 3DIC Forum, 2014 ISSCC, San Francisco, Ca
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TSMC Property
1st to deliver Si Interposer (2.5D), CoWoSTM, for HPC
1st to propose and realize 2D/3D high performance FOWLP,
InFO and InFO_PoP, for mobile/IoT. A game changer.
1st System Integration Foundry- a new paradigm shift.
WLSI Technology Platform Initiative, Innovation and Implementation
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TSMC Property
Si Interposer Milestones 1st Wave
Product Xilinx 7V2000T Xilinx 7VH580T Altera 3DTV1
Package view
Interposer size 775 mm2 (25x31) 500mm2 (25x20) 725mm2 (25x29)
Production May ’12, TSMC Oct. ’12, TSMC Oct. ’12, TSMC
Logic x4 Logic1 x2
Logic2 x1 Logic x1
SRAM x1
Lead industry to introduce Si Interposer.
Homogeneous and Heterogeneous Integration.
Enables both Split-dies and Chip-partition to support Moore’s Law extension.
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TSMC Property
Si Interposer Milestones 2nd Wave
Product Xilinx VU440 AMD Fiji Nvidia GP100
Package view
Interposer size 1150 mm2 (31x36) 1010mm2 (28x36) 1160mm2 (29x40)
Production Jan. ’15, TSMC Jun. ’15, ASE/UMC Apr. ’16, TSMC
Logic x1
HBM2 x4 Logic x1
HBM1 x4 Logic x3
Exceeded full scanner size.
Enable Logic + HBM1/2 integration for HPC.
Scale-up SiP function and performance for deep learning and more.
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TSMC Property
CoWoS Key Merits
Sub-mm interconnect DD Cu, 1000+ lines/mm
Small via, easy routing
Very low defect density
Super large size 1200 mm2 in production.
Going 1500 mm2
Highest level of multi-die integration
Flexible Integration
JESD235 compatible for HBM. NO customization need.
Enable Logic Chip-partition.
Leverage Flip-Chip No ELK related CPI issue
Same thermal solution as flip chip
DD SAP
Interposer SiP
~40 mm
~30 mm
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TSMC Property
InFO-PoP: Si Process Extention 1st HD/HP 3D-FOWLP proposed, developed and delivered.
Chips and function extended with molding. Si process extended
and help to sustain Moore’s Law.
NOT embedded. Chip backside exposed with Form Factor, Heat
Dissipation, CT and Cost advantages (Chip-first approach).
Logic I/Os
Logic
Substrate
Package I/Os InFO
Multi-Chip Flip Chip CSP
Molding and Metal
Logic or DRAM, Die or PKG
Flip Chip PoP InFO-PoP
SoC1
Substrate
SoC2
SoC2 SoC1
Through-
Mold –Via
(TMV)
DRAM
Logic
substrate
Flip Chip CSP
Multi-Chip InFO
Through-
InFO –Via
(TIV)
Logic
Logic
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InFO_PoP for AP/DRAM
Integrated design and manufacturing (Si→System).
High-end AP/DRAM applications with PPPCC optimization.
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TSMC Property
AP/DRAM SiP
InFO/TIV Replaces 3DIC/TSV
Architecture FC_PoP 3DIC (TSV) InFO_PoP
Max. Bandwidth L H H
Total Power H L L
Thickness H M L
Thermal qJA (SoC) M H L
Cost L H L
Chip Partition N N Y
DRAM KGP Y N Y
- Doug Yu, 2014 IEDM, San Francisco, CA
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Introduction Moore’s Law Challenges
Heterogeneous Integration
WLSI Innovation and Implementation WLSI for HPC
WLSI for Mobile and others
Si Process and Moore’s Law Si Process Extend from IC to System
Moore’s Law Extension from SoC to SiP
Conclusion
WLSI Outline
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TSMC Property
Si Process Extension Extended Si System process flow
Integrated Design and Manufacturing
Grand optimization of multi-component system
Moore’s Law Extension
Enable SiP-Scaling, complementary or alternative to SoC-Scaling
System Volume Scaling Down, Function Scaling Up
Full IO pin-count spectrum: mobility, IoT, automotive, HPC and DRAM integration.
WLSI for Advanced Packaging
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TSMC Property
WLSI Leverage/Extend Si Process
CoWoS: CoW, Chips stack on TSV wafer.
InFO_PoP: PoW, PKG stack on TiV wafer.
Manufacturing of HD/HP 3D-FOWLP and CoWoS is very challenging.
WLSI leverages on-chip Cu interconnect technology. Extends Si wafer
processing from Si to (sub) System.
Si with TSV
(Interposer)
CoW
Stacking
(m-bump)
Dicing,
Mount on
Substrate
Ship
CoW CoWoS Interposer
wafer
CoWoS
Fan-out
With TIV
PoW
Stacking
(with BGA)
Dicing and
Ship
PoW Fan-out
wafer
InFO_PoP
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TSMC Property
SiP-Scaling Reduce System Size and Increase Function
More functions
Higher Performance
Smaller, cheaper with lower power
Silicon Interposer
DRAM
Logic
Flash RF Passives
CIS Analog MEMS
PCB for system integration
WLSI for heterogeneous integration-
multi-chips integrated In a single package
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TSMC Property
Die-1
Die-2
Die-3
Finer pitches RDL (L/S=2/2mm)
Multi-Chip ultra-large PKG 24x26mm2
Compact 2D Integration For Chip Partition and HPC
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TSMC Property
Compact 3D-Stacking for Extension of Moore’s Law
High-density multi-chips 2D-Stacking
High-density multi-layers 3D-Stacking
3D-Stacking Layout
Multi-chips Integrated
Package
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TSMC Property
Multi-chips, multi-sensors intelligent systems
Intelligent System
Compact 3D-Stacking Realizes Intelligent Systems
Scheme
Chip 1
Sensor 1
Chip 2
Sensor 2
Pulse Rate: 4/3.44x60 = 70 (beats/min)
Heart Rate
Sensor
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© 2013 TSMC, Ltd
TSMC Property
Foundry Tech Platforms
Logic MEMS
M 65nm
90nm
0.13µm
0.25µm
0.35µm
>0.5µm
40nm
28nm
0.18µm
Mixed
Signal/RF
R
A
BCD
Power IC
B
HV
Driver
D
CIS
C
E-Flash
(MCU)
M
E-DRAM
More-Than-Moore Platform
WLSI Platform
Bumping
EU/LF/Cu TSV
Interposer
65nm
90nm
0.13µm
0.25µm
0.35µm
40nm
28nm
0.18µm
Fan-In
WLP FC-CSP
Cu_BoT
InFO_PoP FC-BGA
Cu_BoP
TSV 3D-
IC
InFO
20nm
0.13µm
Logic MEMS
65/55nm
90/80nm
0.18µm
0.25µm
0.35µm
40nm
28nm
Analog Power
IC-BCD
High
Voltage
CMOS
Image
Sensor
Embedded
Flash
(MCU)
Embedded
DRAM
MS/RF
CMOS
16nm
Cu/
LK
Strai
nedS
ilico
n
Immer
sion
Cu/EL
K
HK/MG
Low-R
8” BSI
12” BSI
Expanding Functionality Expanding Functionality
ESF1 Automot
ive
ESF2
ESF3
Moore’s Law Platform
20nm
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TSMC Property
WLSI Optimization and Heterogeneous Integration
SoC→ SiP
Grand Optimization
3D
W
LS
I
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TSMC Property
1st to commercialize Si Interposer, and 1st to bring propose and bring 3D-FOWLP to HVM. Grow TSMC to 1st SiP-foundry.
WLSI extends Si process to system and enables SiP-Scaling, to support Moore's Law extension.
Grand system optimization of Moore’s Law and MTM chips with WLSI provides unique values. Further strengthen TSMC as wafer processing technology powerhouse.
WLSI Conclusions
Recommended