Voltage Divider Bias ELEC 121. January 2004ELEC 1212 BJT Biasing 3 For the Voltage Divider Bias...

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Voltage Divider Bias

ELEC 121

January 2004 ELEC 121 2

BJT Biasing 3For the Voltage Divider Bias Configurations• Draw Equivalent Input circuit• Draw Equivalent Output circuit• Write necessary KVL and KCL Equations• Determine the Quiescent Operating Point

– Graphical Solution using Loadlines– Computational Analysis

• Design and test design using a computer simulation

January 2004 ELEC 121 3

Voltage-divider bias configuration

January 2004 ELEC 121 4

Voltage Divider Input Circuit Approximate AnalysisThe Approximate method may be used only when R2 .1 RE

Under these conditions RE does not significantly load R2 and it is effect may be ignored: IB << I1 and I2 and I1 I2 Therefore:

We may apply KVL to the input, which gives us:

-VB + VBE + IE RE = 0

Solving for IE we obtain:

2B CC

1 2

RV = V

R + R

B BE

EE

V - V I =

R

January 2004 ELEC 121 5

Input Circuit Exact AnalysisThe Exact Analysis method is always valid must be used when R2 > .1 RE

Perform Thevenin’s Theorem using the transistor as the loadOpen the base lead of the transistor, and the Voltage Divider bias circuit is:

Calculate RTH

2TH CC

1 2

RV = V

R + R

We may apply KVL to the input, which gives us:-VTH + IB RTH + VBE + IE RE = 0Since IE = ( + 1) IB

ESolving for I we obtain:

THTH E BE E E

TH BEE

THE

R-V + I + V + I R = 0

β + 1

V - V I =

R + R

β + 1

January 2004 ELEC 121 6

Redrawing the input circuit for the network

January 2004 ELEC 121 7

Determining VTH

2TH CC

1 2

RV = V

R + R

January 2004 ELEC 121 8

Determining RTH

1 2TH

1 2

R R R =

R + R

January 2004 ELEC 121 9

The Thévenin Equivalent Circuit

Note that VE = VB – VBE and IE = ( + 1)IB

January 2004 ELEC 121 10

Input Circuit Exact Analysis

We may apply KVL to the input, which gives us:-VTH + IB RTH + VBE + IE RE = 0Since IE = ( + 1) IB

ESolving for I we obtain:

THTH E BE E E

TH BEE

THE

R-V + I + V + I R = 0

β + 1

V - V I =

R + R

β + 1

January 2004 ELEC 121 11

Collector-Emitter Loop

January 2004 ELEC 121 12

Collector-Emitter (Output) Loop

Applying Kirchoff’s voltage law: - VCC + IC RC + VCE + IE RE = 0

Assuming that IE IC and solving for VCE: IC = VCC – VCE – (RE + RC)

Solve for VE: VE = IE RE

Solve for VC: VC = VCC - IC RC

or

VC = VCE + IE RE

Solve for VB: VB = VCC - IB RB or

VB = VBE + IE RE

January 2004 ELEC 121 13

Voltage Divider Bias Example 1

January 2004 ELEC 121 14

Voltage Divider Bias Example 2

January 2004 ELEC 121 15

Design of CE Amplifier with Voltage Divider Bias

1. Select a value for VCC

2. Determine the value of from spec sheet or family of curves3. Select a value for ICQ

4. Let VCE = ½ VCC (typical operation, 0.4 VCC ≤ VC ≤ 0.6 VCC )

5. Let VE = 0.1 VCC (for good operation, 0.1 VCC ≤ VE ≤ 0.2 VCC )6. Calculate RE and RC

7. Let R2 ≤ 0.1 RE (for this calculation, use low value for )8. Calculate R1

CC B1 2

B

V - V R = R

V

January 2004 ELEC 121 16

CE Amplifier Design• Design a Common Emitter Amplifier with Voltage Divider

Bias for the following parameters:

VCC = 24V

IC = 5mAVE = .1VCC

VC = .55VCC

= 135

January 2004 ELEC 121 17

January 2004 ELEC 121 18

CE Amplifier Design

January 2004 ELEC 121 19

CE Amplifier Design Voltage Divider Bias

January 2004 ELEC 121 20

Voltage Divider Bias with Dual Power Supply

January 2004 ELEC 121 21

Voltage Divider Bias with Dual Power Supply

Input Circuit Find VTH and RTH

2 1TH CC EE

1 2

2TH1 CC

1 2

EE

1TH2 EE

1 2

TH TH

1 2

1 2TH

1 2

1 TH2

R V = V

R + R

(Note V is negative)

R V = V

R + R

V =

R R V = V - V

R + R R + R

R R R =

R +

V - V

R

January 2004 ELEC 121 22

Voltage Divider Bias with Dual Power Supply

Output Circuit

CC

CC C C CE E E EE

E C

C E

EE CEC

C E

CC EE CEC

C E

V + V - V I =

R +

-V + I R + V + I R - V = 0

If we assume I @ I (β > 100)

If R

V + V -

we use

V I =

I =

R +

I

αR

α

January 2004 ELEC 121 23

Voltage Divider Bias with Dual Power Supply

PSpice Simulation

January 2004 ELEC 121 25

PSpice Bias Point Simulation

January 2004 ELEC 121 26

PSpice Simulation for DC Bias

January 2004 ELEC 121 27

PSpice Simulation for DC Sweep

January 2004 ELEC 121 28

PSpice Simulation for DC Sweep

The response of VCE demonstrates that it reaches a peak value near the Q point and then decreases

The response of VC demonstrates rises rapidly towards the Q Point and then increases gradually towards a maximum value

January 2004 ELEC 121 29

Simulation Settings for AC Sweep

January 2004 ELEC 121 30

Probe Output for AC Sweep

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