Virtex II-Pro Dynamical Test Application - Part B -

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Performed By: Khaskin Luba Performed By: Khaskin Luba

Einhorn RazielEinhorn Raziel

Instructor: Rivkin InaInstructor: Rivkin Ina

Winter 2005Winter 2005

Virtex II-Pro Dynamical Virtex II-Pro Dynamical Test ApplicationTest Application

- Part B -- Part B -

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Quick OverviewQuick Overview

Examining possible space-Examining possible space-compatibility of compatibility of civilian devicescivilian devices, in , in order to integrate them in satellites.order to integrate them in satellites.

Statistically modelingStatistically modeling the device’s the device’s robustness to robustness to temporarytemporary damage and damage and it’s ability to recover in a case of an it’s ability to recover in a case of an error.error.

Testing the device’s modules Testing the device’s modules functioning functioning under real-time radiation.under real-time radiation.

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THE COMPLETE SYSTEM THE COMPLETE SYSTEM OVERVIEWOVERVIEW

HOST - PC

DUT -Virtex II-PRO XC2VP7(placed on the development board)

Serial PortSerial Port USB PortUSB PortJTAG PortJTAG Port

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System Block DiagramSystem Block Diagram

DUTDUTVirtex II-PRO FPGAVirtex II-PRO FPGA

HostHostXilinx ToolsXilinx Tools

GUIGUI

Microsoft ExcelMicrosoft Excel

LogicLogic Power PCPower PC

Serial PortSerial PortUSB PortUSB Port JTAG PortJTAG Port

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The Virtex II-PRO FPGA The Virtex II-PRO FPGA XC2VP7XC2VP7

The Internal FPGA Modules:

- 8 Rocket I/O Transceiver Blocks- 4 DCM (Digital Clock Manager)- 44 Block Select RAM Memory total of 792KB- 44 18x18 Multiplier Blocks- PPC405- 396 User I/O pads- 4928 slices holding 157KB memory, 9856 flip-flops, and 11088 logic cells

DUTDUT

HostHost

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Graphical User InterfaceGraphical User Interface

User transparentUser transparent Initializing the testing systemInitializing the testing system Choosing and loading the testing functionChoosing and loading the testing function Receiving data via USB and calculating statistical resultsReceiving data via USB and calculating statistical results

GUI was created in C++ language, using Visual Studio 6GUI was created in C++ language, using Visual Studio 6 Uses supplied Dynamic Library files (Dll files),Uses supplied Dynamic Library files (Dll files),

in order to control the USB modulein order to control the USB module

DUTDUT

HostHost

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Graphical User Interface - Graphical User Interface - AlgorithmAlgorithm

Test in

Process

Gathering test info

Writing appropriate

impl. file

Test typedecision

Opening USB port

Sending start signal

Listening to USB

Collecting datato Excel file

Closing USB port

Delete temporary var .

End Test condition

Opening Excel

START

Test Ended

DUTDUT

HostHost

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GUI – Main WindowGUI – Main Window

Status Window

Test Type

Tests List

DUTDUT

HostHost

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GUI – Settings GUI – Settings WindowWindow

Programs’ locationUSB connection & drivers check button

DUTDUT

HostHost

Serial Port COM Select

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Serial PortSerial PortJTAG PortJTAG Port

HostHost

DUTDUT - - Virtex II-PRO FPGAVirtex II-PRO FPGA

Power PCPower PC

USB PortUSB Port

DUTDUT - - Virtex II-PRO FPGAVirtex II-PRO FPGA

LOGICLOGIC

JTAG PortJTAG Port

HostHostThe DUTThe DUT

Combined of: Combined of: Power PCPower PC LogicLogic – logic and memory elements, DCM, MGT. – logic and memory elements, DCM, MGT.

In the In the Power PC Power PC tests the tests the Serial Port Serial Port is being used.is being used.

In the In the Logic Logic tests the tests the USB Port USB Port is being used.is being used.

The first part of this presentation deals with the The first part of this presentation deals with the LOGIC modules of the FPGA and the USB LOGIC modules of the FPGA and the USB connection…connection…

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DLP-USB245M - DLP-USB245M - FeaturesFeatures

Fast connection – up to 1 Mb/sec.Fast connection – up to 1 Mb/sec. Small implementation Small implementation Simple InterfaceSimple Interface Mounted on a P130 expansion moduleMounted on a P130 expansion module

DUTDUT

HostHost

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The Testing Concept – The Testing Concept – Peripheral ModulesPeripheral Modules

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MUT - Module Under MUT - Module Under TestTest

The examined modules:The examined modules:

I/O BlocksI/O Blocks Fast Multipliers Fast Multipliers Rocket I/ORocket I/O Digital Clock Manager (DCM) Digital Clock Manager (DCM) CLB MemoryCLB Memory CLB Flop-flopsCLB Flop-flops CLB logicCLB logic BRAMsBRAMs Power PCPower PC

USBContr.

MCT MUT

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USB ControllerUSB Controller USBContr.

MCT MUT

Controls reading and writing cycles.Controls reading and writing cycles. Determines USB’s control signals during reading Determines USB’s control signals during reading

and writing cycles.and writing cycles. Sets up the relevant data to be sent back to host.Sets up the relevant data to be sent back to host. Designed with minimal usage of logic and Designed with minimal usage of logic and

memory elements.memory elements.

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USB ControllerUSB ControllerUSBContr.

MCT MUT

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MCTMCT Identical basic structure for all the testing functions:Identical basic structure for all the testing functions:

- Defines input and comparison vectors in order to test the - Defines input and comparison vectors in order to test the

module’s functioning. module’s functioning.

- Computes the numbers of errors and instructs their - Computes the numbers of errors and instructs their

transference using the USB Controller. transference using the USB Controller.

Designed with the ambition to maximize the test’s mapping of each examined module.Designed with the ambition to maximize the test’s mapping of each examined module.

Minimal usage of logic and memory elements.Minimal usage of logic and memory elements.

USBContr.

MCT MUT

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The MCT Testing The MCT Testing FlowFlow

End Test Comman

d

Creating input and comparison

vectors;Updating

control signals

Listening to Host

Single/Multiple

tests?

Waiting for

outputs

Sending input vectors to

MUT

Multiple tests

Checking outputs;

Sending results

Single test

Loading bit file

TestEnded

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The Fast Multipliers The Fast Multipliers TestTest

USBContr.

MCT MUT

USB ControllerUSB Controller

MCTMCT

MUTMUT

(Multiplier Blocks)

Reading Control

Read-Write Control

Writing Control

Error Generator **

Indicator

Reset Block

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Several blocks of fast multipliers are chained together to achieve 100% mapping.Several blocks of fast multipliers are chained together to achieve 100% mapping. The input vectors, set by the MCT, diffuse through the multipliers chain. The outputs are The input vectors, set by the MCT, diffuse through the multipliers chain. The outputs are

being compared with the expected result vectors using several feedbacks. being compared with the expected result vectors using several feedbacks. The calculated errors are being sent via USB, using the USB Controller, in steady time The calculated errors are being sent via USB, using the USB Controller, in steady time

intervals.intervals. Same method of diffusion through the MUT blocks chain and of error Same method of diffusion through the MUT blocks chain and of error

calculation by comparison between the expected result vectors and the calculation by comparison between the expected result vectors and the output vectors was used in all the performed tests described further…output vectors was used in all the performed tests described further…

The Fast Multipliers The Fast Multipliers TestTest

USBContr.

MCT MUT

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Design Summary--------------Number of errors: 0Number of warnings: 0Logic Utilization:

Number of Slice Flip Flops: 1,229 out of 9,856 12%

Number of 4 input LUTs: 1,796 out of 9,856 18%Logic Distribution:

Number of occupied Slices: 1,352 out of 4,928 27%

Total Number 4 input LUTs: 1,820 out of 9,856 18%

Number of bonded IOBs: 13 out of 248 5% Number of PPC405s: 0 out of 1 0%

Number of MULT18X18s: 44 out of 44 100% Number of GCLKs: 1 out of 16 6% Number of GTs: 0 out of 8 0% Number of GT10s: 0 out of 0 0%

Fast Multipliers Test Mapping Statistics:Fast Multipliers Test Mapping Statistics:

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The BRAMs TestThe BRAMs Test USBContr.

MCT MUT

USB ControllerUSB Controller

MCTMCT

MUTMUT

(BRAM Block)

Reading Control Read-Write

Control

Writing Control

Indicator

Reset Block

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Design Summary--------------Number of errors: 0Number of warnings: 0Logic Utilization:

Number of Slice Flip Flops: 150 out of 9,856 1% Number of 4 input LUTs: 405 out of 9,856

4%Logic Distribution:

Number of occupied Slices: 245 out of 4,928 4%

Total Number 4 input LUTs: 420 out of 9,856 4%

Number of bonded IOBs: 18 out of 248 7% Number of PPC405s: 0 out of 1 0%

Number of Block RAMs: 44 out of 44 100% Number of GCLKs: 1 out of 16 6% Number of GTs: 0 out of 8 0% Number of GT10s: 0 out of 0 0%

BRAMs Test Mapping Statistics:BRAMs Test Mapping Statistics:

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CLB Flip-Flops TestCLB Flip-Flops Test USBContr.

MCT MUT

USB ControllerUSB Controller

MCTMCT

MUTMUT

(CLB Flip-Flops Blocks)

Indicator

Reset Block

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CLB Flip-Flops CLB Flip-Flops TestTest

USBContr.

MCT MUT

CLB Flip-Flops Block – Closer LookCLB Flip-Flops Block – Closer Look

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Design Summary--------------Number of errors: 0Number of warnings: 0Logic Utilization:

Number of Slice Flip Flops: 9,235 out of 9,856 93%

Number of 4 input LUTs: 227 out of 9,856 2%Logic Distribution:

Number of occupied Slices: 4,926 out of 4,928 99%

Total Number 4 input LUTs: 237 out of 9,856 2% Number of bonded IOBs: 18 out of 248 7%

Number of PPC405s: 0 out of 1 0% Number of GCLKs: 1 out of 16 6% Number of GTs: 0 out of 8 0% Number of GT10s: 0 out of 0 0%

CLB Flip-FlopsCLB Flip-Flops Test Mapping Statistics:Test Mapping Statistics:

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CLB Logic TestCLB Logic Test USBContr.

MCT MUT

USB ControllerUSB Controller

MCTMCT

MUTMUT

(Logic Blocks - Adders)

Reading Control

Read-Write Control

Writing Control

Indicator

Reset Block

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Design Summary--------------Number of errors: 0Number of warnings: 0Logic Utilization:

Number of Slice Flip Flops: 9,705 out of 9,856 98%

Number of 4 input LUTs: 6,188 out of 9,856 62%Logic Distribution:

Number of occupied Slices: 4,926 out of 4,928 99%

Total Number 4 input LUTs: 6,188 out of 9,856 62%

Number of bonded IOBs: 18 out of 248 7% Number of PPC405s: 0 out of 1 0% Number of GCLKs: 1 out of 16 6% Number of GTs: 0 out of 8 0% Number of GT10s: 0 out of 0 0%

CLB LogicCLB Logic Test Mapping Statistics:Test Mapping Statistics:

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CLB Memory TestCLB Memory Test USBContr.

MCT MUT

USB ControllerUSB Controller

MCTMCT

MUTMUT

(LUT Blocks)

Indicator

Reset Block

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Design Summary--------------Number of errors: 0Number of warnings: 0Logic Utilization:

Number of Slice Flip Flops: 128 out of 9,856 1% Number of 4 input LUTs: 1,047 out of 9,856

10%Logic Distribution:

Number of occupied Slices: 4,920 out of 4,928 99%

Total Number 4 input LUTs: 9,760 out of 9,856 99%

Number used for 32x1 RAMs: 8,704( Two LUTs used per 32x1 RAM)

Number of bonded IOBs: 18 out of 248 7% Number of PPC405s: 0 out of 1 0% Number of GCLKs: 1 out of 16 6% Number of GTs: 0 out of 8 0% Number of GT10s: 0 out of 0 0%

CLB MemoryCLB Memory Test Mapping Statistics:Test Mapping Statistics:

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DCM TestDCM Test USBContr.

MCT MUT

USB ControllerUSB Controller

MCTMCT

MUTMUT

(4 DCM Units)

Indicator

Reset Block

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Design Summary--------------Number of errors: 0Number of warnings: 0Logic Utilization:

Number of Slice Flip Flops: 272 out of 9,856 2% Number of 4 input LUTs: 452 out of 9,856 4%

Logic Distribution: Number of occupied Slices: 273 out of 4,928 5%

Total Number 4 input LUTs: 452 out of 9,856 4% Number of bonded IOBs: 18 out of 248 7%

Number of PPC405s: 0 out of 1 0% Number of GCLKs: 16 out of 16 100%

Number of DCMs: 4 out of 4 100% Number of GTs: 0 out of 8 0% Number of GT10s: 0 out of 0 0%

DCMDCM Test Mapping Statistics:Test Mapping Statistics:

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Rocket I/O TestRocket I/O Test USBContr.

MCT MUT

USB ControllerUSB Controller

MCTMCT

MUTMUT

(Transceivers Block)

Indicator

Reset Block

Clock Buffers

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Rocket I/O TestRocket I/O Test USBContr.

MCT MUT

DATA FLOW CHART –DATA FLOW CHART –Transceivers and Loop-back Transceivers and Loop-back

TestingTesting

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Design Summary--------------Number of errors: 0Number of warnings: 0Logic Utilization:

Number of Slice Flip Flops: 117 out of 9,856 1% Number of 4 input LUTs: 294 out of 9,856 2%

Logic Distribution: Number of occupied Slices: 186 out of 4,928 3%

Total Number 4 input LUTs: 294 out of 9,856 2% Number of bonded IOBs: 26 out of 248 10%

Number of PPC405s: 0 out of 1 0% Number of GTIPADs: 8 out of 16 50% Number of GTOPADs: 8 out of 16 50% Number of GCLKs: 1 out of 16 6% Number of GTs: 4 out of 8 50%

Number of GT10s: 0 out of 0 0%

Rocket I/O Transceivers Test Mapping Statistics:Rocket I/O Transceivers Test Mapping Statistics:

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Design Summary--------------Number of errors: 0Number of warnings: 0Logic Utilization:

Number of Slice Flip Flops: 119 out of 9,856 1% Number of 4 input LUTs: 389 out of 9,856

3%Logic Distribution:

Number of occupied Slices: 229 out of 4,928 4%

Total Number 4 input LUTs: 389 out of 9,856 3%

Number of bonded IOBs: 26 out of 248 10% Number of PPC405s: 0 out of 1 0%

Number of GTIPADs: 16 out of 16 100% Number of GTOPADs: 16 out of 16 100%

Number of GCLKs: 1 out of 16 6% Number of GTs: 8 out of 8 100%

Number of GT10s: 0 out of 0 0%

Rocket I/ORocket I/O Loop-Back Test Mapping Statistics:Test Mapping Statistics:

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Combined TestCombined Test USBContr.

MCT MUT

USB ControllerUSB Controller

MCTMCT

Reading Control

Read-Write Control

Writing Control

Indicator

Reset Block

CLB Logic (adders)

Fast Multipliers

MGT

DCM

CLB Memory (LUTs)

BRAMs

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Design Summary--------------Number of errors: 0Number of warnings: 0Logic Utilization:

Number of Slice Flip Flops: 8,661 out of 9,856 87%

Number of 4 input LUTs: 7,137 out of 9,856 72%Logic Distribution:

Number of occupied Slices: 4,926 out of 4,928 99%

Total Number 4 input LUTs: 7,655 out of 9,856 77%

Number of bonded IOBs: 26 out of 248 10% Number of PPC405s: 0 out of 1 0%

Number of GTIPADs: 16 out of 16 100% Number of GTOPADs: 16 out of 16 100% Number of Block RAMs: 44 out of 44 100%

Number of MULT18X18s: 44 out of 44 100%

Number of GCLKs: 1 out of 16 6% Number of GTs: 8 out of 8 100% Number of DCMs: 1 out of 4 25%

Number of GT10s: 0 out of 0 0%

CombinedCombined Test Mapping Statistics:Test Mapping Statistics:

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SOFTWARE WORK FLOW

Bit file GUI Design

Logic Simulation

High Level Design

Core Generator, Architecture Wizard

Low Level Synthesis

Test Algorithm

Place and Route

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The Virtex II-Pro FPGA The Virtex II-Pro FPGA XC2VP7XC2VP7Power-PC 405 structurePower-PC 405 structure DUTDUT

HostHost

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Performed TestsPerformed Tests

1.1. General Purpose Registers testGeneral Purpose Registers test

2.2. MMU test (TLB)MMU test (TLB)

3.3. Instruction test (including memory Instruction test (including memory test) test)

4.4. Cache testCache test

5.5. Timers testTimers test

6.6. Interrupts testInterrupts test

7.7. Integrated modules testIntegrated modules test

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Hardware Design: 3 Hardware platforms:Hardware Design: 3 Hardware platforms:1.1. Platform without access to external Platform without access to external

memory – for cache testmemory – for cache test2.2. Platform with maximum modules – for Platform with maximum modules – for

integrated modules testintegrated modules test3.3. Platform with minimum modules – for all Platform with minimum modules – for all

other tests other tests Software design: 2 layers - C code & Software design: 2 layers - C code &

assemblyassembly Implementation of software in designated Implementation of software in designated

BRAM blockBRAM block

Test Concept - PPCTest Concept - PPC

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Hardware Design – Block Hardware Design – Block DiagramDiagram

PPC405

PLB

PLB2OPB

BRAM

BRAM

OPB

JTAG

Timer

RS232 (UART)

DCM

To Host

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Hardware Design – Block Hardware Design – Block DiagramDiagram

Cache test systemCache test system

PPC405

PLB

PLB2OPB

BRAM

BRAM

OPB

JTAG

Timer

RS232 (UART)

DCM

To Host

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Hardware Design – Block Hardware Design – Block DiagramDiagram

Integrated test systemIntegrated test system

PPC405

PLB

PLB2OPB

BRAM

BRAM

OPB

JTAG

Timer

RS232 (UART)

DCM

To Host

GPIO

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Test Algorithm - PPCTest Algorithm - PPC

Assembly LayerAssembly Layer

C code LayerC code LayerSTART

CreateInput & “Golden”

Vectors

Assign Physical Address

To inputs

Load input Vectors by physical

address

Perform TestCreate Outputs

Save outputVectors to specified Physical address

Load & CompareOutputs with golden

vectors

Send results to serial port

Single/Multiple

tests?

FINISHTEST

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Write the following values to registers:Write the following values to registers:

0x00000000,0xFFFFFFFF,0xAAAAAAAA,00x00000000,0xFFFFFFFF,0xAAAAAAAA,0x55555555,x55555555,

Number of register (0-31).Number of register (0-31).

Read from registers and compare to Read from registers and compare to written values written values

Instructions Used: li, mr, addiInstructions Used: li, mr, addi

1. General-Purpose 1. General-Purpose RegistersRegisters

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TLB buffer contains 64 indexes.TLB buffer contains 64 indexes.

Using same method as in the General-Using same method as in the General-Purpose RegistersPurpose Registers

test for the TLB Buffer. Write & read to test for the TLB Buffer. Write & read to each indexeach index

Instructions Used: tlbre, tlbweInstructions Used: tlbre, tlbwe

2. MMU Test - TLB2. MMU Test - TLB

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3. Instruction Set3. Instruction Set

Executing selected instructions (including Executing selected instructions (including memorymemory

instructions) using above values.instructions) using above values.

Compare outputs with those expected.Compare outputs with those expected.Instructions tested:Instructions tested:

Arithmetic:Arithmetic: Add, mulli, subf Add, mulli, subf

Compare:Compare: cmpi, mfcr cmpi, mfcr

Logic:Logic: Or, And, Xor Or, And, Xor

Memory:Memory: stw, lwz stw, lwz

Branch:Branch: b b

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As mentioned – a separate hardware platform is As mentioned – a separate hardware platform is usedused

here. here.

Run simple code which performs Add, Multiply andRun simple code which performs Add, Multiply and

Condition operations. Condition operations.

Compare with expected results. Compare with expected results. C-Code level only. No special instructions used.C-Code level only. No special instructions used.

4. Cache Test4. Cache Test

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5. Timers test5. Timers test

Implement a timer (using base system resources), andImplement a timer (using base system resources), and

Measure a pre-defined process.Measure a pre-defined process.

Compare with expected results.Compare with expected results. C-Code level only. No special instructions used.C-Code level only. No special instructions used.

access to timer using supplied driver.access to timer using supplied driver.

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Generating an Interrupt which raise a global flag andGenerating an Interrupt which raise a global flag and

Check the flag’s value. Check the flag’s value.

The interrupt is generated using decrementing counterThe interrupt is generated using decrementing counter

(based on a timer implemetation) (based on a timer implemetation) C-Code level only. No special instructions used.C-Code level only. No special instructions used.

access to timer and control on interrupt using supplied driver.access to timer and control on interrupt using supplied driver.

6. Interrupts test6. Interrupts test

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As mentioned – a separate hardware platform is As mentioned – a separate hardware platform is usedused

here. here.

Run simple but common program which Run simple but common program which generategenerate

outputs.outputs.

Then compare results with those expected.Then compare results with those expected.

6. Integrated Modules 6. Integrated Modules testtest

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Example Code - TLBExample Code - TLBmain() {int* a;int* addr;int i,errors;a=(int*)0x00000010; *a=0x00000000;errors=0;

li(2,0x00000010);lwz(2,2);li(3,0);

for(i=0;i<63;i++){tlbwe(2,3,0);tlbwe(2,3,1);addi(3,3,1);}

li(2,0x00000100);li(3,0);

for(i=0;i<63;i++){tlbre(4,3,0); addi(4,4,0);stw(4,2); addi(2,2,4);tlbre(4,3,1); stw(4,2);addi(2,2,4); addi(3,3,1);}

for(i=0;i<63;i++){addr=(int*)(256+4*i);if(0x00000000!=*addr){

errors++;}

xil_printf(“%d”,errors);}

}}}}

}}}

Initialize Test

Initialize Write Process

Write Process

Initialize Read Process

Read Process

Compare Process

Send result to host

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1.1. Design the hardware structure (MHS Design the hardware structure (MHS file)file)

2.2. Create hardware platform (MMS file - Create hardware platform (MMS file - Platgen stage)Platgen stage)

3.3. Create software platform, i.e. Create software platform, i.e. designated drivers, parameters, designated drivers, parameters, libraries etc. (Libgen stage)libraries etc. (Libgen stage)

4.4. Design software (C-Code)Design software (C-Code)5.5. Compile software (ELF file)Compile software (ELF file)6.6. Combine HW & Software (BIT file)Combine HW & Software (BIT file)7.7. Download to device and run (Impact) Download to device and run (Impact)

Work Flow – Xilinx Work Flow – Xilinx EDKEDK

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Design Tools Used Design Tools Used During The Project During The Project

HDL Designer – Creating hardware applicationsHDL Designer – Creating hardware applications MODELSIM – VHDL simulation MODELSIM – VHDL simulation Synplify – Synthesis tool Synplify – Synthesis tool Xilinx ISE Project Navigator – Place and RouteXilinx ISE Project Navigator – Place and Route Xilinx XPS (EDK) – PPC related testsXilinx XPS (EDK) – PPC related tests Visual C++ – Designing the GUIVisual C++ – Designing the GUI