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C. T. Chuang and P. Su, 04/2010
Variability and Design of SRAM in Scaled and Emerging Technologies
Ching-Te Chuang and Pin Su
Department of Electronics Engineering and
Institute of ElectronicsNational Chiao Tung University
Hsinchu, Taiwan
C. T. Chuang, 10/2008
Part-1: Prof. Ching-Te Chuang
SRAM Design Challenges 6T SRAM Cell and Circuit Techniques Alternative SRAM Cells & Low-Voltage Operation
Part-2: Prof. Pin Su
FinFET vs. Bulk SRAM Analytical FinFET/UTBSOI Subthreshold SRAM Framework SNM of FinFET 6T SRAM Cells Impact of Surface Orientation
Outline
C. T. Chuang and P. Su, 04/2010
Scaling, Read Disturb & Cell Stability Margin
(H. Pilo, ISSCC, 2005)
Iread
C. T. Chuang and P. Su, 04/2010
Conflicting Read/Write Requirements
2( / )
~( / )
AX AX AXREAD
PD PD PD
I W LV
I W L
1
( / )~
( / )p PUPPUP
TRIPPD PD PD
W LIV
I W L
BL BR
WL
‘0’‘1’
PUP
PD
VREAD
VTRIP
AXAX
3( / )
~( / )
AX AX AXWRITE
PUP p PUP
I W LT
I W L
To facilitate Read and minimize Read-disturb (VREAD) Strong PD NMOS and weak AX NMOS (small 2)
To improve Writability (Write margin) Strong AX NMOS and weak PUP PMOS (large 3)
C. T. Chuang and P. Su, 04/2010
Half-Select Disturb
BL BLBR BR
WL0
WL1
COL0 COL1
‘1’ ‘1’ ‘1’ ‘0’
‘0’
‘1’Selected for WRITE
Disturb failure can occur
BL BLBR BR
WL0
WL1
COL0 COL1
‘1’ ‘1’ ‘1’ ‘0’
‘0’
‘1’Selected for WRITE
Disturb failure can occur
During a Read or Write operation, half-selected cells on theselected word-line are actually experiencing “Read” operation Disturb similar to Read-disturb
C. T. Chuang and P. Su, 04/2010
6T SRAM Cell and Circuit Techniques
Thin cell layout Hierarchical bit-lines with short local bit-lines Dual supply Large signal domino-like sensing Unclamped or weakly-clamped local bit-lines Power-gating with header/footer Adaptive Read/Write supply Dynamic Read/Write supply Floating power-line Write Capacitive coupling
Read-assist and Write-assist circuits Suppressed Wordl-Line Negative Bit-Line Self-Adjust/Repair
Exploit device structure (e.g. Asymmetrical Transistor)
C. T. Chuang and P. Su, 04/2010
Example: IBM Power7TM Dcache
(J. Pille et al., ISSCC, 2010)
Dual supply Hierarchical bit-lines with short local bit-lines Unclamped local bit-lines Large signal domino-like sensing
C. T. Chuang and P. Su, 04/2010
Suppressed Word-Line: 1
(K. Nii et al., ISSC, 01/2008)
C. T. Chuang and P. Su, 04/2010
Suppressed Word-Line: 2
(K. Nii et al., Symp. VLSI Circuits., 2008 )
Split-R to mitigate sheet resistance variation
C. T. Chuang and P. Su, 04/2010
Suppressed Word-Line: 3
(Y.Fujimura et al.,ISSCC, 2010)
C. T. Chuang and P. Su, 04/2010
(S. Mukhopadhyay et al., ISCAS, 2008 )
Methods for Reducing Write Failure
C. T. Chuang and P. Su, 04/2010
Two boosting capacitorsconnected directly toeach and every BL pair
Negative pulse also coupled into the BL that held at “High”
Cross-coupled P1 & P2provide a push-pull toreduce the disturbance
NBL timing subject to PVTvariation and VT scatter
Transient Negative Bit-Line: 1
C. T. Chuang and P. Su, 04/2010
Transient Negative Bit-Line: 2
(D. P. Wang et al., Int’l SOC Conf., 2007 )
Single boosting capacitorshared by BL pair
DI determines the transient negative pulse passed to BL or BLB
Timing of the negativepulse is derived withdelay chains and several control signals
NBL timing subject to PVTvariation and VT scatter
C. T. Chuang and P. Su, 04/2010
Transient Negative Bit-Line: 3
Transient NBL action initiated by low-going BL
Timing of NBL pulse muchmore tolerant to variation
Extra inverter needed foreach and every BL
Device count and areaoverhead
(K. Nii et al., Symp. VLSI Circuits., 2008 )
C. T. Chuang and P. Su, 04/2010
Transient Negative Bit-Line: 4
(Y.Fujimura et al.,ISSCC, 2010)
Bit-line capacitance monitor tracks BL discharging time and controls the amount of charges stored in boosting capacitor
Constant NBL level for SRAM compiler applications
C. T. Chuang and P. Su, 04/2010
Self-Adjust/Repair SRAM
(N. Mojumder et al., VLSI Test Symp., 04/2008 & IEEE T-VLSI, 01/2010)
C. T. Chuang and P. Su, 04/2010(J. J. Kim et al., IEEE EDL, 08/2009)
Asymmetrical Transistor in 6T SRAM: 1
C. T. Chuang and P. Su, 04/2010(K. Nii et al et al., ISSCC, 2010)
Asymmetrical Transistor in 6T SRAM: 2
C. T. Chuang and P. Su, 04/2010
6T vs 8T SRAM: Cell Size Scaling
(Y. Morita et al., Symp VLSI Circuits, 2007)
6T cell: Conflicting Read/Write margin requirements Read: Large pull-down NMOS cell Tx & large ratio (pull-down/access width ratio) Write: large access pass-Tx
8T cell: Pull-down NMOS cell Tx can be reduced w/o degrading Read margin Dynamic voltage control enables further scaling
Va for memory cell, Vmax for WWL and RWL 64 Mb 8T SRAM with Vmin = 0.42 V in 90 nm CMOS
C. T. Chuang and P. Su, 04/2010
8T SRAM: Half-Select Disturb during Write
(Y. Morita et al., Symp VLSI Circuits, 2007)(R. Joshi et al., Symp VLSI Circuits, 2007)
During Write, half-selected cells on the same wordline still experience storage node disturb similar to “Read” disturb in 6T SRAM Especially worse for dual supply SRAM with VMAX applied to WWL
Array architecture approach (L. Chang et al., Symp. VLSI Circuits, 2007) No column select. Floorplan such that all bits in a word are spatial adjacent Constraint: Bits from different words can not be physically interleaved 5.3 GHz, 0.41 V Vmin, 32Kb subarray in 65 nm PD/SOI
Gated Write wordline signal (Byte Write) Local Write wordline “on” only for the selected block 6.6+ GHz, 0.4 V Vmin, dual-supply, 1.2 Mb SRAM in 65 nm PD/SOI
Write-back scheme RWL activated even during Write, all cell data in selected WL read out to D-latches Dataout is then written back to half-selected cells 0.42 V Vmin, 64 Mb SRAM in 90 nm CMOS
C. T. Chuang and P. Su, 04/2010
Sub-VT 8T SRAM 256Kb, 65 nm CMOS, 25kHz, 2.83/3.96μW (Read/Write)@ Vmin =
0.35V Buffer-foot with gate-boosted foot driver
(N. Verma and A. P. Chandrakasan, ISSCC, 2007)
C. T. Chuang and P. Su, 04/2010
256Kb 10T Sub-VT SRAM in 65nm CMOS Enable sub-VT Read/Write by lowering leakage from unaccessed cells
For QB=‘0’, Ileak across top RWL NFET ~ 0 For QB=‘1’ Ileak across top RWL NFET ~ 0 with negative VGS
Floating VVDD while boosting WWL by ~ 50-80mV improves V divider 10X, making cell Writable at 0.3V (WL and Write driver operated at 100 mV above VDD;Write is much easier in Sub-VT with exponential dependency of V divider)
475 KHz, 3.28 W @ VDD = 0.4V Leakage reduction
0.6V -> 0.4V: 2.5X ; 0.6V -> 0.3V: 3.8X ; 1.2V -> 0.3V: 60X
(B. H. Calhoun and A. Chandrakasan, ISSCC, 2006)
C. T. Chuang and P. Su, 04/2010
Sub-VT SRAM w. Data-Independent BL Leakage 480 Kb: 120 KHz, 10.2 A @ 0.2V in 130 nm CMOS Data-independent bit-line leakage
(T. H. Kim et al., ISSCC, 2007)
C. T. Chuang and P. Su, 04/2010
32 Kb: 166 KHz@0.25V (Leakage: 1.4 uA for 49 Kb@0.25V) in 90 nm CMOS Vcc,min = 0.16V: 500 Hz, 0.123 W @ 0.16V W_WL shared by cells in a column
Writing a cell does not affect Hold stability of other cells along the same WLAllows bit-interleaving for soft-error immunity
Differential Read w. dynamic DCVSL for better stability and leakage tolerance
10T Sub-VT SRAM w. Bit-Interleaving and Differential Read
(I. J. Chang et al., ISSCC, 2008)
C. T. Chuang, 10/2008
Part-1: Prof. Ching-Te Chuang
SRAM Design Challenges 6T SRAM Cell and Circuit Techniques Alternative SRAM Cells & Low-Voltage Operation
Part-2: Prof. Pin Su
FinFET vs. Bulk SRAM Analytical FinFET/UTBSOI Subthreshold SRAM Framework SNM of FinFET 6T SRAM Cells Impact of Surface Orientation
Outline
C. T. Chuang and P. Su, 04/2010
Ultralow-power applications such as portable devices, implanted medical instruments, and wireless body sensing networks require SRAM operating at low supply voltage below VT.
Degraded functional robustness is a serious concern for subthreshold SRAM.
Conventional Bulk 6T SRAM cell has failed to offer adequate stability in the subthreshold region.
FinFET SRAM for Ultralow-Power Applications
C. T. Chuang and P. Su, 04/2010
Random Mismatch in Bulk Transistors
60 dies in a 300mm wafer measured
G DS
Id1,Vth1, β1
G DS
Id2,Vth2, β2
matching pair in one die
[J. Kuo et al., IEEE TNANO, March 2010]
-80 -60 -40 -20 0 20 40 60 800
5
10
15
20
25
30
C
ount
Vth (mV)
Control Strained Gaussian distribution
PFETLgate=54nm
• The impact of Random DopantFluctuation increases with device scaling because the sensitivity of a transistor increases with decreasing channel volume.
C. T. Chuang and P. Su, 04/2010
0.0 5.0x1017 1.0x1018 1.5x1018 2.0x10180.25
0.30
0.35
0.40
0.45
0.50
0.55W total=75nm, Leff=25nmtHfO2=2nm, VDS=0.05V
AR=0.5
V th (V
)Doping concentration (cm
-3)
AR=1
AR=2
Threshold Voltage Sensitivity to Doping
GateS
D
BOX
Generic Multi-Gate Structure
[Y. Wu and P. Su, IEEE TNANO, May 2008]AR=2 AR=1 AR=0.5
• Small fin-width (Wfin) enhances the gate control and reduces the Vth dependence on channel doping.
Wfin AR = Hfin/Wfin
Hfin
C. T. Chuang and P. Su, 04/2010
BOX(oxide)
tox
Hfin
Lgate
source
drain
Single Fin (W=Hfin)
BOX(oxide)
Hfin
Lgate
pitchsource
drain
Multiple Fin (W=3Hfin)
FinFET
• The device width for FinFET is quantized (integer multiple of Hfin).• In a minimum-sized FinFET SRAM cell, single-fin devices are used.
Wfin
C. T. Chuang and P. Su, 04/2010
FinFET vs. Bulk
• FinFET exhibits steeper subthreshold slope and larger Ion/Ioff ratio than the Bulk counterpart.
0.0 0.2 0.4 0.6 0.8 1.010-14
10-12
10-10
10-8
10-6
10-4
104
Id
[A/
m]
Vg [V]
Bulk Planar FinFET
Vds=0.05, 1.0V
Identical Id,sat
~160X106
NFET
0.0 0.1 0.2 0.3 0.40.0
0.1
0.2
0.3
0.4
RSNM
RSNM
VR
(V)
VL (V)
6T BULK SRAM (=1.5)
6T FinFET SRAM (single-fin, =1.0)
Vdd=0.4V
Lg=25nm, Wfin=7nm, Hfin=20nm, EOT=.65nmVCS
VWL
VBLB VBL
ARAL
NR
PR
NL
PL
VRVL
VCSVCS
VWL
VBLB VBL
ARAL
NR
PR
NL
PL
VRVL
C. T. Chuang and P. Su, 04/2010
FinFET vs. Bulk
• FinFET SRAM cell shows larger Read Static Noise Margin (RSNM) than the Bulk counterpart because of its superior electrostatic integrity.
250 300 350 400
40
50
60
70
80
RSN
M [m
V]
Temperature [K]
w/o self-heating: Bulk SRAM (=1.3) FinFET SRAM
w/i self-heating: Bulk SRAM (=1.3), (=150 W/mK) FinFET SRAM (=15 W/mK)
Vdd = 0.4V
[M.-L. Fan et al., IEEE TED, June 2010]
0.2 0.3 0.4
20
40
60
80
1.5X
1.8X
R
SNM
[mV
]
Vdd [V]
BULK (=1.3) BULK (=1.5) FinFET (=1.0)
Standard 6T SRAM
3.3X
C. T. Chuang and P. Su, 04/2010
FinFET vs. Bulk
• FinFET SRAM cell can be more robust than the Bulk counterpart.
0 0.1 0.2 0.3 0.40
0.1
0.2
0.3
0.4
-20 0 20 40 60 800
10
20
30
40
RSNM [mV]
92.
READ failure
0 0.1 0.2 0.3 0.40
0.1
0.2
0.3
0.4
30 40 50 60 70 80 900
10
20
30
RSNM [mV]
36.
150 samples
Bulk SRAM with RDF
150 samples
FinFET SRAM with Fin LERVdd=0.4VVdd=0.4V
[M.-L. Fan et al., IEEE TED, June 2010]
...
C. T. Chuang and P. Su, 04/2010
Independent-Gate Control Capability of FinFET
GateS
D
FrontGate
BackGate
S
D
Tied Gate Independent Gate
C. T. Chuang and P. Su, 04/2010
Cell (II) : Ying-Yang feedback
Cell (III) : Improved Ying-Yang feedbackCell (IV) : Doubled-WL
RSNM
10
WSNM Adaptively controlled
Several 6T FinFET SRAM Cells
[Z. Guo et al., ISLPED 2005]
[O. Thomas et al., ISCAS 2007]
[M. Yamaoka et al., Symp. VLSI Circuits 2004]
Cell (I): standard tied-gate 6T
C. T. Chuang and P. Su, 04/2010
baxxqN
si
a 21 2
x
WizW
Wicz
Wic
effieff
effeff
sinsinhsinh1
2
1 13 sinsinsinhsinh
m n effeffyy z
Hnx
WmyLkeyke
zyxzxxzyx ,,,,, 321
The drain current can be calculated using the channel potential solution (x,y,z):
2
0
0 0
exp exp
, ,exp
eff
f in fin
i S Dna
DS L
H W
n VkT Vqq N kT q kT q
I dyq x y z
dxdzkT
Analytical FinFET Subthreshold Model
[Y. Wu and P. Su, IEEE TED, Nov. 2008]
C. T. Chuang and P. Su, 04/2010
Vdd
WL
BL BLB
ARAL
NR
PR
NL
PL
VRVL
VddVdd
WL
BL BLB
ARAL
NR
PR
NL
PL
VRVL
b'
SNM = min [ SNML, SNMR]
b
SNMR
a
VR (V
)
VL (V)
longest diagonal aa' , bb'
a'
SNML
VR (V
)
VL (V)
SNMR = bb'/ sqrt(2)
longest diagonal : aa' , bb'
bb'
SNML = aa'/ sqrt(2)
SNM = min [ SNML, SNMR]
aa'
Analytical Subthreshold Drain Current Model
Butterfly Curve by Solving Storage Nodes
Static Noise Margin Calculation
Design Analysis for Various Subthreshold SRAM Cells
Analytical FinFET/UTBSOI Subthreshold SRAM Framework
[V. P.-H. Hu et al., IEEE TED, Sep. 2009]
C. T. Chuang and P. Su, 04/2010
0.0 0.1 0.2 0.3 0.40.0
0.1
0.2
0.3
0.4
WSNM
RSNM
RSNM
VR [V
]
VL [V]
TCAD model
Nominal CellLeff=25nmWfin=7nmHfin=20nmVdd=0.4V
Verification – Scalability & Efficiency
0.00 0.05 0.10 0.15 0.200.00
0.05
0.10
0.15
0.20
Leff=25nmWfin=7nmHfin=20nmVdd=0.2V
VR
[V]
VL [V]
TCAD model
0.0 0.1 0.2 0.3 0.40.0
0.1
0.2
0.3
0.4
Leff=20nmWfin=5nmHfin=15nmVdd=0.4V
VR
[V]
VL [V]
TCAD model
Scaled cell
Lowered Vdd
Nominal cell
[M.-L. Fan et al., IEEE SOI Conf., Oct. 2009]
• Analytical approach not only shows better efficiency than TCAD mixed-mode simulation, but also enables an assessment for sensitivity to process variations.
C. T. Chuang and P. Su, 04/2010
• Cell (II), (III) and (IV) show significant RSNM improvement as compared with cell (I).
• The percentage improvement in RSNM is larger for Subthresholdthan Superthreshold.
• R/W WL voltage control is effective to improve the cell stability of subthreshold SRAM.
Asymmetrical cell (V)Double word-line structure(IV)
Improved Ying-Yang feedback (III)Ying-Yang feedback(II)
Standard tied-gate 6T(I)
RSNM Comparison of 6T FinFET SRAM Cells
0
50
100
150
200
250
300
350
R
SNM
[mV]
Subthreshold (Vdd=0.4V) Superthreshold (Vdd=1.0V)
(I) (II) (III) (IV) (V)
75% 71% 75%
24%
62% 56% 62%
4%
[M.-L. Fan et al., VLSI-TSA, April 2010]
C. T. Chuang and P. Su, 04/2010
• Cell (II) and (III) fail to WRITE at Vdd =0.4V. Boosted WL technique is needed to restore the Write-ability.
• The Write-ability of Cell (IV) is not degraded.
0.40 0.45 0.50 0.55 0.60
-100
-50
0
50
100
150
200
250
VWL=172mV
WSN
M [m
V]WL voltage [V]
Cell (II) Cell (III)
VWL=133mV
-100
0
100
200
300
400
500
600
(V)(IV)(III)(II)(I)write1 write0
-131%-220%
0%
0%61%
-60%
0%
16%0%
-79%
WSN
M [m
V] Subthreshold (Vdd=0.4V) Superthreshold(Vdd=1.0V)
WSNM Comparison of 6T FinFET SRAM Cells
[M.-L. Fan et al., VLSI-TSA, April 2010]
C. T. Chuang and P. Su, 04/2010
Stability of Double-WL FinFET SRAM Cell
• Local random variation (Fin LER) together with global process variations (process corners) are considered by Monte Carlo simulations.
• Double word-line SRAM cell with adequate nominal RSNM can provide sufficient / ratio in RSNM for various process corners (TT = 10.9, FS = 6.4, SF = 13, SS = 14.2, FF = 7.2) at Vdd=0.4V.
Cell (IV) : Doubled-WL
[O. Thomas et al., ISCAS 2007]
02468
101214
FFSSFS SF
/
TT
0 0.1 0.2 0.3 0.40
0.1
0.2
0.3
0.4150 samples
Worst case:FNSP corner
Vdd=0.4V±20% device parameter deviations (Leff and Wfin) are assumed.
C. T. Chuang and P. Su, 04/2010
Impact of Surface Orientation on FinFET SRAM Cell
• For FinFET, the conventional sidewall conducting (110) surface orientation can be rotated by layout to improve the cell stability.
All (110) NMOS (100)
C. T. Chuang and P. Su, 04/2010
Impact of Surface Orientation on FinFET SRAM Cell
0 3 6 9 12 15-0.05
0.00
0.05
0.10
0.15
0.20
0.25
(111)(110)
(100)
Vth
[V]
tch [nm]
Si-NMOS
Leff = 25nmVDS=0.05V
symbols: simulation lines: model
CL
0.00
0.05
0.10
Leff = 25nmtch = 4nmVGS = 0.1V
(111)(110)
E 0
EC
(x=0
) [eV
]
(100)0.0
0.2
0.4
0.6
0.8
1.0
1.2
(110,100) (110,110)(100,110)
Nor
mal
ized
RSN
M
(PD,PG)
PU (110) PU (100)
(100,100)
Vdd=0.4V
C. T. Chuang and P. Su, 04/2010
0.0
0.2
0.4
0.6
0.8
1.0
1.2
(100,110)(110,110)(100,100)
Nor
mal
ized
R
SNM
(PD,PG)
PU(110) PU(100)
(110,100)
Vdd=0.4V
Impact of Surface Orientation on FinFET SRAM Cell
0 3 6 9 12 15-0.05
0.00
0.05
0.10
0.15
0.20
0.25
(111)(110)
(100)
Vth
[V]
tch [nm]
Si-NMOS
Leff = 25nmVDS=0.05V
symbols: simulation lines: model
CL
0.00
0.05
0.10
Leff = 25nmtch = 4nmVGS = 0.1V
(111)(110)
E 0
EC
(x=0
) [eV
]
(100)
C. T. Chuang and P. Su, 04/2010
With superior electrostatic integrity, suppressed random dopant fluctuation, independent-gate control capability and surface-orientation optimization, FinFET SRAM cell can be more robust than the Bulk counterpart.
Conclusion
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