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Update on the Design Implementation Methodology for the 130nm processMethodology for the 130nm process
Microelecronics User Group meetingTWEPP 2010 – Aachen
Sandro BonaciniSandro BonaciniCERN PH/ESE
sandro.bonacini@cern.ch
Motivation
Mixed Signal Design flow methodology Open Access based
Implementation of Digital On Top ASICs Implementation of Digital-On-Top ASICs Script based flow
U i th IBM 130 t d d ll lib Using the IBM 130 nm standard cell library
Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch
Design flow components Tools
Virtuoso 6.1.3 (OA based)( ) SOC Encounter 8.1 (velocity) Conformal 8.1 EXT 8.1.4 (QRC) (Q ) Assura 3.2 Calibre 2009.3
Design Kits IBM CMOS8RF DM design kit V1.7
3 thin 2 thick 3 RF metals 3 thin, 2 thick, 3 RF metals. IBM CMOS8RF LM design kit V1.7
6 thin, 2 thick metals.
Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch
Enhancements
Digital libraryI/O pads I/O pads Implement missing Cadence/Virtuoso views
Functional and symbol views for simulation Fixed existing views
Pin mismatches of power pads Abstract power pin width Layout fixes
New corner cells with 45 degrees bend Standard cells Standard cells
New filler cells conforming to PC & RX pattern density rules New double vias for denser routing / better yield
Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch
Enhancements Implementation flow
Added support for multiple power domains Added support for multiple power domains Analog, digital, …
Support for P&R of mixed signal ASICs and third-party IP blocks Better integration between Virtuoso and Encounter Better integration between Virtuoso and Encounter
Automatic final netlist import into Virtuoso Automated physical verification
DRC and LVS Other fixes
Scan chain reordering Antenna rule definition for Encounter Two-steps routing for DM metal stack to avoid antenna violations
1st pass on 3 metals (only thin) 2nd pass on 5 metals (thin+thick)
Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch
“Digital on Top” Design Flow
SOC_EncounterChip Design
VirtuosoAnalog Block Creation
AcOAc
RTL synthesis
Logical Equivalence
CheckingDFM
Clock tree synthesis
Timing optimization
Automated taskUser task
Logical Equivalence
Checking
RTL synthesis
Logical Equivalence
CheckingDFM
Clock tree synthesis
Timing optimization
Automated taskUser task
Logical Equivalence
Checkingcce
Ope
cce
Floorplanning& power routing
Placement
SignoffRC extraction
Timing
DRC
DFM
LVS
y
Routing
Timing optimization
Floorplanning& power routing
Placement
SignoffRC extraction
Timing
DRC
DFM
LVS
y
Routing
Timing optimization
n ss
Congestion analysis
Timing optimization
Timing analysis
Routing
Tape-out
Congestion analysis
Timing optimization
Timing analysis
Routing
Tape-out
30/3/10 Kostas.Kloukinas@cern.ch 6
Mixed-signal example design A realistic example of a Mixed Signal ASIC
to demonstrate the design flow:
Analog IP block: DAC Digital IP block: SRAM
g
Digital block: I2C slave Synthesizable RTL code Triple Module Redundancyp y
Two separate power supplies Analog, digital Analog, digital
30/3/10 Kostas.Kloukinas@cern.ch 7
Synthesis: RTL Compiler [rc] Timing constraints:
Clock definitions Input delays,
fanout, transition, etc.
Output load, etc.
Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch
Design import: Encounter Reference design used in the AMS
workshop: I2C slave connected to
SRAM DAC (with separate analog power supply) DAC (with separate analog power supply) registers
DACSRAM
Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch
DACSRAM
Floorplanning & power routing
Define Chip/core size Chip/core size target area utilization I/O placement module placement in
case of TMR or othercase of TMR or other special constraints
Power planning/routingp g g Core/block rings and
stripes DAC SRAM
Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch
PlacementOpen AccessFloorplannedDesign [.oa]
Connect cells power/ground
Open AccessFloorplannedDesign [.oa]
Connect cells power/ground
Placement
Scan-chain d
Add tap cells
Placement
Scan-chain d
Add tap cells
reorder
Open AccessPlaced
Design [.oa]
Reports
reorder
Open AccessPlaced
Design [.oa]
Reports
Power/ground connections Tap cells
Standard cells
Scan-chain reordering
Multiple power domains
Analog & digital blocks
Separate power supplies.
Insertion of Power Breaker peripheral pads.
DACSRAM
Clock tree synthesis & signal routing
Open AccessPlaced
Design [.oa]
Timing optimization
Open AccessPlaced
Design [.oa]
Timing optimization
Clock tree synthesis
Routing
Timing optimization
Clock tree synthesis
Routing
Timing optimization
Timing optimization
Open AccessRouted
Design [.oa]
Reports
Timing optimization
Open AccessRouted
Design [.oa]
Reports
Sandro Bonacini - PH/ESE - sandro.bonacini@cern.chClock tree synthesis
Routing onthin metals
Routing on all metals
DFM: Antenna fixOpen Access
RoutedDesign [.oa]
Antenna fix
Via
Final netlist[.v]
Open AccessRouted
Design [.oa]
Antenna fix
Via
Final netlist[.v]
SignoffRC extraction
Cells & metal fill
Via optimization
Open AccessFinal
Design [.oa]SignoffRC extraction
Cells & metal fill
Via optimization
Open AccessFinal
Design [.oa]
Timing analysis
Signoff timingreport
Delay file[.sdf]
Timing analysis
Signoff timingreport
Delay file[.sdf]
Re-routes long nets Inserts tie-down Inserts tie down
diodes
Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch
Via optimization
Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch
Cells & metal fill
Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch
Back to Virtuoso !
ASIC design is present in Virtuosopresent in Virtuoso. Scripts take care of
changing abstracts into real layouts
Automatic import of netlist
DAC SRAM
Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch
Calibre DRC – Assura LVS
Thank you…
Implementation of digital-on-topmixed signal ASICs Using the IBM 130 nm standard cell library Defined methodology compatible with mixed signal Defined methodology compatible with mixed signal
design flows Presented in the AMS courses
Future plansAdd i l i t it h k Add signal integrity checks Celtic
Automate additional DRC checks (ortho/grid, …)
Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch
( g , )
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