The Ultimate System Integration Platform · 2019-11-22 · Simplify PCB Layout •...

The Ultimate System Integration Platform

VIRTEX-5 FPGAs

212986A2 9/19/06 12:15 PM Page 1

THE WORLD’S FIRST 65nm FPGA

One Family—Multiple Platforms

The Virtex™-5 family of FPGAs offers a choice of four new platforms,each delivering an optimized balance of high-performance logic,serial connectivity, signal processing, and embedded processing.

Virtex-5 LXT FPGAs, optimized for high-performance logic with serial I/O, expand the Virtex-5 family offering, joining the Virtex-5 LXplatform devices released earlier. Discover how this new familydelivers even higher performance, lower power, and lower systemcost than previous-generation Virtex-4 FPGAs.

Meet Your Performance Targets Easily

• Achieve a 30% performance gain with newExpressFabric™ technology

• 550 MHz clocking technology and performance-tunedIP blocks

• 1.25 Gbps LVDS I/O: up to 600 pin pairs

Optimize I/O Bandwidth, Power and Cost with Easy-to-Use High-Speed Serial Solutions

• RocketIO™ GTP transceivers deliver 100 Mbps – 3.2 Gbpsserial connectivity

• First FPGA with hardened PCI Express endpoint blocksand Tri-mode Ethernet MACs

• Lowest power in the industry: less than 100 mW per transciever at 3.2 Gbps

• Advanced equalization techniques to drive backplanes beyond 40”

• Protocol solutions kits accelerate development

Beat Your Power Budget while Maximizing Performance

• 35% lower dynamic power with 65nm ExpressFabricand power-saving IP blocks

• Reduce serial connectivity power consumption: RocketIOGTP transceivers consume less than 100 mW at 3.2 Gbps

Perf

orm

ance

LogicFabric

Performance

On-chipRAM

550 MHz

DSP32-Tap Filter

550 MHz

I/O LVDSBandwidth750 Gbps

I/O MemoryBandwidth384 Gbps

Virtex-5 FPGAs Virtex-4 FPGAs Nearest Competitor

Numbers show comparision with nearest competitorBased on competitor’s published datasheet numbers

1.4 x

1.3 x 1.6 x

2.4 x

4.4 x

Industry’s fastest 90nm FPGA benchmark

Virtex-5

212986A2 9/19/06 12:15 PM Page 2

Reduce Cost through System Integration with aSelection of Optimized Platform FPGAs

• Choose a smaller device: 65nm process shrinks die size andnew 6-input LUT increases utilization and efficiency

• Meet aggressive performance targets in the least expensivespeed grade

• Reduce part count with built-in, low-power transceivers • Increase logic efficiency with built-in PCI Express® endpoint

and Ethernet MAC blocks • Select smaller heat sinks, fans, and power supplies enabled

by reduced power consumption • Bring your product to market faster with proven development

and verification tools • Reduce component cost in volume production with Virtex-5

EasyPath™ FPGAs

Finish Your Design Ahead of Schedule

• Achieve FPGA performance goals quickly with ISE™ Fmaxtechnology and PlanAhead™ design analysis tools

• Design faster and reduce risk with over 225 pre-verifiedIP cores

• Reduce debug cycle time with the real-time verification capabilities of ChipScope™ Pro tools

• Build complete embedded processing systems withPlatform Studio and Embedded Development Kit

• Implement DSP algorithms in custom-configured hard-ware with the AccelDSP™/MATLAB™ tool flow

• Accelerate product development with online resources,training courses, and premium support services

• Get Xilinx Productivity Advantage (XPA) bundles of software, education, support services, and IP cores

• Augment your development team with a worldwide network of Xilinx Design Service (XDS) and partner experts

The conversion-free cost-reduction path for volume production.

• EasyPath FPGAs reduce component cost by 30–75%with no risk of conversion, no hidden costs

• Enjoy unprecedented flexibility and fastest turn-around times

VIRTEX-5 EASYPATH™ FPGAs

Solve Signal Integrity Challenges and Simplify PCB Layout

• Second-generation sparse chevron packaging delivers SSOnoise and crosstalk benefits, essential for reliable operationof high-bandwidth parallel interfaces (e.g. memories)

• On-substrate bypass capacitors and a unique pinout simplifyPCB design, improve power integrity, and reduce system cost

• Built-in serial connectivity reduces pin/trace count and eliminates parallel interface design challenges

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The Right Memory for Any Application

Distributed RAM—Small

• Build 256-bit memory per CLB • 64 bits per LUT

550 MHz, 36 Kbit Block RAM—Medium

• Configure Block RAM as multi-rate FIFO• Built-in ECC for high-reliability systems• Automatic power conservation circuitry

389 Gbps External Memories—Large

• ChipSync™ technology for reliable interfaces

65nm ExpressFabric™

Technology

Achieve highest performance, most efficient utilization on 65nm triple-oxide process

• 30% higher speed, 35% lower dynamic power,and 45% less area than the previous generation

• Industry’s first LUT with six independent inputs for fewer logic levels

• Flexible LUTs are configurable as logic, distributed RAM or shift registers

• Advanced diagonally symmetric interconnect enables shortest,fastest routing

• From 30,000 to 330,000 logic cells for system-level integration

THE ULTIMATE SYSTEM

INTEGRATION PLATFORM

550 MHz Clocking Technology

Achieve highest speeds with high-precision, low-jitter clocking

• 12 DCMs provide phase control of less than 30 ps for better design margin

• 6 PLLs reduce reference clock jitter by more than 2x• Differential global clocking ensures low skew and jitter

Virtex-5

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Ethernet Media Access Controller:10/100/1000 Mbps

Connect to the Internet via an integrated tri-mode EMAC

• UNH-verified compliance • Built-in hard IP frees user logic resources and reduces power • Four Ethernet MAC blocks on every Virtex-5 LXT device

RocketIO™ GTP Transceivers:100 Mbps–3.2 Gbps

Implement serial protocols atlowest power

• Flexible SERDES supports multi-rateapplications

• Designed to work with integratedPCIe™ and EMAC blocks

• 77% lower power consumption:<100 mW at 3.2 Gbps

PCI Express® Endpoint Block:1/2/4/8-lane

Built-in support for ubiquitous serial connectivity standard

• PCI SIG-verified compliance (on integrators list) • Works with RocketIO GTP transceivers to deliver

full PCIe endpoint function • Built-in hard IP frees user logic resources and

reduces power

Sparse Chevron Packaging Technology

Keep system noise under control and simplify PCB layout

• Unique PWR/GND pin pattern minimizescrosstalk and reduces PCB layers

• On-substrate bypass capacitors shrink PCB area

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Enhanced Configuration and Bitstream Protection

Reduce system cost, increase reliability,and safeguard your design

• Configure with commodity SPI and parallel flash memory • Easier partial reconfiguration and smaller frame size• Greater reliability for in-system reconfiguration with

multi-bitstream management • Protect your designs with 256-bit AES

(Advanced Encryption Standard) security

550 MHz DSP48E Slice

Create high-performance DSP systems

• New 25 x 18 multipliers enable single-precision floating-point math and wide filters with fewer slices

• Configurable for DSP, arithmetic, and bit-wise logic • Enables efficient adder-chain architectures• 40% lower power consumption: 1.38mW/100MHz at

a 38% toggle rate

1.25 Gbps SelectIO™ with ChipSync™ Source-SynchronousTechnology

Implement industy-standard and custom protocols

• Simplify board design with built-in input delay andnew output delay circuits that compensate forunequal trace lengths

• Adaptive delay setting recalibrates automatically tocompensate for changing operating conditions

• Interface to popular standards with 1.25 Gbps differential and 800 Mbps single-ended I/O

• Digitally controlled impedance reduces componentcount and board size

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µP ASSP

CLK1

CLK2

CLK5

CLK6

CLK3 CLK4

Implement Parallel Networking and System Interface Standards

SelectIO circuitry, combined with pre-verified IP cores,make it easy to support all popular interface standards

• 1.25 Gbps LVDS, 800 Mbps single-ended • Interface or bridge to virtually any external component • Support multiple electrical standards in the same device with

35 individually configurable I/O banks• Design with PCI, RapidIO, XSBI, SPI4.2, and more • Configure I/Os to support HSTL, LVDS (SDR and DDR), and more,

at voltages from 1.2V to 3.3V

A SOLUTION FORDESIGN CHALLENGE

Accelerate Development with Complete Serial Solutions

Build chip-to-chip, board-to-board, and box-to-box applications quickly and easily

• Obtain assured compliance with popular standards • Reduce design time with integrated interface blocks and

pre-verified IP • Implement custom solutions • Reduce pin/trace count to simplify board design and reduce

manufacturing cost • Start designing with ready-to-use solution kits including protocol-

specific characterization reports, boards, and simulation models

Bridge Protocols

Protect your investment by interfacing easily to legacy ASSPs or ASICs

• Reduce design time with built-in support for PCI Express and Ethernet • Implement other popular protocols with pre-verified IP • Connect external peripheral components to any processor with

standards-compliant I/O

Simplify Source-Synchronous Interfacing

ChipSync technology in every SelectIO block provides precise control over critical timing for high-performancesource-synchronous interfaces

• Achieve performance targets and simplify PCB layout with flexible per-bit deskew

• Synchronize incoming data to FPGA internal clock with built-inSerializer/Deserializer

Build Highest-Bandwidth Memory Interfaces

ChipSync technology and the Memory Interface Generatortool make it easy to build reliable interfaces to the latesthigh-performance memories, including:

Data Rate(Mbps)

400

667

600

600

MemoryInterface

DDR SDRAM

DDR2 SDRAM

QDR II SRAM

RLDRAM II

Data Width(# of bits)

576

576

2 x 324

648

Bandwidth(Gbps)

230

384

389

389

Telecom OC-3 CPRI CPRI CPRI SFI-5

0.5 1.0 1.5 2.0 2.5 3.0 3.5Data Rates (Gbps)

0.0

OC-12

Networking 1GbE XAUI10G Base-CX4

Storage FibreChannel FibreChannelSATA, SAS

Video SDIDVB-ASI HD-SDI HD-SDI

SATA, SAS

OBSAI

Computing PCIeInfiniband

SRIO SRIOSRIO

OBSAI OBSAISFI-5OC-48

Virtex-5

212986A2 9/19/06 12:16 PM Page 7

Implement PCI Express with Reduced Cost,Power, and Complexity

Minimize design risk with hardened PCIe blocks to connect tonext-generation graphics, storage, networking, and I/O devices

• Integrate multiple functions into a single PCIe-enabled FPGA • Preserve software investment and extend infrastructure life with

scaleable bandwidth (x1, x2, x4, x8) • Re-target designs without changing your PCIe interface implementation

as your project evolves

EVERY PLATFORM

Accelerate development with ready-to-use solution kits

• Protocol compliance reports • Device characterization • Reference designs • Development boards• Simulation models • Pre-verified IP • Development tools • User documentation • Partner solutions

PCI Express Design Example: High-End Desktop/Server System

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Multi-ChannelMemory

Controller

Multi-ChannelMemory

Controller

OPBMemory

Controller

OPBMemory

Controller

OPBPeripherals

On-chip Peripheral Bus (OPB)

Block RAM

HW/SWAccelerator

Integrate a Soft Embedded Processor

Embedded development tools and IP make it easy to builda processor subsystem tailored to your requirements

• Start with the MicroBlaze™ soft processor core• Add an IBM CoreConnect™ bus for flexible connectivity and

guaranteed performance• Connect a custom hardware accelerator through the fast

simplex link (FSL)• Complete your subsystem with pre-verified peripheral IP cores

Create Efficient, High-Performance DSP Systems

Increase DSP algorithm performance

• Implement video compression, digital up/down conversion, singleinstruction multiple data (SIMD) functions, and filters efficiently

• DSP processor acceleration with FPGA pre/post/co-processing • ExpressFabric enables fine granularity data shifting and control, and

small bit-width arithmetic functions• Dynamically control DSP48E to create more than 40 functions, such as

Mult/MAC, Add, and Mux, without consuming other resources • Build filters with cascadable DSP48E slices that eliminate the

performance bottlenecks imposed by traditional adder trees

RocketIO GTP transceivers enable efficient data transport whenusing Virtex-5 LXT FPGAs for DSP acceleration

• Interface to latest DSP processors with RapidIO and free up band-width on system memory bus

• Ideal for HD video, baseband co-processing in wireless base stations, and adding image processing acceleration to surveillance cameras and remote servers

DSP and Serial I/O Design Example: Video-Over-IP

212986A2 9/19/06 12:16 PM Page 9

Corporate Headquarters

Xilinx, Inc.

2100 Logic Drive

San Jose, CA 95124

Tel: 408-559-7778

Fax: 408-559-7114

Web: www.xilinx.com

Europe Headquarters

Xilinx

Citywest Business Campus

203 Brooklands Road

Saggart,

Co. Dublin

Ireland

Tel: +353-1-464-0311

Fax: +353-1-464-0324

Web: www.xilinx.com

Japan

Xilinx, K. K.

Shinjuku Square Tower 18F

6-22-1 Nishi-Shinjuku

Shinjuku-ku, Tokyo

163-1118, Japan

Tel: 81-3-5321-7711

Fax: 81-3-5321-7765

Web: www.xilinx.co.jp

Asia Pacific Pte. Ltd.

Xilinx, Asia Pacific

No. 3 Changi Business Park Vista,

#04-01

Singapore 486051

Tel: (65) 6544-8999

Fax: (65) 6789-8886

Web: www.xilinx.com

The Programmable Logic CompanySM

www.xilinx.com

©2006 Xilinx Inc. All rights reserved. The Xilinx name and logo are registered trademarks, and The Programmable Logic Company is a service mark of Xilinx Inc. All other trademarks are theproperty of their respective owners.

Printed in U.S.A. PN 0010938-1

TAKE THE NEXT STEPVisit us online at www.xilinx.com/virtex5

Notes: 1 EasyPath™ solutions provide a conversion-free cost reduction path for volume production.2 A single Virtex-5 CLB comprises two slices, with each containing four Real 6-input LUTs and four Flip-Flops (twice the number found in a Virtex-4slice), for a total of eight 6-LUTs and eight Flip-Flops per CLB.

3 Virtex-5 logic cell ratings reflect the increased logic capacity offered by the new Real 6-input LUT architecture.4 FFA Packages: flip-chip fine-pitch BGA (1.00 mm ball spacing).5 Number of available RocketIO™ multi-gigabit transceivers (MGTs) for each device/package combination shown in parentheses.6 I/O standards supported: HT, LVDS, LVDSEXT, RSDS, BLVDS, ULVDS, LVPECL, LVCMOS33, LVCMOS25, LVCMOS18, LVCMOS15, LVTTL, PCI33, PCI66,PCI-X, GTL, GTL+, HSTL I (1.2V,1.5V,1.8V), HSTL II (1.5V,1.8V), HSTL III (1.5V,1.8V), HSTL IV (1.5V,1.8V), SSTL2 I, SSTL2 II, SSTL18 I, SSTL18 II

7 Virtex-5 commercial grade devices come in three speedgrades: -1, -2, -3 (-3 being the fastest). 8 Virtex-5 industrial grade devices come in two speedgrades: -1, -2 (-2 being the fastest).

LX30XC5VLX30

–

80 x 30

4,800

30,720

19,200

320

32

1,152

42400

13

Yes

200

320008.4

220

400

LX50XC5VLX50

–

120 x 30

7,200

46,080

28,800

480

48

1,728

126560

17

Yes

280

48000

12.6

220

440

560

CLB Resources

Mem

oryResources

Clock Resources

I/O Resources

6

Embedded

Hard IP

Resources

Part Num

ber

EasyPath™

Cost Reduction Solutions 1

CLB Array Size (Row x Colum

n)

Slices 2

Logic Cells 3

CLB Flip-Flops

Maxim

um Distributed RAM

(Kbits)

Block RAM/FIFO

w/ECC (36 Kbits each)

Total Block RAM (Kbits)

Digital Clock Manager (DCM

)

Phase Locked Loop (PLL)/PMCD

Maxim

um SelectIO

™Pins

SelectIO™

Banks

Digitally Controlled Impedance

Maxim

um Differential I/O

Pairs

DSP48E Slices

PCI Express Endpoint Blocks

10/100/1000 Ethernet MAC Blocks

RocketIO™

GTP Low

-Power Transceivers

Configuration Mem

ory (Mbits)

Package 4A

reaIO

MG

T 5

FF32419 x 19 m

m220

FF67627 x 27 m

m440

FF115335 x 35 m

m800

FF176042.5 x 42.5 m

m1200

FF66527 x 27 m

m360

8

FF113635 x 35 m

m640

16

FF173842.5 x 42.5 m

m960

24

LX85XC5VLX85

XCE5VLX85

120 x 54

12,960

82,944

51,840

840

96

3,456

126560

17

Yes

280

48000

21.8

440

560

LX110XC5VLX110

XCE5VLX110

160 x 54

17,280

110,592

69,120

1,120

128

4,608

126800

23

Yes

400

64000

29.1

440

800

800

LX220XC5VLX220

XCE5VLX220

160 x 108

34,560

221,184

138,240

2,280

192

6,912

126800

23

Yes

400

128000

53.1

800

LX330XC5VLX330

XCE5VLX330

240 x 108

51,840

331,776

207,360

3,420

288

10,368

126

1,200

35

Yes

600

192000

79.7

1200

VIR

TEX-5 FA

MILY

VIR

TEX-5 LX

PLATFO

RM

Optim

ized for High-performance Logic

VIR

TEX-5 LX

T PLATFO

RM

Optim

ized for High-performance Logic w

ith Low

-power Serial Connectivity

LX30TXC5VLX30T

–

80 x 30

4,800

30,720

19,200

320

36

1,296

42360

13

Yes

180

321489.4

360 (8)

LX50TXC5VLX50T

–

120 x 30

7,200

46,080

28,800

480

60

2,160

126480

17

Yes

240

481412

14.1

360 (8)

480 (12)

LX85TXC5VLX85T

–

120 x 54

12,960

82,944

51,840

840

108

3,888

126480

17

Yes

240

481412

23.3

480 (12)

LX110TXC5VLX110T

XCE5VLX110T

160 x 54

17,280

110,592

69,120

1,120

148

5,328

126680

23

Yes

340

641416

31.1

640 (16)

640 (16)

LX330TXC5VLX330T

XCE5VLX330T

240 x 108

51,840

331,776

207,360

3,420

324

11,664

126960

35

Yes

480

1921424

82.7

960 (24)

212986A2 9/19/06 12:16 PM Page 10

Cover

Back Cover

page 2, 3

page 4, 5, 6 (Main spread)

page 7, 8, 9