SpiNNaker - a million core ARM-powered neural...

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SpiNNaker - a million coreARM-powered neural HPC

The Advanced Processor Technologies Group

Cameron Pattersoncameron.patterson@cs.man.ac.uk

School of Computer Science, The University of Manchester, UK

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Outline

Motivation

SpiNNaker Architecture

Machines

Software

State of the Nation

Conclusions and Futures

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Motivation

Ubiquity of parallelism

The human brain is the best example

Grand challenges

UK: “GC5: Architecture of Brain and Mind”

Can we learn from the brain?

As a processor technologies group

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Brains demonstrate:massive parallelism (1011 neurons)

massive connectivity (1015 synapses)

excellent power-efficiency

low-performance components (~ 100 Hz)

low-speed communication (~ metres / s)

adaptivity – tolerant of component failure

autonomous learning

The Biological Brain

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Simplified Structure

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Taking Inspiration

The Grand Challenges - work both ways

By mimicking the brain, can we understand it?

Use it to perform 'unethical' experiments

Improve treatment regimes

Can we learn lessons from the biology?

Apply to parallel computing e.g.

Energy efficiency

Fault-tolerance

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Artificial Neural Nets

Taxonomy

Three generations of neural modelling

Granularity of Simulation

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Outline

Motivation

SpiNNaker Architecture

Machines

Software

State of the Nation

Conclusions and Futures

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Network Scaling

Large-scale ANNs require lots of neuronsSpiNNaker's aim is 1 billion plausible neurons

Large-scale ANNs require lots of bandwidthIn the brain discrete 'wiring'

Resulting in:109 neurons * 10 Hz * 103 synapses = 1013 (10 trillion) network events / s

Often the limiting factor for large simulations

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Biology vs Electronics

Luckily biology is 'slow' & electronics 'fast'

This is exploited in SpiNNaker

Model multiple neurons/synapses on a core

SpiNNaker models neurons in software on ARM

Quantity depends on fidelity required

Route spikes using AER

SpiNNaker has a rich interconnection fabric

Su pports very large number of small packets (spikes)

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SpiNNaker Principles

Energy frugality

Low-power processors – ARM, embedded

GALS (Globally Asynchronous, Locally Synchronous)

Event-Driven

Redundancy18 cores per chip

6 links per chip

Real-time modelling

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SpiNNaker Project

Multi-core SpiNNaker nodes

18 ARM968 cores

Programmable

Interconnects

Scalable up to 216 nodes in a system

over a million processors

>108 MIPS total

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Flattened Topology

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System On a Chip

Async Ext. Links

2 Async NoCs Comms

Packetised via Router

SystemShared resource

In package RAM

Ethernet

18 Proc. Nodes

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Processor Node

ARM968E-SSynthesizable

Fixed Point

“Efficient”

32KB & 64KB instruction/data

Local peripheralsCustom DMAC

JTAG

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Fabricated CMPUMC 130nmDie area - 101.64 mm2

>100 million transistors Power consumption:

1W at 1.2V, 180MHz

Peak performance ~4 GIPS

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Choice of process technologyUMC 130nm 1.2V 1P8M Fusion process

Standard Performance & Low Leakage libraries

Mature, competitively priced

Physical LayoutAsync logic crafted with commercial EDA tools

Customized macrocells for key asynchronous circuits

Chip Design Considerations 1

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Power OptimizationLow power embedded processors

Relatively low frequency – 180 MHz

32-bit fixed point arithmetic

Mobile DDR SDRAM

Idle processor cores put to sleep mode

Architecture and logic-level clock gating

Power-aware synthesis throughout the design flow

Chip Design Considerations 2

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GALS Clocked Islands: 2 * cores @ 180MHz, router @ 180MHz, system

peripherals @ 100MHz, SDRAM @ 166 MHz

Fault Tolerance and MonitoringRedundancy: 18 cores, 6 bidir. I/O links, 2 PLLs

Runtime diagnostics, temps and reconfiguration

Diagnostic comms along with application traffic

Comms NoC – parity and framing error detection

DMA – optional CRC

Emergency Routing – for inter-chip comms failures

Chip Design Considerations 3

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Emergency Routing

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Outline

Motivation

SpiNNaker Architecture

Machines

Software

State of the Nation

Conclusions and Futures

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SpiNNaker Board

3rd Generation SpiNNaker board

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4th Generation Board

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Hexagonal PCB structure

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SpiNNaker Machines

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Outline

Motivation

SpiNNaker Architecture

Machines

Software

State of the Nation

Conclusions and Futures

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Software on SpiNNaker

SpiNNaker primarily for ANNsNot limited to this

Finite Element Analysis

Ray Tracing

Heat Diffusion

All require mapping from the problem space/graph to the machine itself

As this scales, the problem gets significant

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Mapping Paths

PlaceRoute

SplitterA B C

Desc.Desc.

2 paths being developed for large machines

PACMAN – for mapping models to hardware

Partition And Configuration MANager

Machine and Model Libraries

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Neural Simulation

Processors16 application + 1 monitor (+1 spare)

Simulate ~1000 neurons/proc.

SDRAM holds synaptic dataBrought to core by DMA across System NoC

Spikes coded as packetsBespoke router with multicast & point-to-point routing tables

and emergency routing mechanism

Source-addressed MC 'spike' packets over Comms NoC

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Software Operation

API provides h/w abstraction for modelling3 main events ANN software deals with:

Packet Received

Buffer and request DMA

DMA Event

Read / update synapse table

Timer Event

Calculate and update neurons

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Example ANN Problem

Constraint:10 neurons / core

(due to mem/cpu etc.)

A splits into 2 coresMapped to core 1&2

B, C and D map to 3-5

1:1

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All:All

4 25% 12 4

50%

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A

B

DC

Routes: 1↔3 & 2↔3 (A↔B), 1↔5 & 2↔5 (A↔D), 3↔5 (B↔D), 4↔5 (C↔D).

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PyNN Integration

PACMAN

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Real-Time I/O 1

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Real-Time I/O 2

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Real-Time I/O 3

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Outline

Motivation

SpiNNaker Architecture

Machines

Software

State of the Nation

Conclusions and Futures

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Full 18-core chip: arrived May 2011

4th Gen Card: 48 chips, 864 processors June 2012

Neuron models: LIF, Izhikevich, MLP

Synapse models: STDP, NMDA

Networks: PyNN, NEF (Nengo) -> SpiNNaker

various small tools to build Router tables, etc

Plans: 104 machine (Q4 2012), 105 (1H 2013), 50,000-chip 106 machine (Q3 2013).

Current Project Status

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Outline

Motivation

SpiNNaker Architecture

Machines

Software

State of the Nation

Conclusions and Futures

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SpiNNaker MPSoC Power-efficiency

Scalable communications

Programmability

Fault-tolerance

SpiNNaker machine

Massively-parallel, programmable platform

Aim to help neuroscientists to explore and understand information processing mechanisms in the brain

Other parallel applications too

Conclusions

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Manchester Team

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Any Questions

?http://apt.cs.man.ac.uk/projects/SpiNNaker/

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