SCHEDULING AND TIMING ANALYSIS OF HW/SW ON-CHIP COMMUNICATION IN MP SOC DESIGN

SCHEDULING AND TIMING ANALYSIS OF HW/SW ON-CHIP COMMUNICATION IN

MP SOC DESIGN

2

Contents

Introduction

Motivation

Communication Scheduling and HW/SW

Timing Analysis

Experimental Results

Conclusion

3

On-chip Communication Architecture in MP SoC design

On-chip Communication Design Design of HW/SW Communication Architecture Mapping and scheduling of on-chip communication

Contribution of this work is the consideration of both of Dynamic behavior of SW communication architecture Physical communication buffer sharing

Introduction

4

Preliminaries

Mapping/Allocation

Communication Scheduling

5

Motivation

6

Extended Task Graph (ETG)

7

Communication Delay Model

Communication Delay

Communication Delay of SW Communication Architecture

Communication Delay of HW Communication Interface

Communication Delay of On-chip Communication Network

(n)C(n)C(n)C(n)C OCN

i

HW

i

SW

ii

)()()( nC(n)C(n)CvR(n)C DDCSISRiSW

i

Interface) ionCommunicat HW of delay(n(n)C HW

i

BLOCKEDtrans

OCN

i DnD(n)C

8

ILP for Scheduling Communication Nodes and Tasks of ETG Data dependency constraints

Resource contention constraints

– Processor and on-chip communication network

Communication Scheduling and Timing Analysis

startendstartend tttt 3121 and

9

ILP for Binary variable

– Physical communication buffer contention constraints

10

List scheduling

Heuristic Algorithm

LIST (G(V,E),a) {

I=1;

Repeat {

For each resource type k=1,2,…., nres {

Determine candidate tasks

Determine unfinished tasks

Select nodes, such that

Schedule the tasks at time

by setting

}

} until ( is scheduled);

Return (t);

}

;,1 kkk aTS

;, kIU

;, KIT

KIk US ,

kS I

):(, ki SviiIt

nv

11

Experiments

12

Experimental Results

Execution delay of tasks in the H.263 system

Delay of software communication architecture Software communication architecture delay measured by ISS.

Functional Block Execution Cycle

Source 1386

Motion predictor

1123650

Macro block 875358

Encoder 875358

VLC 2103156

Services Execution Cycle

ISR 857

CS 1060

DD(read) 5376

DD(write) 6528

13

Execution Time of H.263 encoder

14

Execution Time of JPEG and IS-95 example

15

On-chip Communication Design Design of HW/SW Communication Architecture Mapping and scheduling of on-chip communication

Communication Scheduling and Timing Analysis ILP Formulation Heuristic

Consideration of Dynamic behavior of SW communication architecture Physical communication buffer sharing

Future Work To extend the approach to the complicated On-Chip Network To design On-Chip Communication Scheduler

Conclusion

Thank you ^^