Role of Op-Amps

1Analog and Mixed-Signal VLSI Design Center

IOWA STATE UNIVERSITY

Role of Op-Amps

• widely used building blocks for analog circuits

• widely used in communication circuits• Widely used in analog signal processing

– critical block for data-converters• Widely Used in High Volume ICs

– memory read out– Disk-driver reading-writing

New challenges in Analog Design

• Decreased Supply Voltage• Increased Digital/Analog Interference• Reduced Testability• Increased Parametric Variations

Critical Specifications for Op-Amps

• High DC Gain• High Speed/Large Gain-Bandwidth • Sufficient Output Swing• High power efficiency

Desirable: digital built-in-self-test and self-calibration

Existing structures & Limitations

Cascode AmplifierDC Gain: Modest

Speed: Excellent

Output Swing: Small

Power Efficiency: Good

Frequency Response: Good

Cascaded AmplifierDC Gain: High

Output Swings: Large

Speed: Poor

in outA1 A2 A3

Frequency Response: Poor

Positive Feedback AmplifierDC Gain: Large

Output Swing: Good

Speed: High

Low Yield

Frequency Response: Good

Vi1 Vi2

Vbp Vbp

Vo1 Vo2

Our Objective

• Low Voltage Compatible• High DC Gain• High Speed• Good Output Swing• High Yield• Standard Digital Process Compatible• Good Power Efficiency

Our Approach

• Find new amplifier architectures• Rely on digital logic to enhance

performance• Use simple digital circuit sensing amplifier

performance• Integrate controllability• Use adaptive feedback control

Positive Feedback Gain-Boosting

• Can operate at very low voltages• Can achieve very high DC gain• No compromise in bandwidth• No appreciable power increase• Conventional wisdom has two concerns

– positive feedback leads to RHP poles– gain boosting is limited if requiring robustness w.r.t.

process variations

Our response to the concerns

• positive feedback causes RHP open-loop poles, but do not necessarily cause RHP closed-loop poles!

• RHP open-loop poles can actually improve performance of closed-loop amplifiers!

• F16/F18 fighter jets have open-loop RHP poles, they play critical role in achieving their superior closed-loop performance

• no need for robustness across process variations• use positive feedback pole control after fabrication

Positive Feedback Operational Amplifiers

+Vd VoutA(s)

+Vd Vout

Open loop transfer function ps

pAA(s)

Closed-loop transfer function βGBps

GBβA(s)A(s)(s)Af

Open-loop pole: Closed-loop pole: βGBppf p

Positive Feedback Amplifier Architecture Exploration

• Some positive feedback amplifier architectures have a dc gain that is much more sensitive to the feedback control variable than others

• Although architecture optimality may be difficult to determine, synthesis techniques may yield better structures than those already considered

• Comparative study of several structures with existing positive feedback structures

A)(1gggsCg(s)A

dsnds2ds1L

Vbias1 Vo

ADC = gm1

gds1+gds2- (A-1)gdsn

As (A-1)gdsn → gds1+gds2,

ADC → ∞ !

Negative Output Conductance Op Amp

Implementation Block Diagram

Bias Generator

Vin Von

VopBasic Amp

2nd stage

Negative Conductance GeneratorVi-

2nd stage

First Stage

Basic Amplifier and the Second Stage

Basic amplifier Second stage

VCMVBN

Von Vop

Negative Conductance Generator

VopVon

Mg1Mn1

Vi+ Vi-

VXX VXX

Low Gain Stage A

VopMa1

Ma2Von

Positive Feedback Amplifier Architecture Exploration

f1(-θ1VA-θ2VB-θ3VOUT)

Overhead for realizing this structure can be very small

IOWA STATE UNIVERSITY 43212122

433343

2221 )(

omoooombm

oombmoo

gkggggggggggggg

Vi1 Vi2

Example positive feedback amp1:

212122

433343

oooombm

oombmoo

gggggggggggg

Gain = infinity

IOWA STATE UNIVERSITY 2122

gggggkg

gggggg

gggggggg

Vi1 Vi2

Vo1 Vo2

gggggg

Gain = infinity

Vi1 Vi2

422122

433343

2221 )(

oooombm

oombmoo

gggggg

gkgggggggggggg

212122

433343

oooombm

oombmoo

ggggggg

gggggggggggg

Gain = infinity

Vi1 Vi2

314333

212221

2221 )(

oooombm

oombmoo

gggggg

gkgggggggggggg

314333

434333

212221

oooombm

oombmoo

gggggg

gggggggggg

Gain = infinity

DC Sweep of amp1 in 0.1um process

-6 -4 -2 0 2 4 6x 10-3

differential input(V)

A High Gain Positive Feedback Amplifier in 0.1um Process

Preliminary Results: DBISTSC PFAmp

A Digital Programmable Amplifier

Bifurcation in Positive Feedback Amplifier

Simulation and Measurement Results

A digital controllable Amplifier•Low-Voltage Compatible

3 transistors from VDD to VSS

•High GainAttenuator provides positive feedbacknegative-conductance compensation

•High SpeedSingle Stage

Vo1 Vo2 CL CL

Small Signal Linear Equivalence

21 ii VVx

21 oo VVy gopgongmnx

xsCL-gmpy

0mpoponL

gggsCgA

Nonlinear Dynamic

04})](1[)(4{ 232 xgyxVVgggy mnSOCMnnnmponoppp

SOCMnnn

mponop

)](1[4

Dynamic equation

Equilibrium manifold (DC Transfer)

Amplifier’s DC Characteristics

0.020.021

-0.1 -0.05 0 0.05 0.1-1.5

0=0.02=0

=0.021

Amplifier’s DC Characteristics

>0 Hysteresis

No Hysteresis

Decrease L Gain

Hysteresis

Observations

Phase Diagram in Y- Plane

0.017 0.018 0.019 0.02 0.021 0.022 0.023-1

unstable

stable

0.018 0.019 0.02 0.021 0.022 0.023 0.024-1

*x=-0.001

0.018 0.019 0.02 0.021 0.022 0.023 0.024-1

*x=0.001

Observations

>0 Bifurcation

For some given x, 3 solutions for y2 stable and 1 unstableFor some given x, one unique solution for y

0 No Bifurcation

For a given x, one unique solution for y

Pull up/Pull down Circuit

-0.5 0 0.5-1.5

yDiscontinouity

Stable

Unstable

Stable

pullup pulldown

-0.5 0 0.5-1.5

yDiscontinouity

Stable

Unstable

Stable

Pull down, stay low

OHOL=10

Pull up/Pull Down

Pull up, stay high

-0.5 0 0.5-1.5

yDiscontinouity

Stable

Unstable

Stable

Pull down, return high

OHOL=11

Pull up/Pull Down

Pull up, stay high

-0.5 0 0.5-1.5

yDiscontinouity

Stable

Unstable

Stable

Pull down, stay low

OHOL=00

Pull up/Pull Down

Pull up, return low

Sensing Processpull up

release

record OH

pull down

release

record OL

OHOL=?

no bifurcation bifurcation detected

11/00 10

Linear MOS Attenuator

111 k1.

3. controlled by Aspect Ratio Vo

221 //

4. k controlled by Aspect Ratio

5. Infinite input impedance at DC

Adaptively Controllable Attenuator

1.Quiescent-voltage shifting

)11( 132 kk2.

3.Decreased Sensitivity to transistor size change

: input code <d6…d0>

Programmable Attenuation

0 20 40 60 80 100 120 1400.016

Gain Enhancement Requirement

gA)]([ 0

Gain is related to controllable Attenuator

Required Attenuator Control Code

Achievable Gain Lower Bound

mm or 02

Design Specification for Attenuator DAC

1. Sufficient Coverage)2()0( 1

max0min0N

2. Fine Resolution

specAN

1)}()1({max120 1

3. DAC Size

min0max012 N

Effect of Offset on Sensing

-0.1 -0.05 0 0.05 0.1-1.5

offset

Offset Compensated Sensing Circuit

pull up pull down

DACcomparator O

Design Specifications for input DAC

1. Sufficient Coverage)2()0( 2

maxminNOffsetOffset

2. Fine Resolution

specLN

)}()1({max120 2

3. DAC Size

OffsetOffset minmax22

Design Specifications

-0.1 -0.05 0 0.05 0.1-1.5

=0.021

Aspec:80dB

Lspec:20V

:0.0001

offset variation:50mV

0variation:0.006N16

Combined Sensing and Control Logic

• Implement with inexpensive digital logic• Time-efficient processing• Accomplish offset compensation• Realize optimal control code searching• Adaptive feedback control

Functional Block Diagram

pull up pull down

ComparatorO

branching parameter controland offset cancellation

cal/un

Nested attenuation/bifurcation control

initialize

=(L+H)/2

bifurcation detection

Bifurcation?

: Attenuator DAC input

yes no

step=N1?yes

finish searching

inner loop

Bifurcation Detection Algorithm

initialize

=(L+H)/2

Pull-up/Down

OHOL=? bifurcationdetected

: Input of offset compensation DAC

break L= 11

no2N2+1input codes

step=N2?yes

break withoutbifurcation

Convergence Proof

Conditions on offset-DAC range guarantee initial conditions:

offset

at step 01.When =L=0, OHOL=112.When =H=2N2,

OHOL=003. (L)< offset (H)4. H-L=2N2

Convergence Proof (Continue)• at step k+1,

=(L+ H)/2, pull up/down

– if OHOL=10, bifurcation is detected, break

– if OHOL=11, ()<offset, let L=

– if OHOL=00, ()offset, let H= – if bifurcation is not detected, continue.

• then (L)< offset (H) H - L=2N2-(k+1)

– At L, OHOL=11; at H ,OHOL=00• This iteration ends either with ‘bifurcation detected’ or ‘step=N2’

without bifurcation.

Convergence Proof (Continue)• If step=N2, H-L=1 (L)< offset (H)

• when =L, OHOL=11, (L)< lower bound of hysteresis

• when =H, OHOL=00, (H)> up bound of hysteresis

• Lhys>(H)- (L)offset

(L) (H)

potential

hysteresis width

lower bound up boundLhys

Convergence Proof (Attenuator)

control code

Converge tobifurcation

nobifurcation

Conditions on -DAC range guarantee initial conditions:at step 01.When = L=0, no bifurcation

2.When = H=2N1, bifurcation

3. (L)0< (H)4. H- L=2N1

Convergence Proof (Attenuator)•step k+1: (L)0< (H), H- L=2N2-k •let =(L+ H)/2, do ‘bifurcation detection’•if bifurcation is detected, ()> 0 ,let H= •else let L= •at both situations, (L)0< (H), H- L=2N1-k-1

Convergence Proof (Attenuator)

• This iteration ends with no bifurcation and finds an optimal control code L

Lachieved

1)}()1({max

• Aachieved Aspec

(L) (H)

Simulation Environment• Ami 0.5um CMOS (most)• Cadence

– Spectre (simulator)– Hspice (simulator)– SpectreVerilog (simulator)– Analog Artist– Schematic– Virtuoso (layout tool)– SEDSM (Floor-plan /Route )

• Synopsys

Simulation Results

0 50 100 150 200 2500

DAC input (MSB)

Offset Compensation DAC Characteristics

16-b R-1.8R DAC=5V<Lspe

Digitally controlled PF Amplifier

Two Stage Amplifier

PU PDA1 A2

R-2R DAC

ground

reference

2R 2R 2R 2R 2R 1.9R

R R 0.94R

Matched 2R-R

For K LSBDesigned 2R-xR

For N-K MSB

X<1LSB MSB

0 1 N-2 N-1

ground

reference

2R 2R 2R 2R 2R 1.9R

R R 0.94R

Matched 2R-R

For N-K MSB

ground

reference

2R 2R 2R 2R 2R 1.9R

R R 0.94R

ground

reference

2R 2R 2R 2R 2R 1.9R

R R 0.94R

Matched 2R-R

For N-K MSB

output

LSBLSB MSBMSB

0 1 N-2 N-1

Two way switch

Comparator

Vin+ Vin-

M1 M2Vin+ Vin-

Vin+ Vin-

Vout Comparator

Self-Calibrated High Gain Amplifier

DACcode

calibr

controller Amp Comparator

16-bit R-2R

Algorithm for Controller

• Step 1: Initialize • Step 2: Sweep input• Step 3: Use pull-up/down method to detect hysteresis• Step 4: if hysteresis exists, decrease ; else increase • Step 5: if is very close to 0, finish; else goto step 2

Offset Compensation DAC

Attenuator Control DAC

32768 16384 24576 16384 28672 25578 24577

No Bifurcation

64 32 48 52 50 49 48

yesbifurcation: no no yes yes yesMax searching time: 7x16 cycles

Searching Process

Bifurcation Simulation

pull up

pull down

Pull-up/Pull Down

pull up

pull down

x=-0.1mV

AC Response

50dB gain enhancement

Step Response

1.8 2 2.2 2.4 2.6 2.8x 10-7

before calibrationafter calibration

Step Response

2.28 2.3 2.32 2.34 2.36 2.38x 10-7

0.0988

0.0992

0.0994

0.0996

0.0998

before calibrationafter calibration

Significant Settling

accuracy Improvement

Robustness Over Temperature

-40 -20 0 20 40 60 80 10050

temperature(C)

No temperature compesation

With Temperature Compensation

Simulated Performance in 90nm CMOS

Easy Migration

One Fabricated Amplifier’s Performance

Tab. 1 Simulated DC gain over wide temperature range

Gain (dB)

SS SF FS FF NN

0°C 84 85 72 92 103

27°C 82.2

89 84 85 110

80°C 70.4

AMI 0.5um CMOS

Tab. 2 Measured DC gain of fabricated chipsChip #

1#2 #3 #4 #5

Gain (dB)

90 87.6

manual tuning

Two-Stage to enhance linearity

Vi1 Vi2

Two stage amp DC Sweep

-2 -1 0 1 2x 10-4

differential inputs(V)

Two stage Gain vs Vout

-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1110

differential outputs(V)

Equivalent Gain Plot

>130dBover +- 0.75V

Amplifier performance summary

• Berkeley projected 90nm process• power supply voltage Vdd=1.1 • two stage total current Itot=18ma• Total power consumption Ptot=20mw• Capacitive load CL=4p • Unity gain frequency UGF = 1.35GHz• Phase margin at UGF = 39 deg• Frequency at gain 2: G2F = 804MHz • Phase margin at G2F = 65 deg

Switched-Capacitor Amplifier

Precision Multiply-by-Two Circuit

100 MS/s

60% swing:0.3Vdiff

Settlingaccuracy:8.9e-4=10.1 bits

Transient Simulation Results

100 MS/s

full swing0.5Vdiff

Settlingaccuracy:0.0013=9.6 bits

80 MS/s

60% swing0.3Vdiff

Settlingaccuracy:2.1e-4=12.24 bits

input=0.25V

output=0.499969V

40 MS/s

Settling accuracy:3.1e-5/0.5=6.2e-5=14.0 bits

input=0.25V

output=0.499994V

10 MS/s

Settling accuracy:6e-6/0.5=1.2e-5=16.3 bits

Role of Op-Amps

Documents

Cmos Op Amps

Op Amps (2)

OP-AMPS Characteristics Analysis

Ideal Op-Amps and Basic Circuits

Lecture 1 - Intro to Op Amps

Audio Applications for Op-Amps 2

0750697024 Op Amps Design

LECTURE 220 – INTRODUCTION TO OP AMPS - Phillip …aicdesign.org/SCNOTES/2010notes/Lect2UP220_(100327).pdfLECTURE 220 – INTRODUCTION TO OP AMPS LECTURE OUTLINE Outline • Op Amps

OP-AMPS in SIGNAL PROCESSING APPLICATIONS

Internal Structure of Op-Amps and Audio Power Amps

Op Amps - Solved Problems

16. Op Amps - Stanford University · No current into op-amp inputs No voltage difference between op-amp input terminals The Two Golden Rulesfor circuits with ideal op-amps*

How To Use Op Amps

11 Op Amps

Operational Amplifiers (Op Amps) Discussion D3.1

Analog electronics op amps for everyone

Op-amps (v.1a)1 CENG4480_A2 Op Amps and Analog interfacing Analog interfacing techniques

Practical Op Amps

LECTURE 350 – LOW VOLTAGE OP AMPS

LECTURE 310 – HIGH SPEED/FREQUENCY OP AMPSpallen.ece.gatech.edu/Academic/ECE_6412/Spring... · Lecture 310 – High Speed/Frequency Op Amps (3/23/04) ... Explore op amps having