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RF Electronics Engineering
Emad Hegazi Professor, ECE
Communication Circuits Research Grouphttp://portal.eng.asu.edu.eg/emadhegazi.php
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Resonance
• Resonance represents the intrinsic rate of energy exchange in a second order system.
• Friction forces oscillation to cease after a while.
• Less friction means higher quality system2
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Circuit Analysis
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If there is no loss
defineWhy?
Impedance @ Resonance
• Inductor and Capacitor exchange energy and loss resistance keeps burning energy
• By the way, the parallel resistance is simply a model.
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Susceptance @ Resonance
• R is the ONLY block that draws current from the source at resonance
• The tank looks like a high impedance to the supply.
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Quality
• The ratio of stored current to the source current at resonance
• R must be large for higher Q.
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Series Resonance
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Getting Real
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If the input source is constant
Impedance @ Resonance
• Inductor and Capacitor exchange energy and loss resistance keeps burning energy
• The impedance is at minimum when at resonance
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Impedance @ Resonance
• Q is the ratio between the voltage on the reactance to the source voltage.
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Passive Amplification
• Maximum current flows in the circuit means L & C see maximum voltage at opposite polarities.
• @ resonance, the circuit amplifies the source voltage by Q
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QVm -QVm
Impedance Conversion
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Impedance Conversion
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Outline
• Friis Formula• Merits of LNAs• Common Gate LNA• Common Source LNA
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Cascaded Noise Figure
• In a line-up of receiver stages, use Friis equation
• Gi is the power gain• Says that the noise factor ‘F’ is more
influenced by earlier stages
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LNA Merits
• Gain• Low Noise (NF)• High Linearity (IIP3)• Low Reflection (S11)• High reverse isolation (S12)• High Stability (K)
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Maximum Power Transfer
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Transistor Noise
• Thermal noise is referred to the input
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Physical Circuit equivalent
Common Gate LNA
• Input impedance is resistive (except for parasitics)
• Offers good impedance match even at low frequencies
R
vout
Cgs
Cgd
Vin
ZinRs
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Common Gate LNA
• Inductor @input tunes out transistor and board parasitics.
• Channel resistance offers good reverse isolation
R
vout
Cgs
Cgd
Vin
RsCpad
+ Csb L
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Common Gate LNA
• At matching condition, Zin = 1/gm
R
vout
Cgs
Cgd
Vin
RsCpad
+ Csb L
sms
m
RgkTR
gkTF
1
4
/41
1F
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Impedance Transformers
•
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Impedance Matching
• Maximum power transfer• Minimum noise figure• Optimized passives’ transfer functions• Minimum reflections
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Impedance Matching
• Impedance mismatch is preserved at each port• We need a TRANSFORMER
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Transformer Matching
• Transformers are bulky and lossy
• We don’t really need wideband matching in RF transceivers
• Think of a narrow band equivalent of a transformer
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Narrow Band Impedance Transformers
• Load resistance takes only a fraction of the input current
• Looks like a higher resistance than it really is.
• Problem:Zin looks reactive
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L-Match
• @resonance the C and Ls tune out and only Rs remains.
• LNA input is made with higher R to save power
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Antenna LNA
Common Gate LNA: Lowering Power II
• Narrowband impedance transformer (L Section) allows the LNA to have Zin>50W.
• Transformer amplifies input signal by:
R
vout
Cgs
Cgd
Vin
RsCpad
+ Csb L
50 >50
1o
in
Z
Z
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Common Gate LNA: Lowering Power II
• For same IIP3, Veff has to increase by
• >1 • Current is reduced by the
same factor • Bias current is given by:
R
vout
Cgs
Cgd
Vin
RsCpad
+ Csb L
50 >50
o
in
Z
Z
oin
effD
ZZ
VI
2
1
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gm
Common Gate LNA: Lowering Power III
•
R
vout
Cgs
Cgd
Vin
RsCpad
+ Csb L
50 >50
oin
effD
ZZ
VI
2
1
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gm
Common Source Amplifier
Input impedance is purely capacitive
Resistive part appears at high frequency
No input matching is possible
R
vin
vout
Cgs
Zin= 1/jCgs
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Common Source Amplifier
• Rg is set to 50 W => Input Matching
• Miller Effect due to Cgd
=> Limited Bandwidth
R
vin
vout
Cgs
Rg
Cgd
p
sin j
RZ
1
)(
1
gdMgssp CACR
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Common Source Amplifier
• Cascode reduces Miller Effect
• Resistive Load limits linearity
R
vin
vout
Cgs
Cgd
Rg
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Common Source Amplifier
• Parallel Resonance at output boasts narrow band gain without impacting linearity
• Rg produces a lot of Noise NF>3 dB
vin
Cgs
Rg
QoL
vout
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Common Source Amplifier
Series resonance at input creates a resistive term
Iin= jw CgsVgs
Vin=Vgs+jwLs(Iin+gmVgs)
sTsgs
in LLjCj
Z
1
QoL
vin
vout
Cgs
L
LsSeries Resonance
gmVgs
Iin
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Common Source Amplifier
• Series resonance at input creates a resistive term
• @ RF, input is still capacitive because Ls is very small to give 50W with high wT
QoL
vin
vout
Cgs
L
LsSeries Resonance
sgs
ms
gsin L
C
gLj
CjZ
1
gs
mT C
g
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Common Source Amplifier
Gate inductance offers one more degree of freedom to allow matching and series resonance at the same time
Valid for
QoL
vin
vout
Cgs
L
LsSeries Resonance
Lg s
gs
mgs
gsin L
C
gLLj
CjZ
1
gss
oCL
1
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Parasitics
Ali Niknejad ECE14238
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Design Procedure for Common Source LNAs
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Common Source Amplifier
Assume an equivalent resistive load Rd
@ resonance vin
vout
Cgs
Rd = QoL
LsSeries Resonance
Lg
sgs
mgs
gsin L
C
gLLj
CjZ
1
OhmLC
gZ s
gs
min 50
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Common Source Amplifier
Noise Figure (F) is given by
vin
vout
Cgs
Rd = QoL
LsSeries Resonance
Lg
OhmLC
gZ s
gs
min 50
Decreases with wT
Use samll Ls
Source Coils Transistor
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Optimization of CS LNA
Assume
@ Input matching condition
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Optimization of CS LNA
wT Increases
Lg Noise dominates
Higher power
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Another Way to Look at It
• If Q is input quality factor
vinCgs
Ls
Lg
vinCgs
Ls
TLs
+
-Vgs
QV
V
in
gs
sTsmo
T
LRgQ
1
smRgQF
4
11
2
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Another Way to Look at It
• The input is amplified by Q before it reaches the transistor
• This reduces linearity vinCgs
Ls
Lg
vinCgs
Ls
TLs
+
-Vgs
22
333
Q
IIP
in
gs
IIPIIP FETFET
LNA
V
V
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Other Losses: Inductor Losses
• Typically Lg losses dominate• Adds in series to source noise • Independent of FET gain
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Other Losses: Gate Resistance
• Gate Resistance creates additional noise (uncorrelated with channel noise)
• Use inter-digitated layout to reduce gate electrode resistance
rg
g
mFETn
rg
kTv
42
,
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Other Losses: Gate Induced Noise
• Due to inversion layer resistance
• Partly correlated with conventional thermal noise
• Modeled as a resistance in series with gate
GateSource Drain
oxeffinv CWV
Lr
5
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Other Losses: Gate Induced Noise
• The effective Q is lowered by losses
• Higher Q is achieved through lower Cgs
• Smaller Cgs raises rinv and also gate resistance
• There is an optimum W at each current
vin
Cgs
Ls
Lg
+
-Vgs
rinv
W
FQ increases
Fopt
Other losses dominate
FETDominates
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Other Losses: Substrate Coupling
• BSIM3V3 models do NOT capture Cgb• Gate to bulk capacitance is an additional path for
noise
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Other Losses: Substrate Coupling
• Hole distribution in the depletion layer are modulated by gate voltage
• Same effect on electrons in the inversion layer which reflects back on depletion region
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