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Quad Independent ChannelHOTLink II™ CYV15G0404DXB
Video PHY Demonstration BoardUsers Guide
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised February 2, 2005
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TABLE OF CONTENTS1.0 INTRODUCTION ..............................................................................................................................52.0 KIT CONTENTS ...............................................................................................................................53.0 DEMO BOARD FEATURES ............................................................................................................64.0 BOARD ARCHITECTURE ...............................................................................................................7
4.1 Cable Driver and Equalizer Interfaces ........................................................................................74.2 Clocking Architecture ..................................................................................................................84.3 FPGA and Control Architecture ................................................................................................104.4 Power Supply ............................................................................................................................11
5.0 GUI AND OPERATING MODES ....................................................................................................125.1 Setting the SDI Data Rate .........................................................................................................145.2 Serial Interface I/O Selection ....................................................................................................155.3 Standard ...................................................................................................................................155.4 Transmit Test Pattern ...............................................................................................................165.5 Status ........................................................................................................................................16
6.0 SAMPLE TEST PROCEDURES ....................................................................................................176.1 Required Equipment .................................................................................................................176.2 Tektronix WFM 700 ...................................................................................................................176.3 Tests .........................................................................................................................................19
6.3.1 Generating SD Color Bar Patterns ..................................................................................................196.3.2 Generating HD Color Bar Patterns and Reclocking the Data Three Times ....................................206.3.3 Using Redundant Outputs ...............................................................................................................226.3.4 Using Selectable Inputs and Automatic Rate Detection ..................................................................25
7.0 SUMMARY .....................................................................................................................................298.0 REFERENCES ...............................................................................................................................29APPENDIX A: SCHEMATICS OF HOTLINK II CYV15G0404DXB VIDEO DEMO BOARD................30APPENDIX B: PCB MANUFACTURING FILES (GERBER FILES).....................................................43APPENDIX C: PCB ASSEMBLY FILES (DRILL AND ASSEMBLY) ...................................................65APPENDIX D: BILL OF MATERIALS (BOM) OF HOTLINK II CYV15G0404DXB VIDEO DEMO BOARD..........................................................................................................................69APPENDIX E: UNPACKING HOTLINK II CYV15G0404DXB VIDEO DEMO BOARD ........................75APPENDIX F: CONFIGURING THE HOTLINK II CYV15G0404DXB VIDEO DEMO BOARD FOR SD-SDI TO HD-SDI UPCONVERSION ..................................................86
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LIST OF FIGURESFigure 2-1. Top View of Video Demo Board ............................................................................................ 6Figure 4-1. Placement of Cable Drivers and Equalizers and Channel-specific LEDs ............................. 7Figure 4-2. Placement of Clocks on the Board ........................................................................................ 9Figure 4-3. Clock Configuration ............................................................................................................. 10Figure 4-4. Placement of FPGA and Controls ....................................................................................... 11Figure 4-5. Placement of Power Supply and Jumper Headers.............................................................. 12Figure 5-1. Graphical User Interface ..................................................................................................... 13Figure 5-2. GUI–Setting the Data Rate.................................................................................................. 15Figure 5-3. GUI–Selecting the Serial I/Os ............................................................................................. 15Figure 5-4. GUI–Selecting the Standards–SD....................................................................................... 15Figure 5-5. GUI–Selecting the Standards–HD....................................................................................... 16Figure 5-6. GUI–Selecting the Test Patterns......................................................................................... 16Figure 5-7. GUI–Selecting Status .......................................................................................................... 17Figure 6-1. Tektronix WFM 700–Front View.......................................................................................... 18Figure 6-2. Tektronix WFM 700–Rear View .......................................................................................... 18Figure 6-3. Sample Test 1–Generating and Transmitting Color Bars.................................................... 19Figure 6-4. GUI Setting for Sample Test 1 ............................................................................................ 20Figure 6-5. Sample Test 2–Transmits Color Bar Data Via Three Reclockers ....................................... 21Figure 6-6. GUI Setting for Sample Test 2 ............................................................................................ 22Figure 6-7. Sample Test 3–Generate and Transmit Color Bars Through Both Output Buffers ............. 23Figure 6-8. GUI Setting for Sample Test 3–Transmit SD-SDI Color Bars ............................................. 24Figure 6-9. GUI Setting for Sample Test 3–Transmit HD-SDI Color Bars ............................................. 25Figure 6-10. Sample Test 4–Selectable Inputs and Auto Rate Detection ............................................. 26Figure 6-11. GUI Setting for Sample Test 4: Step 6 .............................................................................. 27Figure 6-12. GUI Settings for Sample Test 4: Step 9 ............................................................................ 28Figure 6-13. GUI Setting for Sample Test 4: Step 13 ............................................................................ 29
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LIST OF TABLESTable 4-1. Interface of Cable Drivers and Equalizers to HOTLink II Serial I/Os .....................................8Table 5-1. Summary of GUI Button Functionality (Shown Here for Channel A) ...................................13
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1.0 Introduction
The Quad Independent Channel HOTLink II CYV15G0404DXB Video Demonstration (Demo) Board is a full-fledged serial digitalvideo reference platform that demonstrates the HOTLink II video physical layers (PHYs) interfacing to industry-standard cabledrivers and equalizers. Upstream processing of the video data is performed using on-board Altera Cyclone FPGAs. The boardalso has a flexible clocking architecture with automatic rate detection that allows the board to pass video traffic in multiple formats. The Independent Channel HOTLink II devices[1] are capable of simultaneously operating each channel at a different data rate.The CYV15G0404DXB has the additional capability of performing independent reclocking on a per-channel basis.The Independent Channel HOTLink II CYV15G0404DXB Video Demo Board demonstrates:
• the ability of the Cypress family of transceivers to pass serial digital video at signaling rates from 270 Mb/s to 1485 Mb/s• the independent channel functionality of the applicable devices[1]
• the ability to use a HOTLink II transceiver with an FPGA for auto rate detection and clock reconfiguration • the ability to perform reclocking in the HOTLink II CYV15G0404DXB device • the flexible configuration abilities of Cypress Microsystems’ PSoC microcontroller• the use of Cypress EZ-USB FX2™ USB microcontroller for video data and in-system configuration applications• on-board FPGAs that generate and receive different video test patterns.
Although this board uses the CYV15G0404DXB device, the same board can be used as an evaluation vehicle for any device inthe HOTLink II Independent Channel family of devices. Please refer to the data sheets for descriptions of the HOTLink IIIndependent Channel family of devices.
2.0 Kit ContentsThe kit contains the following: 1. Quad Independent Channel HOTLink II CYV15G0404DXB Video PHY Demo Board, as shown in Figure 2-1.2. CD containing:
a. Graphical User Interface (GUI) set-up file[2]
b. Application Notesc. Demo board user’s guide (this document)d. Cypress’ device data sheetse. Schematics
3. 75Ω Coaxial cable4. AC/DC wall adapter5. USB cable6. Dear Customer Letter7. Kit checklist.
Notes:1. The Independent Channel HOTLink II family consists of the CYV15G0403DXB, CYV15G0404DXB, CYV15G0104TRB, CYV15G0203TB, CYV15G0204RB,
CYV15G0204TRB, CYV15G0403TB, CYV15G0404RB. Refer to each data sheet for a description.2. Please see Appendix E for instructions on installation.
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3.0 Demo Board FeaturesThis section highlights the key features of the Quad Independent Channel HOTLink II CYV15G0404DXB Video PHY Demo Board.• Video transport at multiple rates of 270 Mb/s, 360 Mb/s, 540 Mb/s, and 1485 Mb/s• Auto-rate detection• Low-Jitter outputs• Programmable clocking options for different SMPTE data rates• SMPTE scrambler/descrambler functionality implemented in FPGA• 4x4 clock header to support multiple clocking options • High-speed USB FX2 microcontroller to configure FPGAs• Configuration of HOTLink II device using Cypress Microsystems PSoC Microcontroller • Reclocking Deserializers• 6V DC supply with on-board voltage regulator to prevent noise transfer from external power sources• Interfaces to industry-standard equalizers and cable drivers• LED status indicators• User-friendly GUI• Windows 2000/XP supported.
Figure 2-1. Top View of Video Demo Board
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4.0 Board Architecture
The architecture of the board is shown in Figure 4-1 through Figure 4-4.
The heart of the board is the Quad Independent Channel HOTLink II CYV15G0404DXB device. The device has four independenttransceiver channels. Each transceiver has a transmitter with two outputs and a receiver with two selectable inputs. EachCYV15G0404DXB channel also incorporates a reclocking deserializer. Each transmitter performs 10-to-1 serialization. Eachreceiver includes a Clock and Data Recovery PLL (CDR PLL with embedded VCO and loop filter) and 1-to-10 deserializer. Onthe board, the parallel interface of the CYV15G0404DXB is connected to the on-board FPGAs (U2 and U3). All serial outputs(except OUTA2) are connected to commercially-available cable drivers. All serial inputs (excluding INA2) are connected tocommercially-available equalizers. The CYV15G0404DXB is configured via an 8-bit data/4-bit address configuration interface.This configuration is controlled via a Cypress Microsystems PSoC microcontroller (U14). The architecture of the board isdescribed in the following sections.
4.1 Cable Driver and Equalizer InterfacesThe serial I/Os of the HOTLink II device are connected to various equalizers on the receive side and various cable drivers on thetransmit side as shown in Figure 4-1. The different cable drivers, equalizers and their connections to the HOTLink II device areshown in Table 4-1. Note that all primary interfaces (INx1 and OUTx1) of each channel support multiformat (both HD and SD)drivers and equalizers, while the secondary interfaces (INx2 and OUTx2) support SD only.
Figure 4-1. Placement of Cable Drivers and Equalizers and Channel-specific LEDs
INA2+/- SMA(J3 and J5)
(No Equalizer)
OUTA2+/- SMA(J4 and J2)
(No CableDriver)
INB1 (J11)(GS1524Equalizer)
OUTB1 (J9)(GS1528 CD)
INB2 (J10)(CLC014Equalizer)
OUTB2 (J8)(CLC001 CD)
INA1 (J7)(GS1524Equalizer)
OUTA1 (J6)(GS1528 CD)
IND1 (J18)(GS1524Equalizer)
OUTD1 (J17)(GS1528 CD)
IND2 (J19)(CLC014Equalizer)
OUTD2 (J16)(CLC007 CD)
INC1 (J13)(GS1524Equalizer)
OUTC1 (J14)(GS1528 CD)
INC2 (J15)(GS9024Equalizer)
OUTC2 (J12)(GS9028 CD)
Channel ALEDs
Channel BLEDs
Channel CLEDs
Channel DLEDs
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4.2 Clocking ArchitectureThe board has multiple clocking options to allow for flexible testing and configuration. On each channel, the user can select eitherthe on-board programmable clock, on-board 74.25-MHz crystal oscillator (for HD-SDI/SMPTE 292M), a clock provided by theFPGA, or an external clock. The on-board programmable clock plays a useful role in the auto rate detection mechanism, whichdynamically reprograms the reference clock to the correct frequency, based on the incoming SDI data rate.
When transmitting the video test patterns generated by the FPGA, either the programmable clock, external clock or on-boardcrystal oscillator (only for HD-SDI) should be used.
Table 4-1. Interface of Cable Drivers and Equalizers to HOTLink II Serial I/Os
HOTLink II Channel Serial I/O of HOTLink II Device
Interfacing Cable Driver Interfacing Equalizer Supported Standard
Channel A OUTA1+ Gennum GS1528 x HD-SDI and SD-SDIINA1+ x Gennum GS1524
OUTA2+ No Cable Driver (SMA) x Supports any data rate from 195 Mb/s–1500 Mb/s
(not SMPTE-compliant)INA2+ x No Equalizer (SMA)
Channel B OUTB1+ Gennum GS1528 x HD-SDI and SD-SDIINB1+ x Gennum GS1524
OUTB2+ National CLC001 x SD-SDIINB2+ x National CLC014
Channel C OUTC1+ Gennum GS1528 x HD-SDI and SD-SDIINC1+ x Gennum GS1524
OUTC2+ Gennum GS9028 x SD-SDIINC2+ x Gennum GS9024
Channel D OUTD1+ Gennum GS1528 x HD-SDI and SD-SDIIND1+ x Gennum GS1524
OUTD2+ National CLC007 x SD-SDIIND2+ x National CLC014
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Note. For HD-SDI transmit jitter measurements, it is recommended to avoid using the programmable clock due to the high intrinsicjitter generated by this clock. This jitter will not influence the output jitter in reclocker mode, so the programmable clock may beused to measure reclocked jitter generation. To measure HD-SDI transmit jitter of the HOTLink II video demo board, it is recom-mended to use the on-board crystal oscillator.
The board allows various video test patterns to be generated by the FPGA at different rates and transmitted through serial outputs.The selection of the pattern and data rate is made through the USB host interface GUI. Clock configuration instructions are givenin Figure 4-3.
If the programmable clock option is selected, the data rate setting in the GUI controls the output frequency of the programmableclock. If the external clock option is selected, the user must ensure that the external clock frequency matches the data rate settingin the GUI. For HD-SDI, either a full-rate (148.5 MHz or 148.5/1.001 MHz) or half-rate (74.25 MHz or 74.25/1.001 MHz) clockmay be used. If the on-board 74.25-MHz crystal oscillator option is selected, the GUI must be set to 1485 Mb/s and the FR (Full-Rate) box should be left unchecked.
For further details on jitter measurement, please see application note entitled, SDI SMPTE Jitter Performance of the IndependentChannel HOTLink II Transceiver.Configuration instructions for the different clocking options are found in Figure 4-3.
Figure 4-2. Placement of Clocks on the Board
ProgrammableClocks for Each
ChannelB
(U13)C
(U12)A
(U11)D
(U10)
B (JP13)
C (JP12)
A (JP11)
D (JP10)
Clock ConfigHeaders for
EachChannel
27 MHz CrystalOscillator (reference forprogrammable clocks)
(X1)
74.25 MHzCrystal
Oscillators
B (X2)
A (X5)
D (X3)
C (X4)
1 to 4Differential
Fanout ClockBuffer (U9)
Channel A
Channel B
Channel C
Channel D
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4.3 FPGA and Control ArchitectureThe board contains two FPGAs, U2 and U3. The FPGA U2 interfaces to channels A and B of the CYV15G0404DXB device. TheFPGA U3 interfaces to channels C and D of the CYV15G0404DXB device. The major functions performed by the FPGA are asfollows.
Figure 4-3. Clock Configuration
The position of the Micrel programmable clock chip is given to set thecorrect orientation for determining the pin numbers for clock configuration.Note: Jumpers 6 and 10, and jumpers 7 and 11 are physically shorted forheader design considerations.
On board programmable clock option:Jumper 14 to 10 and Jumper 15 to 11 for using Programmable Micrel clockas Reference Clock. Remove all other jumpers from the header. This optionmust be chosen if the auto rate detect feature of the board is used.
On board 74.25 MHz crystal oscillator clock option:Jumper 9 to 10 and Jumper 12 to 11 for using 74.25 MHz crystal oscillatorclock as Reference Clock. All other jumpers must be removed. This optionshould be chosen for HD-SDI transmit jitter measurement. The GUI must beset to a datarate of 1485 Mb/s (FR box unchecked) for the associatedchannel.
FPGA clock option:Jumper 2 to 6 and Jumper 3 to 7 for using FPGA clock (FCLK) as ReferenceClock. Remove all other jumpers from the clock configuration header. Thisclock option is only used when implementing the upconversion feature of theboard. See Appendix F for further details.
External clock option:Remove all jumpers from the clock configuration header. Provide adifferential clock to pins 6 and 7, with pins 5 and 8 as respective grounds(pins 6 and 5 and pins 7 and 8 are signal and ground pairs). Ensure that theGUI is set to the same clock frequency as the external clock.
JP10, JP11, JP12, JP13
REFCLKx+
REFCLKx-
FCLKx+
FCLKx-
CLOCKOUT+
CLOCKOUT-
GNDGNDGND
GND GND GNDOSC+
OSC-
1
2
3
8
7
6
5
4 12
11
10
9 13
14
15
16
Mic
rel
Prog
ram
mab
leC
lock
SY
8772
9
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1. Video test pattern generation. For SD-SDI, the FPGA can generate EG1 Color Bar Data, Grey Pattern, SMPTE RP178, and SMPTE RP178 alternate SDI checkfield patterns. For HD-SDI, the FPGA can generate Color Bar Data, Grey Pattern, SMPTE RP198, and SMPTE RP198 alternate SDI checkfield patterns.
2. Auto rate detection and clock reconfiguration. The FPGA plays an important role in automatically detecting the incoming data rate and reconfiguring the programmable clock to the correct frequency.
The CYV15G0404DXB configuration interface (8-bit data and 4-bit address) is configured through a Cypress Microsystems PSoCmicrocontroller. The PSoC receives instructions from the host PC through the on-board USB interface.
The on-board USB interface is used to control the various operating modes of the device through a flexible GUI. The USB interfaceis also used to re-program the FPGA and the PSoC microcontroller.
4.4 Power SupplyThe entire board is powered through a single 6V DC power supply. The 6V input is down-converted using on-board regulators todifferent voltages for the various devices in the board. The kit for the board includes a compatible 6V AC wall power supplyadapter.
Figure 4-4. Placement of FPGA and Controls
HOTLink II CYV15G0404DXB (U1)
FPGA forchannelsA and B
(U2)
FPGA for channelsC and D (U3)
USB InterfaceConnector (J20)
Cypress FX2TM USB
Microcontroller(U7)
Cypress MicrosystemsPSoC Microcontroller
(U14)
128-bit I2C Bus Serial EEPROMboot EEPROM for USB micro-controller (U8)
Configuration Devices(U4 and U5)
ProcessorSupervisoryCircuit (U6)
PSoC ProgrammingHeader for externalPSoC configuration
(JB5)
24MHzcrystal forUSB(Y1)
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5.0 GUI and Operating Modes
Please refer to Appendix E for instructions on installing the GUI on a PC/Laptop and configuring the computer to recognize theUSB device. A picture of the GUI window is presented in Figure 5-1. A summary of the functionality of the buttons for channel Ais presented in Table 5-1. The description of each button’s functionality applies equally to all channels.
Figure 4-5. Placement of Power Supply and Jumper Headers
HOTLink II CYV15G0404DXB (U1)
6V DCPower Supply
Jack (J1)
3-Terminal PositiveRegulator (Q2)
3-Terminal PositiveRegulator (Q1)
DC-DC Converter25W 8V in, 3.3V out (U15)
Parallel Jumper Headers(JP14, JP15, JP16, JP17, JP18, JP19, JP20, JP21)
Channel B
Channel C
Channel D
Channel A
CD
DC BA
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Table 5-1. Summary of GUI Button Functionality (Shown Here for Channel A)
Group Button Name Functionality (On Click)Standard SMPTE No action. This radio button is always selected.
1080i (see channel C inthe above figure)
Standard for HD-SDI, automatically checked when user selects 1485Mb/s in Tx/Rx RatePanel of the GUI.
NTSC Standard for SD-SDI. The user can check NTSC when they are transmitting/receiving data at270 Mb/s, 360 Mb/s, or 540 Mb/s.
PAL Standard for SD-SDI. The user can check PAL when they are transmitting/receiving data at270 Mb/s, 360 Mb/s, or 540 Mb/s.
Interface TxPrim Transmit data via OUTA1 (supports both SD and HD)TxSec Transmit data via OUTA2 (supports SD only)RxPrim Receive data via INA1 (supports both SD and HD)
Figure 5-1. Graphical User Interface
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5.1 Setting the SDI Data RateThe appropriate data rate is set by selecting the appropriate button in the Tx/Rx Rate Box of the GUI. The various data rateoptions are 270 Mb/s (SD-SDI/SMPTE 259M-C), 360 Mb/s (SMPTE 259M-D), 540 Mb/s (SMPTE 344M) or 1485 Mb/s (HD-SDI).See Figure 5-2 for a picture of this GUI panel. The FR (Full Rate) check box adjacent to the 1485-Mb/s option is for setting thesource clock frequency for HD-SDI as either full-rate (148.5 MHz) or half-rate (74.25 MHz), via the programmable clock. Whenthe check-box is checked, a full-rate 148.5-MHz clock is used, and when unchecked, a 74.25-MHz clock is used. This button isactive only when the 1485-Mb/s button is selected.
If the programmable clock option is selected, the data rate setting in the GUI controls the output frequency of the programmableclock. If the external clock option is selected, the user must ensure that the external clock frequency matches the data rate settingin the GUI. If the on-board 74.25-MHz crystal oscillator is used, the 1485 Mb/s option must be selected with the FR box leftunchecked. See Section 4.2 for information on selecting clock options.
RxSec Receive data via INA2 (supports SD only)Tx/RxRate
270 Mb/s SD-SDI: SMPTE 259M-C
360 Mb/s SD-SDI: SMPTE 259M-D540 Mb/s SD-SDI: SMPTE 344M1485 Mb/s HD-SDI: SMPTE 292MAuto Rate Detect Programmable clock is reconfigured to the incoming video data rate and all other Tx/Rx Rate
buttons will display which frequency the programmable clock is set to.FR Setting the source clock frequency for HD-SDI as either full-rate (148.5 MHz) or half rate
(74.25 MHz). When the check-box is checked, a full-rate 148.5 MHz clock is used; whenunchecked, a 74.25 MHz clock is used.
TxSource
EG1 Color Bars The FPGA generates EG1 color bars, which will be transmitted out on OUTA1 or OUTA2 orboth.
Grey The FPGA generates a uniform grey pattern, which will be transmitted out on OUTA1 orOUTA2 or both.
RP178/198 The FPGA generates RP178/198 pattern (a pink half-frame on top of a grey half-frame, whichwill be transmitted out on OUTA1 or OUTA2 or both.
RP 178/198 Alt. The FPGA generates an alternative set of the RP178/198 pattern which will be transmittedout on OUTA1 or OUTA2 or both.
Reclocker Reclock the recovered data from the clock and data recovery unit and retransmit it throughthe serial outputs of the same channel.
Up Convert Ch B Functionality not yet implemented.MCL Maximum Cable Length: for normal operation there is no need for the user to touch this (i.e.
leave at 300m). If user would like to test at specific cable lengths then the bar can be set tothe desired setting.
Status Auto Rate Locked Button selected when the correct data rate is detected.CD Carrier Detect: Button selected when the amplitude of the signal on equalizer is above the
MCL threshold.LFI Link Fault Indicator: Button automatically selected when HOTLink II CYV15G0404DXB does
NOT receive a valid serial signal on the relevant channel.CRC Errors Cyclic Redundancy Check Errors Indicator Bar: indicator bar indicates data reception errors.CLI Cable Length Indicator: estimates length of the cable being used for transmitting/receiving
data. Output from cable equalizer.ChannelA
Run/Stop Hitting run configures the channel with the applied settings; hitting stop ends operation andpowers down channel A.
Table 5-1. Summary of GUI Button Functionality (Shown Here for Channel A) (continued)
Group Button Name Functionality (On Click)
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If the output is to be viewed on a Tektronix WFM 700 waveform monitor, the user should not select the 360 Mb/s or 540 Mb/soptions because this waveform monitor does not support these data rates, and consequently, no images will be displayed on themonitor.
Auto Rate DetectWhen the Auto Rate Detect button is selected, the programmable clock is reconfigured to match the incoming video data rateand all other data rate buttons will be disabled. Upon clicking “Run,” various rates are attempted until a valid SMPTE data rate isdetected on the input. This is shown as the last button in Figure 5-2. During the Auto Rate Detection function, a radial dot loopsthrough each data rate as it is attempted. If the data rate is successfully detected, the dot stops next to the rate of the incomingdata stream. For this feature to function, the programmable clock option must be selected.
5.2 Serial Interface I/O SelectionEach HOTLink II transmit channel has redundant outputs. Either one or both outputs can be enabled to transmit the same data.When TxPrim is checked, the primary serial outputs OUTx1 are enabled. When TxSec is checked, the secondary serial outputsOUTx2 are enabled. Note that both primary and secondary outputs can be enabled simultaneously. Each HOTLink II receivechannel has selectable dual inputs. Either INx1 (RxPrim) or INx2(RxSec), but not both, can be selected as the input serial datasource for the respective channel. See Figure 5-3 for a picture of the GUI panel.
5.3 StandardThe first box in the top of the GUI sets the video standard. For SD, the supported SMPTE formats are NTSC and PAL as shownin Figure 5-4. For HD, the supported format is 1080i and upon selecting 1485 Mb/s in the “Tx/Rx Rate” panel, the “Standard”panel will reflect the HD standard as shown in Figure 5-5.
Figure 5-2. GUI–Setting the Data Rate
Figure 5-3. GUI–Selecting the Serial I/Os
Figure 5-4. GUI–Selecting the Standards–SD
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5.4 Transmit Test PatternFor SD-SDI, the FPGA can be configured to generate EG1 Color Bar, SMPTE RP178 SDI checkfield, SMPTE RP178 AlternateSDI checkfield, or Grey field patterns. For HD-SDI, the FPGA can be configured to generate Color Bar, SMPTE RP198 SDIcheckfield, SMPTE RP198 Alternate SDI checkfield, or Grey field patterns. The Maximum Cable Length (MCL) scroll bar shouldbe set to 300m for normal operating conditions. See Figure 5-6 for details.
ReclockerThe CYV15G0404DXB has an integrated reclocker function to reclock the recovered data from the clock and data recovery unitand retransmit it through the serial outputs of the same channel. This can be set by selecting the Reclocker button. If bothReclocker and Auto Rate Detect are selected, and the programmable clocking option is enabled, the auto rate detect logic willdetect the incoming data rate and reconfigure the clocks to perform reclocking function on the selected channel. See Figure 5-6for a picture of the reclocker radio button.
5.5 Status The status panel reflects the real time status of the board; the user has no control of this panel. The “Cable Length Indicator (CLI)”estimates the length of the cable being used between a transmitter and the receiver on that channel. The “Cyclic RedundancyCheck (CRC) Errors” status bar indicates the number of errors detected after the received signal goes through the appropriatecyclic redundancy check. The “Link Fault Indicator (LFI)” is asserted when the HOTLink II CYV15G0404DXB does not receive avalid signal. The “Carrier Detect (CD)” is automatically checked when the amplitude of the incoming signal is greater than thethreshold. The “Auto Rate Locked” button is selected when the data rate for incoming data is detected and the clock isprogrammed to the corresponding frequency.
Figure 5-5. GUI–Selecting the Standards–HD
ReclockingFunction
Figure 5-6. GUI–Selecting the Test Patterns
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6.0 Sample Test Procedures
Before performing the sample tests, please be sure to read Appendix E. It contains instructions on installing the GUI and config-uring the hardware completely. Note: The on-board FPGAs and PSoC will be preprogrammed at the factory for testing. Thereforethere should be no need to program them. Appendix E contains programming instructions should you need them.
6.1 Required Equipment• Tektronix Waveform Monitor: WFM 700• Quad Independent Channel HOTLink II CYV15G0404DXB Video PHY Demo Board• PC/Laptop with HVDB installed• USB cable• 6V DC Power Supply• Four–six BNC cables
6.2 Tektronix WFM 700 The Tektronix WFM 700 is used in the demo tests to display the signal(s) output by the video demo board on the channel(s)specified by the user. As mentioned in previous sections, the WFM 700 does not support data rates of 360 Mb/s and 540 Mb/s.For a brief description of relevant buttons for the tests, please see Figure 6-1. The connectors used in the tests are shown inFigure 6-2.
Figure 5-7. GUI–Selecting Status
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EYE - Displays eye diagramused for jitter analysis
PICTURE - Displays videoTouchscreen allows easy userinterface
INPUT - A or Bused to choose desired input
STATUS - Displays video formatinformation and CRC status.
Used to see if data contains errors
Figure 6-1. Tektronix WFM 700–Front View
S e r ia l D ig ita l In te r fa c e C a rd
C h a n n e l A in p u t
C h a n n e l Bin p u t
Figure 6-2. Tektronix WFM 700–Rear View
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6.3 TestsThis section contains step-by-step tests for fully evaluating the functionality of the board.
6.3.1 Generating SD Color Bar Patterns1. Apply power to the board and connect the USB cable between the board and the computer.2. Connect output OUTA1 to input A of the WFM700 using a BNC cable.3. Open the GUI.4. Configure channel A to generate color bars in SD format. In the “Tx/Rx Rate” panel of the GUI, click on the radio box for
270 Mb/s. In the “Tx Source” panel, select “EG1 Color Bars” to generate the color bar in SD format. See Figure 6-4 for the GUI setting for transmitting color bar at 270 Mb/s.
5. Select the programmable clocking option as shown in Figure 4-3.6. Press the “Run” button for channel A.7. View the picture and status displays for the signal on the WFM 700.
Figure 6-3. Sample Test 1–Generating and Transmitting Color Bars
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6.3.2 Generating HD Color Bar Patterns and Reclocking the Data Three Times1. Apply power to the board and connect the USB cable between the board and the computer.2. Connect a BNC cable between OUTC1 and IND1, a cable between OUTD1 and INB1, a cable between OUTB1 and INA1,
and a cable from OUTA1 to WFM 700. The pattern is sent from the FPGA to channel C; the data is then reclocked from channel C to channel D, then reclocked from channel D to channel B, then reclocked from channel B to channel A and then displayed on the WFM. Since HD color bars are transmitted, the primary outputs/inputs of each channel should be used.
3. For all channels, configure the clock headers to the programmable clock option.4. Open the GUI.5. Select appropriate buttons on the GUI according to Figure 6-6. Please note that there are two methods for setting the data
rate on the reclocker channels. One method is to select “Auto Rate Detect”, which will reconfigure the programmable clocks to the incoming data rate. The other method is to set the data rate for all reclocked channels to be the same as the data rate of the transmitting channel. In the set up shown in Figure 6-5 and Figure 6-6, the transmitting data rate is 1485 Mb/s which is transmitting HD color bars. All reclocked channels are configured to automatically detect this data rate.
6. Press the “Run” button for channel C, then channel A, then channel B, then channel D.7. View the picture display of the signal on the WFM 700.
Figure 6-4. GUI Setting for Sample Test 1
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Figure 6-5. Sample Test 2–Transmits Color Bar Data Via Three Reclockers
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6.3.3 Using Redundant OutputsThis test shows that primary input/output of a channel on the board supports both SD-SDI and HD-SDI standards while thesecondary input/output supports only the SD-SDI standard (due to presence of SD-SDI equalizers and cable drivers on secondaryI/Os).1. Apply power to the board and connect the USB cable between the board and the computer.2. Connect output OUTB1 to the WFM 700 channel A input and connect output OUTB2 to the WFM 700 channel B input using
BNC cables.3. Open the GUI.4. Select the appropriate GUI settings according to Figure 6-8. For this setting, channel B is transmitting SD-SDI color bars on
both primary and secondary outputs. 5. Press the “Run” button for channel B.6. Press the “Input” button on the WFM to display either the primary or secondary output.7. Press the “Stop” button for channel B.8. Change the GUI settings according to Figure 6-9. For this setting, channel B is transmitting HD-SDI color bars only on the
primary output. 9. Press the “Run” button for channel B.10.Press the Input button on the WFM 700 to display either the primary or secondary output. No signal is shown when the
secondary output is selected.
Figure 6-6. GUI Setting for Sample Test 2
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Figure 6-7. Sample Test 3–Generate and Transmit Color Bars Through Both Output Buffers
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Figure 6-8. GUI Setting for Sample Test 3–Transmit SD-SDI Color Bars
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6.3.4 Using Selectable Inputs and Automatic Rate Detection1. Apply power to the board and connect the USB cable between the board and the computer.2. Connect OUTB1 to IND2, OUTA1 to IND1, and OUTD1 to input A of the WFM 700.3. Configure the clock header for channel A to the 74.25-MHz on-board crystal oscillator option, the clock header for channel B
and channel D to the programmable clock option.4. Open the GUI5. Configure channel A to generate the grey pattern in HD format at 1485 Mb/s and channel B to generate the EG1 color bars
in SD format at 270 Mb/s. For channel D, select TxPrim and RxPrim with Auto Rate Detect and Reclocker enabled. See Figure 6-11.
6. Press the “Run” button for channel A, channel B, and channel D.7. View the picture display of the signal on the WFM 700. The user should see the grey pattern in HD-SDI format displayed.8. Press the “Stop” button for channel D.9. Keep the GUI settings for channel A and channel B. For channel D, select TxPrim and RxSec with Auto Rate Detect and
Reclocker enabled. See Figure 6-12.10.Press the “Run” button for channel A, channel B, and channel D.11.View the picture display of the signal on the WFM 700. The user should see the EG1 color bars in SD-SDI format displayed. 12.Press the “Stop” button for all channels.13.Keep the GUI settings for channel A and channel B. For channel D, keep the settings in the “Interface” panel; select the data
rate to be 270 Mb/s and reclocker enabled. See Figure 6-13.14.Press the “Run” button for channel A, channel B, and channel D.
Figure 6-9. GUI Setting for Sample Test 3–Transmit HD-SDI Color Bars
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15.View the picture display of the signal on the WFM 700. The user should see the EG1 color bars in SD-SDI format displayed.16.Press the “Stop” button for all channels.Note: For this test, the clock headers for channel A can be configured to either the on-board programmable clock option or theon-board 74.25-MHz crystal oscillator clock option. Clock headers for channel B and channel D should be configured to the on-board programmable clock option.
Figure 6-10. Sample Test 4–Selectable Inputs and Auto Rate Detection
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Figure 6-11. GUI Setting for Sample Test 4: Step 6
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Figure 6-12. GUI Settings for Sample Test 4: Step 9
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7.0 Summary
The Cypress HOTLink II family of transceivers are compliant to requirements specified by SMPTE for SD-SDI and HD-SDI serialinterfaces. The evaluation platform provides a full-fledged reference design that enables customers to easily implement SerialDigital Interface systems with HOTLink II Video PHYs.
8.0 References1. Television—10-Bit 4:2:2 Component and 4fSC Composite Digital Signals–Serial Digital Interface, ANSI/SMPTE 259M–1997,
Society of Motion Picture and Television Engineers, 1997.2. Television—Component Video Signal 4:2:2 - Bit-Parallel Digital Interface, ANSI/SMPTE 125M-1995, Society of Motion Picture
and Television Engineers, 1995.3. Television—System M/NTSC Composite Video Signals–Bit-Parallel Digital Interface, ANSI/SMPTE 244M-1995, Society of
Motion Picture and Television Engineers, 1995.4. Television—Bit-Parallel Digital Interface–Component Video Signal 4:2:2 16x9 Aspect Ratio, ANSI/SMPTE 267M-1995, Society
of Motion Picture and Television Engineers, 1995.5. Pathological Conditions in Serial Digital Video Systems, SMPTE Engineering Guidelines, EG 34-1999, Society of Motion
Picture and Television Engineers, 1999.6. Serial Digital Interface Checkfield for 10-Bit 4:2:2 Component and 4fsc Composite Digital Signals, SMPTE Recommended
Practices, RP 178-1996, Society of Motion Picture and Television Engineers, 1996.7. SDI SMPTE Jitter Performance of the Independent Channel HOTLink II Transceiver, Application Note, Cypress Semicon-
ductor Corporation 2004.
Figure 6-13. GUI Setting for Sample Test 4: Step 13
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Appendix A: Schematics of HOTLink IICYV15G0404DXB Video Demo Board
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Figure A-1. Top Level Schematic
11
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Figure A-2. USB FX2 Microcontroller
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VCC38
GND39
TXD040
RXD041
TXD142
RXD143
PB4/FD444
PB5/FD545
PB6/FD646
PB7/FD747
GND48
VCC49
GND50
CT
L3
51C
TL
452
VC
C53
CT
L0
/*F
LA
GA
54C
TL
1/*
FL
AG
B55
CT
L2
/*F
LA
GC
56P
C0/
GP
IFA
DR
057
PC
1/G
PIF
AD
R1
58P
C2/
GP
IFA
DR
259
PC
3/G
PIF
AD
R3
60P
C4/
GP
IFA
DR
461
PC
5/G
PIF
AD
R5
62P
C6/
GP
IFA
DR
663
PC
7/G
PIF
AD
R7
64G
ND
65V
CC
66P
A0/
INT
067
PA
1/IN
T1
68P
A2/
*SL
OE
69P
A3/
*WU
270
PA
4/F
IFO
AD
R0
71P
A5/
FIF
OA
DR
172
PA
6/*P
KT
EN
D73
PA
7/*F
LA
GD
/SL
CS
74G
ND
75C
TL
576
RE
SE
T77
VC
C78
*WA
KE
UP
79P
D0/
FD
880
PD1/FD981
PD2/FD1082
PD3/FD1183
INT584
VCC85
PE0/T0OUT86
PE1/T1OUT87
PE2/T2OUT88
PE3/RXD0OUT89
PE4/RXD1OUT90
PE5/INT691
PE6/T2EX92
PE7/GPIFADR893
GND94
PD4/FD1295
PD5/FD1396
PD6/FD1497
PD7/FD1598
GND99
CLKOUT100
U7
CY
7C6
801
3-10
0AC
F1D
AT
A0
F1A
SD
I
F1D
CL
KF
1nC
S
F1n
CE
F1n
CO
NF
IGF
1CO
NF
IG_D
ON
ED
PL
US
/DM
INU
Ssh
ould
have
90
ohm
+/-
10%
dif
fere
ntia
lim
ped
ance
.
C16
90.
1uC
168
0.1u
XR
ES
XS
CL
KX
DA
TA
R19
51k
C25
20.
1uC
253
0.1u
C25
40.
1uC
255
0.1u
C25
60.
1uC
257
0.1u
C25
80.
1uC
259
0.1u
+C
260
10u
Page 32 of 92
[+] Feedback
Quad Independent Channel
HOTLink II™ CYV15G0404DXBVideo PHY Demonstration Board
Figure A-3. FPGA Top Level
11
22
33
44
55
66
DD
CC
BB
AA
LS
7652
Cypr
essM
olson
-FPG
A's
203
12G
.C
osen
s
Siz
eD
raw
ing
Num
ber
Rev
isio
n
Dat
e:F
ile:
She
etof
Dra
wn
By:
FP
GA
.Sch
Do
c7/
6/20
04
B
Line
arSy
stem
sLt
d.
TX
DA
[7..
0]T
XD
B[7
..0]
TX
DC
[7..0
]T
XD
D[7
..0]
TX
CT
A[1
..0]
TX
CT
B[1
..0]
TX
CT
C[1
..0]
TX
CT
D[1
..0]
TX
CL
KO
AT
XC
LK
OB
TX
CL
KO
CT
XC
LK
OD
TX
CL
KA
TX
CL
KB
TX
CL
KC
TX
CL
KD
RX
DA
[7..
0]R
XD
B[7
..0]
RX
DC
[7..
0]R
XD
D[7
..0]
RX
ST
A[2
..0]
RX
ST
B[2
..0]
RX
ST
C[2
..0]
RX
ST
D[2
..0]
RX
CL
KA
+R
XC
LK
B+
RX
CL
KC
+R
XC
LK
D+
RX
CL
KA
-R
XC
LK
B-
RX
CL
KC
-R
XC
LK
D-
SD
/HD
AS
D/H
DB
SD
/HD
CS
D/H
DD
CD
/MU
TE
AC
D/M
UT
EB
CD
/MU
TE
CC
D/M
UT
ED
PT
XD
A[9
..0]
PT
XD
B[9
..0]
PT
XD
C[9
..0]
PT
XD
D[9
..0]
PR
XD
A[9
..0]
PR
XD
B[9
..0]
PR
XD
C[9
..0]
PR
XD
D[9
..0]
FD
[15
..0]
CT
L[2
..0]
RD
Y[1
..0]
CL
KO
UT
IFC
LK
LF
IAL
FIB
LF
ICL
FID
CD
/MU
TE
B2
CD
/MU
TE
D2
SS
I/C
DC
2
SD
I
SD
OS
CL
SC
SE
F1A
SD
I
F1n
CS
F1D
CL
K
F1n
CE
F1n
CO
NF
IGF
1CO
NF
IG_D
ON
E
F1D
AT
A0
PA
7/*F
LA
GD
/SL
CS
#R
ES
ET
#
RC
LK
EN
DR
CL
KE
NC
RC
LK
EN
BR
CL
KE
NA
SP
DS
EL
AS
PD
SE
LB
SP
DS
EL
CS
PD
SE
LD
LP
EN
AL
PE
NB
LP
EN
CL
PE
ND
INS
EL
AIN
SE
LB
INS
EL
CIN
SE
LD
UL
CA
UL
CB
UL
CC
UL
CD
LD
TD
EN
PR
XC
LK
AP
RX
CL
KB
PR
XC
LK
CP
RX
CL
KD
PT
XC
LK
AP
TX
CL
KB
PT
XC
LK
CP
TX
CL
KD
F2C
ON
FIG
_DO
NE
F2n
CO
NF
IGF
2nC
E
F2D
AT
A0
F2D
CL
KF
2nC
S
F2A
SD
I
SC
SE1
12
34
56
78
910
JP9
HE
AD
ER
5X
2
R13
1.0K
R14
1.0K
R15
1.0K
+3.
3V
+3.
3V
TX
DA
[7..
0]T
XD
B[7
..0]
TX
CT
A[1
..0]
TX
CT
B[1
..0]
TX
CL
KO
AT
XC
LK
OB
TX
CL
KA
TX
CL
KB
RX
DA
[7..
0]R
XD
B[7
..0]
RX
ST
A[2
..0]
RX
ST
B[2
..0]
RX
CL
KA
+R
XC
LK
B+
RX
CL
KA
-R
XC
LK
B-
SD
/HD
AS
D/H
DB
CD
/MU
TE
AC
D/M
UT
EB
PT
XD
A[9
..0]
PT
XD
B[9
..0]
PR
XD
A[9
..0]
PR
XD
B[9
..0]
F1D
AT
A0
F1A
SD
IF
1DC
LK
F1n
CS
CL
KO
UT
IFC
LK
LF
IAL
FIB
SD
I
SD
OS
CL
SC
SEF
1nC
EF
1nC
ON
FIG
F1C
ON
FIG
_DO
NE
PA
7/*F
LA
GD
/SL
CS
#R
ES
ET
#
RC
LK
EN
AR
CL
KE
NB
SP
DS
EL
AS
PD
SE
LB
LP
EN
AL
PE
NB
INS
EL
AIN
SE
LB
UL
CA
UL
CB
LD
TD
EN
PT
XC
LK
AP
TX
CL
KB
PR
XC
LK
AP
RX
CL
KB
FD
[15
..0]
CT
L[2
..0]
RD
Y[1
..0]
CD
/MU
TE
B2
TC
KT
DI
TM
S
TD
O
TX
ER
RA
TX
ER
RB
FC
LK
A+
FC
LK
A-
FC
LK
B+
FC
LK
B-
FP
GA
1F
PG
A1.
Sch
Doc
TX
DC
[7..0
]T
XD
D[7
..0]
TX
CT
C[1
..0]
TX
CT
D[1
..0]
TX
CL
KO
CT
XC
LK
OD
TX
CL
KC
TX
CL
KD
RX
DC
[7..
0]R
XD
D[7
..0]
RX
ST
C[2
..0]
RX
ST
D[2
..0]
RX
CL
KC
+R
XC
LK
D+
RX
CL
KC
-R
XC
LK
D-
SD
/HD
CS
D/H
DD
CD
/MU
TE
CC
D/M
UT
ED
PT
XD
C[9
..0]
PT
XD
D[9
..0]
PR
XD
C[9
..0]
PR
XD
D[9
..0]
F2D
AT
A0
F2A
SD
IF
2DC
LK
F2n
CS
LF
ICL
FID
CD
/MU
TE
D2
SS
I/C
DC
2F
2nC
EF
2nC
ON
FIG
F2C
ON
FIG
_DO
NE
RC
LK
EN
CR
CL
KE
ND
SP
DS
EL
CS
PD
SE
LD
PT
XC
LK
C
PR
XC
LK
C
PT
XC
LK
D
PR
XC
LK
DL
PE
NC
LP
EN
DIN
SE
LC
INS
EL
DU
LC
CU
LC
DS
DI
SD
OS
CL
SC
SE1
RE
SE
T#
TC
KT
DI
TM
S
TD
O
CL
KO
UT
IFC
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Y[1
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CT
L[2
..0]
FD
[15
..0]
PA
7/*F
LA
GD
/SL
CS
#
TX
ER
RC
TX
ER
RD
FC
LK
C+
FC
LK
C-
FC
LK
D+
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FP
GA
2F
PG
A2.
Sch
Doc
TM
RE
SE
T#
TD
O
TD
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TC
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R19
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3
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4
TX
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RB
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RC
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FC
LK
B+
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A+
FC
LK
A-
FC
LK
C+
FC
LK
C-
FC
LK
D-
FC
LK
D+
Page 33 of 92
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Quad Independent Channel
HOTLink II™ CYV15G0404DXBVideo PHY Demonstration Board
Figure A-4. FPGA for Channel A and B
11
22
33
44
55
66
DD
CC
BB
AA
LS
7652
Cypr
essM
olson
-FPG
A1
204
12G
.Cos
ens
Siz
eD
raw
ing
Nu
mbe
rR
evis
ion
Dat
e:F
ile:
She
etof
Dra
wn
By:
FPG
A1.
Sch
Doc
7/6/
2004
B
Line
arSy
stem
sLt
d.
F1n
CS
F1D
AT
A0
F1n
CO
NF
IG
F1D
CL
KF
1ASD
I
TX
DA
[7..0
]
TX
DB
[7..
0]
TX
CT
A[1
..0]
TX
CT
B[1
..0]
TX
CL
KO
A
TX
CL
KO
B
TX
CL
KA
TX
CL
KB
RX
DA
[7..0
]
RX
DB
[7..0
]
RX
ST
A[2
..0]
RX
ST
B[2
..0]
RX
CL
KA
+
RX
CL
KB
+
RX
CL
KA
-
RX
CL
KB
-
SD
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A
SD
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B
CD
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TE
A
CD
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TE
B
PT
XD
A[9
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PT
XD
B[9
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PR
XD
A[9
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PR
XD
B[9
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F1D
AT
A0
F1A
SDI
F1D
CL
KF
1nC
S
CLK
OU
T
IFC
LK
LF
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LF
IB
SD
I
SD
O
SC
L
SC
SE
+3.
3V+
1.5V
DA
TA
2
DC
LK
6
nCS
1
ASD
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VC
C8
VC
C7
VC
C3
GN
D4
U4
EP
CS
4SI8
N
+3.
3V
12
34
56
78
910
JP6
HE
AD
ER
5X2
+3.
3V
F1n
CE
F1n
CS
F1D
CL
KF
1CO
NF
IG_D
ON
EF
1nC
ON
FIG
F1D
AT
A0
F1A
SDI
F1n
CE
F1n
CO
NF
IGF
1CO
NF
IG_D
ON
EF
1CO
NF
IG_D
ON
EF
1nC
ON
FIG
F1D
AT
A0
F1D
CL
KF
1nC
SF
1ASD
I
F1D
AT
A0
F1D
CL
KF
1nC
SF
1ASD
I
F1n
CE
F1C
ON
FIG
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NE
F1n
CO
NF
IG
F1n
ST
AT
US
R5
10K
R4
10K
R3
10K
+3.
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CE
R6
10K
F1n
CE
TX
CL
KA
TX
CL
KO
A
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DA
0
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DA
1
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DA
2
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DA
3
TX
DA
4
TX
DA
5T
XD
A6
TX
DA
7
TX
CT
A0
TX
CT
A1
TX
DA
[7..0
]
TX
CT
A[1
..0]
RX
CL
KA
+
RX
CL
KA
-
RX
DA
0
RX
DA
1
RX
DA
2
RX
DA
3
RX
DA
4
RX
DA
5
RX
DA
6
RX
DA
7
RX
ST
A0
RX
ST
A1
RX
DA
[7..0
]
RX
ST
A[2
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PT
XD
A0
PT
XD
A1
PT
XD
A2
PT
XD
A3
PT
XD
A4
PT
XD
A5
PT
XD
A6
PT
XD
A7
PT
XD
A8
PT
XD
A9
PR
XD
A0
PR
XD
A1
PR
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A2
PR
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A3
PR
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A4
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A5
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A6
PR
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A7
PR
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A8
PR
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A[9
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PR
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TX
CL
KB
TX
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TX
DB
0
TX
DB
1
TX
DB
2
TX
DB
3
TX
DB
4
TX
DB
5
TX
DB
6
TX
DB
7
TX
CT
B0
TX
CT
B1
TX
DB
[7..
0]
TX
CT
B[1
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RX
CL
KB
+
RX
CL
KB
-
RX
DB
0
RX
DB
1
RX
DB
2
RX
DB
3
RX
DB
4
RX
DB
5
RX
DB
6
RX
DB
7
RX
ST
B0
RX
ST
B1
RX
DB
[7..0
]
RX
ST
B[2
..0]
PT
XD
B0
PT
XD
B1
PT
XD
B2
PT
XD
B3
PT
XD
B4
PT
XD
B5
PT
XD
B6
PT
XD
B7
PT
XD
B8
PT
XD
B9
PR
XD
B0
PR
XD
B1
PR
XD
B2
PR
XD
B3
PR
XD
B4
PR
XD
B5
PR
XD
B6
PR
XD
B7
PR
XD
B8
PR
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B9
PT
XD
B[9
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PR
XD
B[9
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PA
7/*
FL
AG
D/S
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S#
C20
0.1
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210.
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C10
0.1
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110.
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0.1
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C14
0.1
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C16
0.1
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170.
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0.1
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190.
1u
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1.5V
C9
0.1
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RE
SET
#
RX
ST
B2
RX
ST
A2
RC
LK
EN
A
RC
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SPD
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LA
SPD
SE
LB
LP
EN
A
INS
EL
A
INS
EL
B
UL
CA
UL
CB
LD
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EN
1 2 3
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R1
0 R2
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SPD
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SPD
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LB
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LA
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PT
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RX
CLK
A
PR
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0]
RD
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FD
[15.
.0]
FD
0F
D1
FD
2
FD
3
FD
4
FD
5
FD
6F
D7
FD
8
FD
9
FD
10
FD
11
FD
12
FD
13
FD
14
FD
15
CTL
[2..
0]C
TL0
CTL
1
CTL
2
RD
Y[1
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RD
Y0
RD
Y1
F1C
ON
FIG
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ST
AT
US
CD
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TE
B2
TC
K
TD
I
TM
ST
DO
+1.
5VA
+1.
5V+
1.5V
C14
60.
1u
C14
71n
+1.
5VA C
148
0.1
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149
1n
C14
30.
1u
C15
50.
1u
D11
LE
D2
D12
LE
D2
D13
LE
D2
D14
LE
D2
D9
LE
D2
D10
LE
D2
D5
LE
D2
D6
LE
D2
D7
LE
D2
D8
LE
D2
D3
LE
D2
D4
LE
D2
R17
4
221
R17
5
221
R17
6
221
R17
7
221
R17
8
221
R17
9
221
R16
8
221
R16
9
221
R17
0
221
R17
1
221
R17
2
221
R17
3
221
LF
IAC
DA
L27
0A
L36
0AL
540A
L74
25A
LF
IB
CD
B
L27
0BL
360B
L54
0B
L74
25B
LF
IA
CD
A
L27
0A
L36
0A
L54
0A
L74
25A
LF
IB
CD
B
L27
0B
L36
0B
L54
0B
L74
25B
D30
LE
D2
R19
6
221
+3.
3V
LP
EN
B
C17
20.
1u
C17
30.
1u
C17
40.
1u
C17
50.
1u
C17
60.
1u
C17
70.
1u
C17
80.
1u
C17
90.
1u
C18
00.
1u
C18
10.
1u
C18
20.
1u
C18
30.
1u
+3.
3V+
1.5V
C17
10.
1u
C17
00.
1u
TX
ER
RA
TX
ER
RB
FC
LK
A+
FC
LK
A-
FC
LK
B+
FC
LK
B-
R21
3
0
R21
4
0
rxst
b[2
]C
3
txd
a[1
]C
2
rxda
[3]
D3
lpen
bD
2
scl
D4
txcl
kaD
1
inse
lbE
3
txct
a[1]
E2
RE
SER
VE
D_I
NPU
TF
1
rxda
[7]
E4
RE
SER
VE
D_I
NPU
TE
5
sdo
F2
scse
F3
lfia
F4
RE
SER
VE
D_I
NPU
TF
5
RE
SER
VE
D_I
NPU
TG
1
RE
SER
VE
D_I
NPU
TG
2
RE
SER
VE
D_I
NPU
TF
6
RE
SER
VE
D_I
NPU
TF
7
RE
SER
VE
D_I
NPU
TH
6
RE
SER
VE
D_I
NPU
TJ1
DA
TA
0H
7
nCO
NFI
GJ2
VC
CA
_PL
L1
J5
rxcl
ka_p
J3
txcl
koa
J4
GN
DA
_PL
L1
K1
GN
DG
_PL
L1
J6
nCE
OK
2
nCE
J7
MS
EL
0K
3
MS
EL
1K
7
DC
LK
L1
RE
SER
VE
D_I
NPU
TK
6
fclk
a_p
K4
fclk
a_n
K5
fd[8
]M
4
fd[7
]N
1
fd[6
]N
2
RE
SER
VE
D_I
NPU
TM
6
RE
SER
VE
D_I
NPU
TN
7
RE
SER
VE
D_I
NPU
TN
5
RE
SER
VE
D_I
NPU
TN
6
fd[1
1]N
3
fd[1
0]N
4
RE
SER
VE
D_I
NPU
TP
5
fd[1
2]P
2
fd[1
3]P
3
fd[5
]R
1
RE
SER
VE
D_I
NPU
TP
4
fd[4
]R
2
fd[1
4]R
3
fd[1
5]T
2
clko
ut
T3
BA
NK
1
RE
SER
VE
D_I
NPU
TG
3
RE
SER
VE
D_I
NPU
TG
4
RE
SER
VE
D_I
NPU
TG
5
RE
SER
VE
D_I
NPU
TG
6
RE
SER
VE
D_I
NPU
TH
1
RE
SER
VE
D_I
NPU
TH
2
rxcl
ka_n
H3
sdi
H4
RE
SER
VE
D_I
NPU
TH
5
RE
SER
VE
D_I
NPU
TL
7
RE
SER
VE
D_I
NPU
TL
6
ctl[
2]
L2
rese
t_n
L3
RE
SER
VE
D_I
NPU
TL
5
pa7_
flag
d_sl
csL
4
ctl[
1]
M1
fd[9
]M
3
ctl[
0]
M2
RE
SER
VE
D_I
NPU
TM
5
U2A
EP
1C20
F32
4C8
rxst
b[1
]C
16
txer
rbB
16
VC
CIN
TG
11
GN
DF
11
rxst
b[0
]B
15
spd
selb
A15
lpen
aC
15
rclk
ena
D14
txd
b[3]
B14
rxdb
[4]
C14
RE
SER
VE
D_I
NPU
TE
13
GN
DG
10
VC
CIN
TF
10
rxdb
[5]
C11
rxst
a[1]
D11
txd
b[0]
B11
txct
b[1]
A11
RE
SER
VE
D_I
NPU
TC
10
rxda
[2]
D10
RE
SER
VE
D_I
NPU
TE
10
rxdb
[2]
C8
txd
a[7
]A
8
txd
a[4
]B
8
RE
SER
VE
D_I
NPU
TE
8
RE
SER
VE
D_I
NPU
TE
7
txd
a[5
]A
7
txd
a[6
]B
7
lfib
C7
RE
SER
VE
D_I
NPU
TE
6
rxda
[4]
D6
txd
a[3
]B
6
rxdb
[7]
C6
txd
a[0
]A
6
RE
SER
VE
D_I
NPU
TB
5
rxdb
[3]
C5
rxda
[5]
D5
txd
a[2
]A
4
rxdb
[6]
B4
VC
CIN
TF
8
GN
DG
8
txer
raB
3
rxda
[6]
C4
BA
NK
2
txd
b[2]
B13
txcl
kbA
13
inse
laD
13
rxdb
[1]
C13
rxst
a[2]
D12
rxdb
[0]
C12
txd
b[7]
B12
txd
b[4]
A12
txd
b[1]
B10
txd
b[5]
A10
VC
CIN
TG
9
GN
DF
9
rxst
a[0]
D9
RE
SER
VE
D_I
NPU
TC
9
txct
a[0]
A9
txct
b[0]
B9
rxda
[0]
D8
rxda
[1]
D7
RE
SER
VE
D_I
NPU
TE
11
U2B
EP
1C20
F32
4C8
led2
T16
ledc
dbT
17
ptxd
a[1]
R17
ptxd
a[0]
R18
prxc
lkb
R15
ledl
fib
R16
led2
70b
P16
led3
60b
P17
RE
SER
VE
D_I
NPU
TP
15
RE
SER
VE
D_I
NPU
TP
14
RE
SER
VE
D_I
NPU
TN
14
led5
40b
N18
ptxc
lka
N17
RE
SER
VE
D_I
NPU
TN
13
RE
SER
VE
D_I
NPU
TN
12
led7
425
bN
16
RE
SER
VE
D_I
NPU
TN
15
ledl
fia
M1
8
ledc
daM
17
fclk
b_p
K16
fclk
b_n
K15
CO
NF
_DO
NE
K17
nST
AT
US
L12
TC
KK
18
TM
SK
14
TD
OK
13
GN
DG
_PL
L2
J18
GN
DA
_PL
L2
K12
txcl
kob
J16
rxcl
kb_
pJ1
5
VC
CA
_PL
L2
J12
TD
IJ1
7
RE
SER
VE
D_I
NPU
TJ1
4
RE
SER
VE
D_I
NPU
TG
13
RE
SER
VE
D_I
NPU
TG
14
RE
SER
VE
D_I
NPU
TG
15
RE
SER
VE
D_I
NPU
TG
16
RE
SER
VE
D_I
NPU
TG
12
RE
SER
VE
D_I
NPU
TF
12
cd_m
ute
bF
18
sd_
hdb
F17
RE
SER
VE
D_I
NPU
TF
13
RE
SER
VE
D_I
NPU
TF
14
cd_m
ute
b2F
16
RE
SER
VE
D_I
NPU
TF
15
RE
SER
VE
D_I
NPU
TE
17
rclk
enb
E1
6
ulca
E1
5
spd
sela
D18
RE
SER
VE
D_I
NPU
TE
14
ldtd
enD
16
RE
SER
VE
D_I
NPU
TD
15
txd
b[6]
C17
ulcb
D17
BA
NK
3
RE
SER
VE
D_I
NPU
TM
14
RE
SER
VE
D_I
NPU
TM
15
led2
70a
M1
6
led5
40a
L18
led3
60a
L17
RE
SER
VE
D_I
NPU
TM
13
RE
SER
VE
D_I
NPU
TL
13
led7
425
aL
16
RE
SER
VE
D_I
NPU
TL
15
RE
SER
VE
D_I
NPU
TL
14
RE
SER
VE
D_I
NPU
TJ1
3
RE
SER
VE
D_I
NPU
TH
13
RE
SER
VE
D_I
NPU
TH
14
rxcl
kb_
nH
15
RE
SER
VE
D_I
NPU
TH
16
RE
SER
VE
D_I
NPU
TH
17
cd_m
ute
aH
18
sd_
hda
G18
RE
SER
VE
D_I
NPU
TG
17
U2C
EP
1C20
F32
4C8
rdy[
1]U
3
fd[2
]V
4
VC
CIN
TM
8
GN
DN
8
ifcl
kT
4
fd[3
]U
4
ptxd
b[9]
T5
prxd
a[9]
U5
rdy[
0]R
4
prxd
b[9
]R
5
fd[0
]V
6
fd[1
]U
6
RE
SER
VE
D_I
NPU
TP
6
RE
SER
VE
D_I
NPU
TP
7
ptxd
b[8]
T6
prxd
a[8]
U7
ptxd
a[9]
V7
ptxd
b[7]
T7
prxd
b[7
]R
7
prxd
a[7]
U8
ptxd
a[8]
V8
ptxd
b[6]
T8
RE
SER
VE
D_I
NPU
TP
9
ptxd
b[4]
T10
prxd
b[4
]R
10
prxd
b[3
]R
11
ptxd
b[3]
T11
prxd
a[4]
U11
ptxd
a[5]
V11
GN
DN
10
VC
CIN
TM
10
RE
SER
VE
D_I
NPU
TP
12
RE
SER
VE
D_I
NPU
TP
13
prxd
a[1]
U14
ptxd
b[0]
T14
prxd
b[0
]R
14
ptxd
a[2]
V15
prxd
a[0]
U15
VC
CIN
TN
11
GN
DM
11
prxc
lka
U16
ptxc
lkb
T15
BA
NK
4
prxd
b[8
]R
6
prxd
a[6]
U9
ptxd
a[7]
V9
prxd
b[5
]R
9
ptxd
b[5]
T9
GN
DM
9
VC
CIN
TN
9
prxd
a[5]
U10
ptxd
a[6]
V10
RE
SER
VE
D_I
NPU
TP
10
ptxd
a[4]
V12
prxd
a[3]
U12
ptxd
b[2]
T12
prxd
b[2
]R
12
ptxd
a[3]
V13
prxd
a[2]
U13
ptxd
b[1]
T13
prxd
b[1
]R
13
prxd
b[6
]R
8
U2D
EP
1C20
F32
4C8
VCCINTA17
VCCINTA2
VCCINTB1
VCCINTB18
VCCINTH10
VCCINTJ9
VCCINTK10
VCCINTL9
VCCINTU1
VCCINTU18
VCCINTV17
VCCINTV2
VCCIO1E1
VCCIO1G7
VCCIO1M7
VCCIO1P1
VCCIO2A14
VCCIO2A5
VCCIO2E12
VCCIO2E9
VCCIO3E18
VCCIO3H12
VCCIO3M12
VCCIO3P18
VCCIO4P11
VCCIO4P8
VCCIO4V14
VCCIO4V5
GNDA1
GNDA16
GNDA18
GNDA3
GNDB17
GNDB2
GNDC1
GNDC18
GNDH11
GNDH8
GNDH9
GNDJ10
GNDJ11
GNDJ8
GNDK11
GNDK8
GNDK9
GNDL10
GNDL11
GNDL8
GNDT1
GNDT18
GNDU17
GNDU2
GNDV1
GNDV16
GNDV18
GNDV3
POWER/GND
U2E
EP
1C20
F32
4C8
+C
250
10u
+3.
3V
Page 34 of 92
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Quad Independent Channel
HOTLink II™ CYV15G0404DXBVideo PHY Demonstration Board
Figure A-5. FPGA for Channel C and D
11
22
33
44
55
66
DD
CC
BB
AA
LS
7652
Cypr
essM
olson
-FPG
A2
205
12G
.Cos
ens
Siz
eD
raw
ing
Nu
mbe
rR
evis
ion
Dat
e:F
ile:
She
etof
Dra
wn
By:
FPG
A2.
Sch
Doc
7/6/
2004
B
Line
arSy
stem
sLt
d.
TX
DC
[7..
0]
TX
DD
[7..0
]
TX
CT
C[1
..0]
TX
CT
D[1
..0]
TX
CL
KO
CT
XC
LK
OD
TX
CL
KC
TX
CL
KD
RX
DC
[7..0
]
RX
DD
[7..0
]
RX
ST
C[2
..0]
RX
ST
D[2
..0]
RX
CL
KC
+
RX
CL
KD
+
RX
CL
KC
-
RX
CL
KD
-
SD
/HD
C
SD
/HD
D
CD
/MU
TE
C
CD
/MU
TE
D
PT
XD
C[9
..0]
PT
XD
D[9
..0]
PR
XD
C[9
..0]
PR
XD
D[9
..0]
F2D
AT
A0
F2A
SDI
F2D
CL
KF
2nC
S
LF
IC
LF
ID
CD
/MU
TE
D2
SSI
/CD
C2
+3.
3V+
1.5V
DA
TA
2
DC
LK
6
nCS
1
ASD
I5
VC
C8
VC
C7
VC
C3
GN
D4
U5
EP
CS
4SI8
N
+3.
3V
12
34
56
78
910
JP8
HE
AD
ER
5X2
+3.
3V
F2n
CE
F2n
CS
F2D
CL
KF
2CO
NF
IG_D
ON
EF
2nC
ON
FIG
F2D
AT
A0
F2A
SDI
F2n
CE
F2n
CO
NF
IGF
2CO
NF
IG_D
ON
EF
2CO
NF
IG_D
ON
EF
2nC
ON
FIG
F2D
AT
A0
F2D
CL
KF
2nC
SF
2ASD
I
F2D
AT
A0
F2D
CL
KF
2nC
SF
2ASD
I
F2n
CE
F2C
ON
FIG
_DO
NE
F2n
CO
NF
IG
F2n
ST
AT
US
R11
10K
R10
10K
R9
10K
+3.
3V
F2n
CE
R12
10K
F2C
ON
FIG
_DO
NE
F2n
ST
AT
US
TX
CL
KC
TX
CL
KO
C
TX
DC
0
TX
DC
1
TX
DC
2T
XD
C3
TX
DC
4
TX
DC
5
TX
DC
6
TX
DC
7
TX
CT
C0
TX
CT
C1
TX
DC
[7..
0]
TX
CT
C[1
..0]
RX
CL
KC
+
RX
CL
KC
-
RX
DC
0
RX
DC
1
RX
DC
2
RX
DC
3
RX
DC
4
RX
DC
5
RX
DC
6
RX
DC
7
RX
ST
C0
RX
ST
C1
RX
DC
[7..0
]
RX
ST
C[2
..0]
PT
XD
C[9
..0]
PR
XD
C[9
..0]
PR
XD
C0
PR
XD
C1
PR
XD
C2
PR
XD
C3
PR
XD
C4
PR
XD
C5
PR
XD
C6
PR
XD
C7
PR
XD
C8
PR
XD
C9
PT
XD
C0
PT
XD
C1
PT
XD
C2
PT
XD
C3
PT
XD
C4
PT
XD
C5
PT
XD
C6
PT
XD
C7
PT
XD
C8
PT
XD
C9
TX
CL
KD
TX
CL
KO
D
TX
DD
0T
XD
D1
TX
DD
2
TX
DD
3T
XD
D4
TX
DD
5T
XD
D6
TX
DD
7
TX
CT
D0
TX
CT
D1
TX
DD
[7..0
]
TX
CT
D[1
..0]
RX
CL
KD
+
RX
CL
KD
-
RX
DD
0
RX
DD
1
RX
DD
2
RX
DD
3
RX
DD
4
RX
DD
5
RX
DD
6
RX
DD
7
RX
ST
D0
RX
ST
D1
RX
DD
[7..0
]
RX
ST
D[2
..0]
PT
XD
D[9
..0]
PR
XD
D[9
..0]
PT
XD
D0
PT
XD
D1
PT
XD
D2
PT
XD
D3
PT
XD
D4
PT
XD
D5
PT
XD
D6
PT
XD
D7
PT
XD
D8
PT
XD
D9
PR
XD
D0
PR
XD
D1
PR
XD
D2
PR
XD
D3
PR
XD
D4
PR
XD
D5
PR
XD
D6
PR
XD
D7
PR
XD
D8
PR
XD
D9
C33
0.1
u
C34
0.1
u
C23
0.1
u
C24
0.1
u
C25
0.1
u
C26
0.1
u
C27
0.1
u
C28
0.1
u
C29
0.1
u
C30
0.1
u
C31
0.1
u
C32
0.1
u
+3.
3V+
1.5V
C22
0.1
u
+3.
3V
RX
ST
C2
RX
ST
D2
RC
LK
EN
C
RC
LK
EN
D
SPD
SE
LC
SPD
SE
LD
1 2 3
JB3
3PIN
1 2 3
JB4
3PIN
R7
0
R8
0
+3.
3V
+3.
3V
SPD
SE
LC
'
SPD
SE
LD
'
PT
XC
LK
C
PR
XC
LKC
PT
XC
LK
DP
RX
CLK
D
inse
ldT
16
txd
c[4
]T
17
ulcd
R17
spd
seld
R18
RE
SER
VE
D_I
NPU
TR
15
ulcc
R16
lpen
dP
16
txd
c[0
]P
17
inse
lcP
15
RE
SER
VE
D_I
NPU
TP
14
RE
SER
VE
D_I
NPU
TN
14
sd_
hdc
N18
cd_m
ute
cN
17
RE
SER
VE
D_I
NPU
TN
13
RE
SER
VE
D_I
NPU
TN
12
RE
SER
VE
D_I
NPU
TN
16
RE
SER
VE
D_I
NPU
TN
15
cd_m
ute
dM
18
ssi_
cdc2
M1
7
fclk
c_p
K16
fclk
c_n
K15
CO
NF
_DO
NE
K17
nST
AT
US
L12
TC
KK
18
TM
SK
14
TD
OK
13
GN
DG
_PL
L2
J18
GN
DA
_PL
L2
K12
txcl
koc
J16
rxcl
kc_p
J15
VC
CA
_PL
L2
J12
TD
IJ1
7
rxcl
kc_n
J14
RE
SER
VE
D_I
NPU
TG
13
RE
SER
VE
D_I
NPU
TG
14
RE
SER
VE
D_I
NPU
TG
15
led2
70c
G16
RE
SER
VE
D_I
NPU
TG
12
RE
SER
VE
D_I
NPU
TF
12
led5
40d
F18
led3
60d
F17
RE
SER
VE
D_I
NPU
TF
13
RE
SER
VE
D_I
NPU
TF
14
led7
425
dF
16
RE
SER
VE
D_I
NPU
TF
15
led2
70d
E1
7
ledl
fid
E1
6
RE
SER
VE
D_I
NPU
TE
15
ptxd
c[9]
D18
RE
SER
VE
D_I
NPU
TE
14
ledc
ddD
16
prxd
d[9
]D
15
led2
C17
ptxd
c[8]
D17
BA
NK
3
RE
SER
VE
D_I
NPU
TM
14
RE
SER
VE
D_I
NPU
TM
15
RE
SER
VE
D_I
NPU
TM
16
cd_m
ute
d2L
18
sd_
hdd
L17
RE
SER
VE
D_I
NPU
TM
13
RE
SER
VE
D_I
NPU
TL
13
RE
SER
VE
D_I
NPU
TL
16
RE
SER
VE
D_I
NPU
TL
15
RE
SER
VE
D_I
NPU
TL
14
RE
SER
VE
D_I
NPU
TJ1
3
RE
SER
VE
D_I
NPU
TH
13
RE
SER
VE
D_I
NPU
TH
14
RE
SER
VE
D_I
NPU
TH
15
led7
425
cH
16
led3
60c
H17
led5
40c
H18
ledl
fic
G18
ledc
dcG
17
U3C
EP
1C20
F32
4C8
txct
d[0]
U3
txcl
kdV
4
VC
CIN
TM
8
GN
DN
8
rxdc
[0]
T4
rxdd
[0]
U4
rxst
d[1
]T
5
txd
d[7]
U5
RE
SER
VE
D_I
NPU
TR
4
rxdc
[1]
R5
txd
d[6]
V6
txd
d[5]
U6
RE
SER
VE
D_I
NPU
TP
6
RE
SER
VE
D_I
NPU
TP
7
rxdd
[5]
T6
txd
d[3]
U7
txd
d[4]
V7
RE
SER
VE
D_I
NPU
TT
7
rxdc
[5]
R7
txd
d[0]
U8
txd
d[1]
V8
RE
SER
VE
D_I
NPU
TT
8
RE
SER
VE
D_I
NPU
TP
9
rxdd
[3]
T10
rxdc
[3]
R10
lfic
R11
rxdd
[2]
T11
RE
SER
VE
D_I
NPU
TU
11
txct
c[0]
V11
GN
DN
10
VC
CIN
TM
10
RE
SER
VE
D_I
NPU
TP
12
RE
SER
VE
D_I
NPU
TP
13
txd
c[1
]U
14
lfid
T14
rxdc
[6]
R14
spd
selc
V15
rclk
end
U15
VC
CIN
TN
11
GN
DM
11
txd
c[7
]U
16
lpen
cT
15
BA
NK
4
rxst
c[0]
R6
txer
rcU
9
txd
d[2]
V9
rclk
enc
R9
rxdd
[4]
T9
GN
DM
9
VC
CIN
TN
9
txd
c[6
]U
10
txcl
kcV
10
RE
SER
VE
D_I
NPU
TP
10
txd
c[3
]V
12
txd
c[2
]U
12
rxdd
[6]
T12
rxdc
[2]
R12
txd
c[5
]V
13
txct
c[1]
U13
rxdd
[7]
T13
rxdc
[7]
R13
rxdc
[4]
R8
U3D
EP
1C20
F32
4C8
fd[1
]C
3
fd[2
]C
2
fd[3
]D
3
fd[1
3]D
2
rdy[
1]D
4
fd[1
2]D
1
fd[4
]E
3
fd[5
]E
2
fd[1
0]F
1
RE
SER
VE
D_I
NPU
TE
4
RE
SER
VE
D_I
NPU
TE
5
fd[1
1]F
2
fd[6
]F
3
fd[7
]F
4
RE
SER
VE
D_I
NPU
TF
5
fd[8
]G
1
fd[9
]G
2
RE
SER
VE
D_I
NPU
TF
6
RE
SER
VE
D_I
NPU
TF
7
RE
SER
VE
D_I
NPU
TH
6
RE
SER
VE
D_I
NPU
TJ1
DA
TA
0H
7
nCO
NFI
GJ2
VC
CA
_PL
L1
J5
rxcl
kd_
pJ3
txcl
kod
J4
GN
DA
_PL
L1
K1
GN
DG
_PL
L1
J6
nCE
OK
2
nCE
J7
MS
EL
0K
3
MS
EL
1K
7
DC
LK
L1
RE
SER
VE
D_I
NPU
TK
6
fclk
d_p
K4
fclk
d_n
K5
RE
SER
VE
D_I
NPU
TM
4
RE
SER
VE
D_I
NPU
TN
1
RE
SER
VE
D_I
NPU
TN
2
RE
SER
VE
D_I
NPU
TM
6
RE
SER
VE
D_I
NPU
TN
7
RE
SER
VE
D_I
NPU
TN
5
RE
SER
VE
D_I
NPU
TN
6
RE
SER
VE
D_I
NPU
TN
3
RE
SER
VE
D_I
NPU
TN
4
RE
SER
VE
D_I
NPU
TP
5
RE
SER
VE
D_I
NPU
TP
2
rxst
d[2
]P
3
txer
rdR
1
rxst
c[2]
P4
rxdd
[1]
R2
rxst
c[1]
R3
txct
d[1]
T2
rxst
d[0
]T
3
BA
NK
1
ctl[
0]
G3
ctl[
1]
G4
RE
SER
VE
D_I
NPU
TG
5
RE
SER
VE
D_I
NPU
TG
6
pa7_
flag
d_sl
csH
1
rese
t_n
H2
ctl[
2]
H3
rxcl
kd_
nH
4
RE
SER
VE
D_I
NPU
TH
5
RE
SER
VE
D_I
NPU
TL
7
RE
SER
VE
D_I
NPU
TL
6
sdi
L2
scse
1L
3
RE
SER
VE
D_I
NPU
TL
5
RE
SER
VE
D_I
NPU
TL
4
sdo
M1
RE
SER
VE
D_I
NPU
TM
3
scl
M2
RE
SER
VE
D_I
NPU
TM
5
U3A
EP
1C20
F32
4C8
prxd
c[9]
C16
prxd
c[8]
B16
VC
CIN
TG
11
GN
DF
11
prxd
c[7]
B15
ptxd
c[7]
A15
ptxd
d[9]
C15
prxd
d[8
]D
14
prxd
c[6]
B14
ptxd
d[8]
C14
RE
SER
VE
D_I
NPU
TE
13
GN
DG
10
VC
CIN
TF
10
ptxd
d[5]
C11
prxd
d[5
]D
11
prxd
c[3]
B11
ptxd
c[4]
A11
ptxd
d[4]
C10
prxd
d[4
]D
10
RE
SER
VE
D_I
NPU
TE
10
ptxd
d[2]
C8
ptxd
c[1]
A8
prxd
c[0]
B8
RE
SER
VE
D_I
NPU
TE
8
RE
SER
VE
D_I
NPU
TE
7
ptxd
c[0]
A7
prxc
lkc
B7
ptxd
d[1]
C7
RE
SER
VE
D_I
NPU
TE
6
prxd
d[0
]D
6
clko
ut
B6
ptxd
d[0]
C6
ptxc
lkc
A6
ifcl
kB
5
ptxc
lkd
C5
prxc
lkd
D5
fd[1
5]A
4
fd[1
4]B
4
VC
CIN
TF
8
GN
DG
8
fd[0
]B
3
rdy[
0]C
4
BA
NK
2
prxd
c[5]
B13
ptxd
c[6]
A13
prxd
d[7
]D
13
ptxd
d[7]
C13
prxd
d[6
]D
12
ptxd
d[6]
C12
prxd
c[4]
B12
ptxd
c[5]
A12
prxd
c[2]
B10
ptxd
c[3]
A10
VC
CIN
TG
9
GN
DF
9
prxd
d[3
]D
9
ptxd
d[3]
C9
ptxd
c[2]
A9
prxd
c[1]
B9
prxd
d[2
]D
8
prxd
d[1
]D
7
RE
SER
VE
D_I
NPU
TE
11
U3B
EP
1C20
F32
4C8 VCCINT
A17VCCINT
A2VCCINT
B1VCCINT
B18VCCINT
H10VCCINT
J9VCCINT
K10VCCINT
L9VCCINT
U1VCCINT
U18VCCINT
V17VCCINT
V2
VCCIO1E1
VCCIO1G7
VCCIO1M7
VCCIO1P1
VCCIO2A14
VCCIO2A5
VCCIO2E12
VCCIO2E9
VCCIO3E18
VCCIO3H12
VCCIO3M12
VCCIO3P18
VCCIO4P11
VCCIO4P8
VCCIO4V14
VCCIO4V5
GNDA1
GNDA16
GNDA18
GNDA3
GNDB17
GNDB2
GNDC1
GNDC18
GNDH11
GNDH8
GNDH9
GNDJ10
GNDJ11
GNDJ8
GNDK11
GNDK8
GNDK9
GNDL10
GNDL11
GNDL8
GNDT1
GNDT18
GNDU17
GNDU2
GNDV1
GNDV16
GNDV18
GNDV3
POWER/GND
U3E
EP
1C20
F32
4C8
SPD
SE
LD
'
SPD
SE
LC
'
LP
EN
C
LP
EN
D
INS
EL
C
INS
EL
D
UL
CC
UL
CD
SD
I
SD
O
SC
L
SC
SE
1
F2n
CS
F2D
AT
A0
F2n
CO
NF
IG
F2D
CL
KF
2ASD
I
F2n
CE
RE
SET
#
TC
K
TD
I
TM
ST
DO
+1.
5V
+1.
5V
+1.
5VA C
152
0.1
u
C15
3
1n
+1.
5VA C
150
0.1
u
C15
1
1n
C15
7
0.1
u
C15
6
0.1
u
FD
[15.
.0]
CTL
[2..
0]
RD
Y[1
..0]
FD
[15.
.0]
FD
0
FD
1F
D2
FD
3
FD
4F
D5
FD
6F
D7
FD
8F
D9
FD
10
FD
11
FD
12
FD
13
FD
14
FD
15
CTL
[2..
0]C
TL0
CTL
1
CTL
2
RD
Y[1
..0]
RD
Y0
RD
Y1
CLK
OU
T
IFC
LK
PA
7/*
FL
AG
D/S
LC
S#
D23
LE
D2
D24
LE
D2
D25
LE
D2
D26
LE
D2
D21
LE
D2
D22
LE
D2
D17
LE
D2
D18
LE
D2
D19
LE
D2
D20
LE
D2
D15
LE
D2
D16
LE
D2
R18
6
221
R18
7
221
R18
8
221
R18
9
221
R19
0
221
R19
1
221
R18
0
221
R18
1
221
R18
2
221
R18
3
221
R18
4
221
R18
5
221
LF
IC
CD
C
L27
0C
L36
0C
L54
0C
L74
25C
LF
ID
CD
D
L27
0D
L36
0D
L54
0D
L74
25D
LF
ICC
DC
L27
0C
L36
0CL
540C
L74
25C
LF
ID
CD
D
L27
0D
L36
0DL
540D
L74
25D
D31
LE
D2
R19
7
221
+3.
3V
C18
6
0.1
u
C18
7
0.1
u
C18
8
0.1
u
C18
9
0.1
u
C19
0
0.1
u
C19
1
0.1
u
C19
2
0.1
u
C19
3
0.1
u
C19
4
0.1
u
C19
5
0.1
u
C19
6
0.1
u
C19
7
0.1
u
+3.
3V+
1.5V
C18
5
0.1
u
C18
4
0.1
u
TX
ER
RC
TX
ER
RD
FC
LK
D+
FC
LK
D-
FC
LK
C+
FC
LK
C-
R21
5
0R21
6
0
+C
251
10u
+3.
3V
Page 35 of 92
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Quad Independent Channel
HOTLink II™ CYV15G0404DXBVideo PHY Demonstration Board
Figure A-6. Parallel Interface Headers
11
22
33
44
55
66
DD
CC
BB
AA
LS
7652
Cypr
essM
olson
-Par
allel
Inter
face
s
206
12G
.C
osen
s
Siz
eD
raw
ing
Num
ber
Rev
isio
n
Dat
e:F
ile:
She
etof
Dra
wn
By:
Par
alle
lIn
terf
aces
.Sch
Doc
7/6/
2004
B
Line
arSy
stem
sLt
d.
PT
XD
A[9
..0]
PT
XD
B[9
..0]
PT
XD
C[9
..0]
PT
XD
D[9
..0]
PR
XD
A[9
..0]
PR
XD
B[9
..0]
PR
XD
C[9
..0]
PR
XD
D[9
..0]
PT
XD
A0
PT
XD
A1
PT
XD
A2
PT
XD
A3
PT
XD
A4
PT
XD
A5
PT
XD
A6
PT
XD
A7
PT
XD
A8
PT
XD
A9
PT
XD
B0
PT
XD
B1
PT
XD
B2
PT
XD
B3
PT
XD
B4
PT
XD
B5
PT
XD
B6
PT
XD
B7
PT
XD
B8
PT
XD
B9
PT
XD
C0
PT
XD
C1
PT
XD
C2
PT
XD
C3
PT
XD
C4
PT
XD
C5
PT
XD
C6
PT
XD
C7
PT
XD
C8
PT
XD
D0
PT
XD
D1
PT
XD
D2
PT
XD
D3
PT
XD
D4
PT
XD
D5
PT
XD
D6
PT
XD
D7
PT
XD
D8
PT
XD
D9
PR
XD
A0
PR
XD
A1
PR
XD
A2
PR
XD
A3
PR
XD
A4
PR
XD
A5
PR
XD
A6
PR
XD
A7
PR
XD
A8
PR
XD
A9
PR
XD
B0
PR
XD
B1
PR
XD
B2
PR
XD
B3
PR
XD
B4
PR
XD
B5
PR
XD
B6
PR
XD
B7
PR
XD
B8
PR
XD
B9
PR
XD
C0
PR
XD
C1
PR
XD
C2
PR
XD
C3
PR
XD
C4
PR
XD
C5
PR
XD
C6
PR
XD
C7
PR
XD
C8
PR
XD
D0
PR
XD
D1
PR
XD
D2
PR
XD
D3
PR
XD
D4
PR
XD
D5
PR
XD
D6
PR
XD
D7
PR
XD
D8
PR
XD
D9
PR
XD
A[9
..0]
PR
XD
B[9
..0]
PR
XD
C[9
..0]
PR
XD
D[9
..0]
PR
XD
C9
PT
XD
A[9
..0]
PT
XD
B[9
..0]
PT
XD
C[9
..0]
PT
XD
D[9
..0]
PT
XD
C9
12
34
56
78
910
1112
1314
1516
1718
1920
2122
JP1
5
HE
AD
ER
11X
2
12
34
56
78
910
1112
1314
1516
1718
1920
2122
JP1
4
HE
AD
ER
11X
2
12
34
56
78
910
1112
1314
1516
1718
1920
2122
JP1
7
HE
AD
ER
11X
2
12
34
56
78
910
1112
1314
1516
1718
1920
2122
JP1
6
HE
AD
ER
11X
2
12
34
56
78
910
1112
1314
1516
1718
1920
2122
JP1
9
HE
AD
ER
11X
2
12
34
56
78
910
1112
1314
1516
1718
1920
2122
JP1
8
HE
AD
ER
11X
2
12
34
56
78
910
1112
1314
1516
1718
1920
2122
JP2
1
HE
AD
ER
11X
2
12
34
56
78
910
1112
1314
1516
1718
1920
2122
JP2
0
HE
AD
ER
11X
2
PR
XC
LK
AP
TX
CL
KA
PR
XC
LK
B
PR
XC
LK
C
PR
XC
LK
D
PT
XC
LK
B
PT
XC
LK
C
PT
XC
LK
D
Page 36 of 92
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HOTLink II™ CYV15G0404DXBVideo PHY Demonstration Board
Figure A-7. Clocking and PSoC
11
22
33
44
55
66
DD
CC
BB
AA
LS
7652
Cypr
essM
olso
n-F
lexib
leCl
ock
&Co
nfig
urat
ion
207
12G
.Cos
ens
Siz
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raw
ing
Nu
mbe
rR
evis
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Dat
e:F
ile:
She
etof
Dra
wn
By:
Fle
xibl
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lock
&C
onfi
gura
tion
.Sch
Do
c7/
6/20
04
B
Line
arSy
stem
sLt
d.
CLI
AC
LIB
CLI
CC
LID
MC
LA
DJA
MC
LA
DJB
MC
LA
DJC
MC
LA
DJD
RE
FCL
KA
+
RE
FCL
KB
+
RE
FCL
KC
+
RE
FCL
KD
+
I2SC
LI2
SDA
RE
FCL
K+
3
RE
FCL
K-
4
PR
OG
CS
6
PR
OG
DI
7
PR
OG
SK8
LO
CK
ED
14
CLO
CK
OU
T-
21C
LOC
KO
UT
+22
GNDA32
GNDA25
FNVCF-30
FNVCF+31
WRVCF-26
WRVCF+27
VC
CA
24V
CC
A1
VC
CO
18
VC
C17
VC
C9
GN
D10
GND33
U10
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877
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FCL
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FCL
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4
PR
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CS
6
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7
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14
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GNDA25
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CA
24V
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CO
18
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C17
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C9
GN
D10
GND33
U11
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877
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FCL
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FCL
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4
PR
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CS
6
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OG
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7
PR
OG
SK8
LO
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14
CLO
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T-
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GNDA25
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CO
18
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C17
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C9
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D10
GND33
U13
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6
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CA
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CO
18
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C17
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C9
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D10
GND33
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877
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AI/
P0[7
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2
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3
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7]9
P4[
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P4[
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P4[
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P13
P3[
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P3[
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P3[
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P3[
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P5[
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P5[
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TA
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2]26
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4]/E
XT
CL
K27
P1[
6]28
P5[
0]29
P5[
2]30
P3[
0]31
P3[
2]32
P3[
4]33
P3[
6]34
XR
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35P
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36P
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37P
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38P
4[6]
39P
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C2
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2]/A
I(A
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Ref
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P0[
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P0[
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IO45
P0[
4]/A
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P0[
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R30
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1u
R23
2.0
KC
430.
1u
R24
2.0
KC
440.
1u
R27
2.0
KC
530.
1u
R28
2.0
KC
540.
1u
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3V+
3.3V
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3V+
3.3V
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3V+
3.3V
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3V+
3.3V
SC
LS
DO
SC
SA
SC
SB
SC
SD
SC
SC
+3.
3V
R41
147
R42
147
R51
121
R52
121
R33
100
R55
121
R56
121
R37
100
R53
121
R54
121
R36
100
R49
121
R50
121
R32
100
C50
0.1
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510.
1u
C52
0.1
u
C45
0.1
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460.
1u
C47
0.1
u
C60
0.1
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610.
1u
C62
0.1
u
C55
0.1
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560.
1u
C57
0.1
u
+3.
3V
+3.
3V
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3V
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3V
+3.
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SC
LS
DO
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SA
SC
SB
SC
SC
SC
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SD
I
SD
OS
CL
SC
SE
SD
I
SC
SE
OU
T8
VCC14
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R47
147
R48
147
R39
147
R40
147
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R45
147
R46
147
R19
0 R21
0
R22
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FCL
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8
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215
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16Q
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m
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m
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LO
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R19
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130
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LK
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FC
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i
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JP11
JP12
JP13
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NC
1
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2
GND3
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T4
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1
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74.2
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1
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GND3
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T4
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T5
VCC6
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74.2
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+3.
3V
+3.
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+3.
3V
OSC
A+
OSC
A-
OSC
D+
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D-
OSC
C+
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C-
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B-
OSC
B+
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10.
1u
C23
20.
1u
C23
30.
1u
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50.
1u
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70.
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6
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50oh
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50oh
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50oh
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Page 37 of 92
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HOTLink II™ CYV15G0404DXBVideo PHY Demonstration Board
Figure A-8. HOTLink II CYV15G0404DXB
11
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Page 38 of 92
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Figure A-9. Serial I/Os Top Level
11
22
33
44
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66
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Page 39 of 92
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Figure A-10. Serial I/O Interface (Primary)
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Page 40 of 92
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Figure A-11. Serial I/O Interface (Secondary)
11
22
33
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975
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HOTLink II™ CYV15G0404DXBVideo PHY Demonstration Board
Figure A-12. Power Supply
11
22
33
44
55
66
DD
CC
BB
AA
LS
7652
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olson
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Page 42 of 92
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HOTLink II™ CYV15G0404DXBVideo PHY Demonstration Board
Appendix B: PCB Manufacturing Files(GERBER Files)
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HOTLink II™ CYV15G0404DXBVideo PHY Demonstration Board
Figure B-1. Board Stackup
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HOTLink II™ CYV15G0404DXBVideo PHY Demonstration Board
Figure B-2. Top Overlay
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HOTLink II™ CYV15G0404DXBVideo PHY Demonstration Board
Figure B-3. Top Layer
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HOTLink II™ CYV15G0404DXBVideo PHY Demonstration Board
Figure B-4. Top Paste
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HOTLink II™ CYV15G0404DXBVideo PHY Demonstration Board
Figure B-5. Top Solder Mask
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HOTLink II™ CYV15G0404DXBVideo PHY Demonstration Board
Figure B-6. Internal Plane 1
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Figure B-7. Internal Plane 2
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HOTLink II™ CYV15G0404DXBVideo PHY Demonstration Board
Figure B-8. Midlayer 1
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HOTLink II™ CYV15G0404DXBVideo PHY Demonstration Board
Figure B-9. Internal Plane 3
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HOTLink II™ CYV15G0404DXBVideo PHY Demonstration Board
Figure B-10. Midlayer 2
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HOTLink II™ CYV15G0404DXBVideo PHY Demonstration Board
Figure B-11. Internal Plane 4
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HOTLink II™ CYV15G0404DXBVideo PHY Demonstration Board
Figure B-12. Internal Plane 5
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HOTLink II™ CYV15G0404DXBVideo PHY Demonstration Board
Figure B-13. Midlayer 3
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HOTLink II™ CYV15G0404DXBVideo PHY Demonstration Board
Figure B-14. Internal Plane 6
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HOTLink II™ CYV15G0404DXBVideo PHY Demonstration Board
Figure B-15. Midlayer 4
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HOTLink II™ CYV15G0404DXBVideo PHY Demonstration Board
Figure B-16. Internal Plane 7
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HOTLink II™ CYV15G0404DXBVideo PHY Demonstration Board
Figure B-17. Internal Plane 8
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HOTLink II™ CYV15G0404DXBVideo PHY Demonstration Board
Figure B-18. Bottom Overlay
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HOTLink II™ CYV15G0404DXBVideo PHY Demonstration Board
Figure B-19. Bottom Layer
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HOTLink II™ CYV15G0404DXBVideo PHY Demonstration Board
Figure B-20. Bottom Paste
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HOTLink II™ CYV15G0404DXBVideo PHY Demonstration Board
Figure B-21. Bottom Solder Mask
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HOTLink II™ CYV15G0404DXBVideo PHY Demonstration Board
Appendix C: PCB Assembly Files(Drill and Assembly)
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HOTLink II™ CYV15G0404DXBVideo PHY Demonstration Board
Figure C-1. Drill Placement
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HOTLink II™ CYV15G0404DXBVideo PHY Demonstration Board
Figure C-2. Assembly–Top View
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HOTLink II™ CYV15G0404DXBVideo PHY Demonstration Board
Figure C-3. Assembly–Bottom View
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HOTLink II™ CYV15G0404DXBVideo PHY Demonstration Board
Appendix D: Bill of Materials (BOM)of HOTLink II CYV15G0404DXB
Video Demo Board
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Table D-1. Bill of Materials for HOTLink II CYV15G0404DXB Video Demo Board
Qty Part No. Manufacturer Description Designator185 C0603C104K4RAC Kemet 0.1-µF 10% X7R ceramic 16V 0603 C1, C2, C3, C4, C5, C6,
C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C32, C33, C34, C35, C36, C37, C38, C39, C40, C43, C44, C45, C46, C47, C48, C49, C50, C51, C52, C53, C54, C55, C56, C57, C58, C59, C60, C61, C62, C65, C73, C81, C85, C94, C99, C100, C101, C107, C120, C122, C126, C127, C128, C129, C130, C131, C132, C133. C140, C141, C143, C144, C146, C148, C150, C152, C155, C156, C157, C159, C160, C161, C162, C163, C164, C165, C166, C168, C169, C252, C253, C254, C255, C256, C257, C258, C259, C170, C171, C172, C173, C174, C175, C176, C177, C178, C179, C180, C181, C182, C183, C184, C185, C186, C187, C188, C189, C190, C191, C192, C193, C194, C195, C196, C197, C219, C211, C212, C213, C214, C215, C216, C217, C218, C220, C221, C222, C223, C224, C225, C226, C229,C230, C231, C232, C233, C234, C235, C236, C237, C238, C239, C240, C246, C247, C248, C249, C261, C263, C264, C266, C267, C268, C269, C270, C271, C272, C273, C274, C275, C276, C277, C278, C279, C280, C281, C282, C283, C284, C285
2 T491C685K020AS Kemet CAPACITOR TANT 6.8-µF 20V 10% SMD C138, C1394 C0603C102K5RACTU Kemet CAP 1000-pF 50V CERAMIC X7R 0603 C147, C149, C151, C1531 C0603C472K5RACTU Kemet CAP 4700-pF 50V CERAMIC X7R 0603 C1583 TPSC686K016R0200 AVX CAPACITOR TANT 68-µF 20V 10% SMD C167, C262, C26516 T491C106K020AS Kemet CAPACITOR TANT 10-µF 20V 10% SMD C203, C204, C205, C206,
C207, C208, C209, C210, C241, C242, C243, C244, C245, C250, C251, C260
2 ECJ-1VC1H220J Panasonic 22-pF 5% NPO ceramic 50V 0603 C41, C421 T491D107M016AS Kemet 100-µF Tantalum 16V 7343 C633 T491C226K016AS Kemet 22-µF 10% Tantalum 16V 6032 C64, C66, C1544 C0805C105K4RAC CAP CERAMIC 1.0-µF 16V X7R 0805 C95, C198, C227, C228
Page 70 of 92
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HOTLink II™ CYV15G0404DXBVideo PHY Demonstration Board
43 ECJ-1VB0J225K Panasonic CAP 2.2-µF 6.3V CERAMIC X5R 0603 C67, C68, C69, C70, C71, C72, C74, C75, C77, C78, C79, C80, C82, C84, C86, C90, C91, C92, C93, C96, C97, C98, C102, C103, C104, C105, C106, C108, C109, C110, C111, C112, C114, C115, C116, C117, C119, C121, C124, C199, C200, C201, C202
9 C0603C103K5RAC Kemet 10-nF (0.01-µF) 10% X7R ceramic 50V C76, C87, C88, C89, C113, C118, C125, C142, C145
2 C0805C101K5GACTU Kemet 100-pF 0805 SMT Ceramic Cap C83, C1234 C0603C105K8PACTU Kemet CAP CERAMIC 1.0-µF 10V X5R 0603 C134, C135, C136, C1372 MMBD914 Fairchild
SemiconductorHigh Conductance Ultra Fast Diode D1, D2
28 SML-LX0603GW-TR Lumex Surface Mount LED, Half-Moon Solder Terminals
D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D30, D31
2 SDM40E20LS Diodes Inc. Schottky Barrier Diode D32, D331 RAPC722 Switchcraft Conn Power Jack Right Angle PCB 2.1
mmJ1
4 142-0701-301 Johnson Compo-nents
Right angle SMA jack J2, J3, J4, J5
1 787780-1 AMP Universal Serial Bus Type B Receptacle J2014 UCBBJE20-3 Trompeter Circuit Board Bulkhead Edge Mount
Coax BNC Style ReceptacleJ6, J7, J8, J9, J10, J11,J12, J13, J14, J15, J16,J17, J18, J19
4 * 0.075 36-140G-0 Mode 3X1 PIN JB1, JB2, JB3, JB41 640456-5 AMP 5X1 PIN FRICTION LOCK JB55 * 0.025 36-280G-0 Mode HEADER 1X2 JP1, JP2, JP3, JP4, JP268 * 0.1 36-280G-0 Mode HEADER 4X4 (2 X 2X4) JP10, JP11, JP12, JP138 90059-0009 Molex 0.1-inch shunt, 15µ gold plate JP10, JP11, JP12, JP138 * 0.275 36-280G-0 Mode HEADER 11X2 JP14, JP15, JP16, JP17,
JP18, JP19, JP20, JP213 * 0.125 36-280G-0 Mode HEADER 5X2 JP6, JP8, JP94 LL2012-F5N6K Toko America 5.6-nH 0805 Inductor L1, L2, L3, L41 BLM18BD102SN1D Murata FERRITE CHIP 1000-OHM 100-MA 0603 L104 LL2012-F10NK Toko America 10-nH 0805 Inductor L5, L6, L7, L81 LL2012-F8N2K Toko America 8.2-nH 0805 Inductor L91 LM2940CS-5.0 National
Semiconductor3-Terminal Positive Regulator Q1
1 LT1587CM-1.5 3-Terminal Positive Regulator Q2
Table D-1. Bill of Materials for HOTLink II CYV15G0404DXB Video Demo Board (continued)
Qty Part No. Manufacturer Description Designator
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21 ERJ-3GEY0R00V Panasonic RES ZERO-OHM 1/10W 5% 0603 SMD R1, R2, R7, R8, R19, R20,R21, R22, R192, R213,R214, R215, R216, R222,R223, R226, R227, R230,R231, R234, R235
5 ERJ-3GEYJ751V Panasonic RES 750-OHM 1/10W 5% 0603 SMD R113, R114, R115, R116,R117
8 ERJ-3GEYJ151V Panasonic RES 150-OHM 1/10W 5% 0603 SMD R118, R119, R120, R121,R122, R123, R124, R125
5 ERJ-3GEYJ102V Panasonic RES 1.0K-OHM 1/10W 5% 0603 SMD R13, R14, R15, R195,R200
8 ERJ-3EKF37R4V Panasonic RES 37.4-OHM 1/16W 1% 0603 SMD R130, R131, R132, R133,R134, R135, R136, R137
1 ERJ-3EKF1911V Panasonic RES 1.91K-OHM 1/16W 1% 0603 SMD R1461 ERJ-3GEYJ681V Panasonic RES 680-OHM 1/10W 5% 0603 SMD R1551 ERJ-3GEYJ472V Panasonic RES 4.7K-OHM 1/10W 5% 0603 SMD R164 ERJ-3EKF51R1V Panasonic RES 51.1-OHM 1/16W 1% 0603 SMD R160, R161, R162, R1631 ERJ-3EKF59R0V Panasonic RES 59.0-OHM 1/16W 1% 0603 SMD R1641 CT6W104 BC Components POT 100K 6-MM CERM SQ ST TOP R1651 ERJ-3EKF1541V Panasonic RES 1.54K-OHM 1/16W 1% 0603 SMD R1661 ERJ-3GEYJ105V Panasonic RES 1.0M-OHM 1/10W 5% 0603 SMD R16727 9C06031A2210FKHFT Yageo America RES 221-OHM 1/10W 1% 0603 SMD R168, R169, R170, R171,
R172, R173, R174, R175,R176, R177, R178, R179,R180, R181, R182, R183,R184, R185, R186, R187,R188, R189, R190, R191,R193, R196, R197
2 ERJ-3GEYJ222V Panasonic RES 2.2K-OHM 1/10W 5% 0603 SMD R17, R181 ERJ-3GEYJ361V Panasonic RES 360-OHM 1/10W 5% 0603 SMD R19410 ERJ-3EKF1300V Panasonic RES 130-OHM 1/16W 1% 0603 SMD R198, R199, R220, R221,
R224, R225, R228, R229,R232, R233
4 ERJ-3EKF10R0V Panasonic RES 10.0-OHM 1/16W 1% 0603 SMD R201, R202, R203, R2048 9C06031A22R0FKHT Yageo America RES 22.0-OHM 1/10W 1% 0603 SMD R205, R206, R207, R208,
R209, R210, R211, R2129 ERJ-3GEYJ202V Panasonic RES 2.0K-OHM 1/10W 5% 0603 SMD R23, R24, R25, R26, R27,
R28, R29, R30, R608 ERJ-3GEYJ103V Panasonic RES 10K-OHM 1/10W 5% 0603 SMD R3, R4, R5, R6, R9, R10,
R11, R1226 ERJ-3GEYJ101V Panasonic RES 100-OHM 1/10W 5% 0603 SMD R31, R32, R33, R34, R35,
R36, R37, R38, R61, R62,R63, R64, R65, R66, R67,R68, R69, R70, R71, R72,R73, R74, R75, R76, R77,R78
8 ERJ-3EKF1470V Panasonic RES 147-OHM 1/16W 1% 0603 SMD R39, R40, R41, R42, R45,R46, R47, R48
4 ERJ-3GEYJ820V Panasonic RES 82-OHM 1/10W 5% 0603 SMD R43, R44, R217, R2188 ERJ-3EKF1210V Panasonic RES 121-OHM 1/16W 1% 0603 SMD R49, R50, R51, R52, R53,
R54, R55, R56
Table D-1. Bill of Materials for HOTLink II CYV15G0404DXB Video Demo Board (continued)
Qty Part No. Manufacturer Description Designator
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36 ERJ-3EKF75R0V Panasonic RES 75.0-OHM 1/16W 1% 0603 SMD R59, R79, R80, R81, R82,R83, R84, R85, R86, R87,R88, R89, R90, R91, R92,R93, R94, R95, R96, R97,R98, R99, R100, R101,R102, R103, R104, R105,R106, R107, R108, R109,R110, R111, R112, R219
1 CYV15G0404DXB-BGC Cypress Independent Clock Quad HOTLink IITransceiver
U1
4 SY87729LHI Micrel 3.3V AnyClock Fractional N Synthesizer U10, U11, U12, U131 CY8C27643-24PVI Cypress PSoC Mixed Signal Array U141 APC08F08 Astec CONV DC-DC 25W 8VIN 3.3VOUT SMD U152 EP1C20F324C8 Altera Cyclone FPGA U2, U34 GS1528-CKA Gennum HD-LINX II Multi-Rate SDI Dual Slew-
Rate Cable DriverU16, U17, U18, U19
4 GS1524-CKD Gennum HD-LINX II Multi-Rate SDI AdaptiveCable Equalizer
U20, U21, U22, U23
1 CLC001AJE National Semiconductor
Serial Digital Cable Driver with AdjustableOutputs
U24
2 CLC014AJE National Semiconductor
Adaptive Cable Equalizer for High-SpeedData Recovery
U25, U26
1 GS9028-CKA Gennum GENLINX II Cable Driver with TwoAdjustable Outputs
U27
1 GS9024-CKB Gennum GENLINX II Automatic Cable Equalizer U281 CLC007AJE National
SemiconductorSerial Digital Cable Driver with DualComplementary Outputs
U29
2 EPCS4SI8 Altera Configuration device U4, U51 TPS3820-33 TI Processor Supervisory Circuit U61 CY7C68013-100AC Cypress EZ-USB FX2 USB Microcontroller High-
Speed USB Peripheral ControllerU7
1 24LC00/SN Microchip 128-bit I2C Bus Serial EEPROM(SOIC) U81 CY2DP314OI Cypress 1 of 2:4 Differential Fanout Buffer U91 SEL2431A-27.0000MHz
PE1144MV-27.0M Saronix Pletronics
27-MHz PECL OSCILLATOR MODULE X1
4 VF261-SL-74.25 MHzXO-500-DFC-205N-74.25 MHz
Valpey FisherVectron
74.25-MHz SMT OSCILLATOR +/-20ppm
X2, X3, X4, X5
1 ECS-240-20-4 ECS 24-MHz 20-pF load Crystal Y14 6-32 threaded Nylon standoffs4 6-32 Nylon screws1 LS7652 Rev 2 14 Layer PCB1 DTS060330UDC-P5P CUI Inc. Universal input 6V 20W power supply,
2.1-mm center-positive plug1 P012-006 Tripp Lite NEMA 1-15P to IEC 320 C7 power cable,
6'
Table D-1. Bill of Materials for HOTLink II CYV15G0404DXB Video Demo Board (continued)
Qty Part No. Manufacturer Description Designator
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Do not populate R57, R58, R126, R127,R128, R129, R138, R139,R140, R141, R142, R143,R144, R145, R147, R148,R149, R150, R151, R152,R153, R154, R156, R157,R158, R159
Table D-1. Bill of Materials for HOTLink II CYV15G0404DXB Video Demo Board (continued)
Qty Part No. Manufacturer Description Designator
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Appendix E: Unpacking HOTLink II CYV15G0404DXB Video Demo Board
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The software GUI must be installed from the resource CD included in the kit. Please follow instructions listed below for installingand running the various tests from the GUI.
HOTLink II CYV15G0404DXB Video Demo Board Software Set-up InstructionsOpen the CD that was supplied with the kit and locate the file named “HOTLink II Video Demo Board Set-up.exe” located in thezip file. Follow the on screen instructions to set up the GUI. This will install the GUI for the video demo board software to run onyour PC/Laptop. A Windows 2000/XP operating system environment is a minimum requirement to run the software. The followinginstructions on installation are based on the Windows XP operating system environment.
1. Locate the file HOTLink II Video Demo Board set-up.exe. Double click the icon.2. When a dialog box pops up to confirm installation, click “Yes” to continue (see
Figure E-1). This will launch the installation wizard.
3. Click “Next” to continue.
4. Select the folder where the HOTLink II Video Demo Board software will be installed, then click on “Next.”
Figure E-1. Software Set-up Dialog Box
Figure E-2. Software Set-up Wizard
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5. Select the Start menu folder in which the HOTLink II Video Demo Board shortcut will be created, then click on “Next.”
Figure E-3. Software Set-up Wizard 2
Figure E-4. Software Set-up Wizard 3
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6. Click on the check box to have the software icon installed either on desktop, or as a quick launch icon, or both, then click “Next.”
7. Click install to have the software installed.
Figure E-5. Software Set-up Wizard 4
Figure E-6. Software Set-up Wizard 5
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The HVDB icon will now be available on your Desktop and/or as a Quick Launch item in your taskbar (depending on yourselections during installation).
Connect the 6V DC power supply to the power supply jack (J1) on the board. The power LEDs on the board will turn on.
Connect the USB cable between the USB port of the video board and the PC/laptop. Once the USB connection from PC/laptopis made, the “Found New Hardware Wizard” will pop up indicating that new hardware has been detected and the drivers mayneed to be installed if they are not present. See Figure E-7.
1. Choose “Install the software automatically (Recommended)”, then click on “Next.”
2. If a warning window pops up as shown in Figure E-8, click on “Continue Anyway.”
Figure E-7. New Hardware Wizard
Figure E-8. Hardware Installation
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3. “Completing the Find New Hardware Wizard” will pop up. Click on “Finish.”
4. Click on the HVDB icon on your desktop or Quick Launch taskbar. The HVDB GUI should appear as shown in Figure E-15 indicating that and you have successfully installed the relevant software and hardware on the computer. However, if upon clicking the HDVB icon, the following warning dialog pops up, please follow the rest of the instructions in this section. Note. The dialog box shown is Figure E-10 will also appear if the GUI is launched while the board is powered down.
5. Go to Start -> Control Panel -> Add Hardware. This will bring up the Add Hardware Wizard as shown in Figure E-11. Click on “Next.”
Figure E-9. New Hardware Wizard 2
Figure E-10. HVDB Warning
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6. Make sure the USB cable is connected to the PC/laptop at this point. The “Yes, I have already connected the hardware” option should be checked by default. Click on “Next.”
Figure E-11. Add Hardware Wizard
Figure E-12. Add Hardware Wizard 2
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7. Select the “Cypress HOTLink II Video Demo Board” hardware already installed on the computer.
8. Click on “Finish” when the hardware is configured properly.
Figure E-13. Add Hardware Wizard 3
Figure E-14. Add Hardware Wizard 4
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• The GUI looks like the following.
Board Configuration InstructionsPlease note that the FPGAs and PSoC are preprogrammed at the factory, for testing purposes. Therefore, you should have noneed to perform the following steps. They are included as a reference should you ever need to reprogram the board.
1. Double click on the HDVB icon. The GUI should appear.2. Click on Tools ->FPGA Programming. A small dialog box should pop up as shown.
Click on FPGA1 (U2). This will bring up a File Open dialog box. Select “Hdvb0.pof”. Click on “Open”. The dialog box will have a“percentage complete” indicator which indicates if the erasing/programming is completed. The FPGA will first be erased, thenprogrammed. When “Programming U2 Complete” is indicated on top of the “percentage complete” bar, click on “Exit” to close thedialog box. The FPGA 1 (U2) is now configured. The series of status indications of the dialog box is shown in the following figures.
Figure E-15. HVDB Graphical User Interface
Figure E-16. GUI–FPGA Programming Dialog Box
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Click on FPGA2 (U3). This will bring up a “File Open” dialog box. Select “Hdvb1.pof.” Click on “Open.” The FPGA is configuredthe same way as in (1).
3. Click on Tools->PSoC Programming. A small dialog should pop up as shown. Click on “Program PSoC.” This will bring up a File Open dialog box. Select “Hdvb.hex.” Click on “Open.” PSoC is now configured.
Figure E-17. FPGA Programming Dialog Box 1
Figure E-18. FPGA Programming Dialog Box 2
Figure E-19. FPGA Programming Dialog Box 3
Figure E-20. GUI PSoC Programming Dialog Box
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Setting ConfigurationsOnce the user has configured the desired settings on the GUI, the settings selected can be saved to a file for future retrieval.Similarly, a user can retrieve a saved setting.• To save a current setting, click on File -> Save Settings, the “Save As” dialog box will prompt the user to enter a valid file name
and the setting for the GUI is saved as a configuration file with an “.ini” file extension. Click on “Save” to save the file. See Figure E-21.
• To load a saved setting, click on File -> Load Settings, the “Open” dialog box will prompt the user to select a valid existing configuration file. Click on “Open” to open the file. The GUI settings should be loaded with the new setting.
Figure E-21. GUI–Save/Load Settings
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Appendix F: Configuring the HOTLink II CYV15G0404DXB Video Demo Board for
SD-SDI to HD-SDI Upconversion
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OverviewThis appendix discusses the necessary modifications that need to be made to the CYV15G0404DXB video demo board, in orderfor it to be able to perform upconversion. The upconversion function described in this appendix is for functional verification only.Due to design constraints, the measured jitter will be higher than normal. If you have any questions about this feature pleasecontact Cypress’s Application Engineers.
UpconversionUpconversion is the process of manipulating SD video data to produce an HD version of the same video. An SD signal is scaledto the desired number of horizontal lines per frame, as well as the appropriate number of pixels per line. The resulting HD signalcan be used to drive a high-resolution projector or monitor.
Upconversion may be used in broadcast situations where SD video masters are provided to stations that wish to broadcast inHD. For example, if a show is produced in 480 line interlaced and is provided to a station that wishes to broadcast in 1080 lineinterlaced, an upconversion would be required. Upconversion can also be used when programming is broadcast in HD, butadvertisements are in SD format. An upconversion will enable the transmission of the advertisements in HD format.
In the CYV15G0404DXB video evaluation board, incoming SDI data that needs to be upconverted is input to the channel Breceiver of the HOTLink II device. The deserialized video data is processed by the FPGA where it is upconverted and transmittedthrough the channel A transmitter of the HOTLink II device. The upconversion process is comprised of two primary components:scaling of the video from 720 by 483 to 1440 by 1035 and conversion of the clock frequency from 27 MHz to 74.25/1.001 MHz.Figure F-1 shows the block diagram for upconversion through the CYV15G0404DXB video demo board.
Video ScalingTo perform the video scaling, the incoming SDI data is stored and scaled in up to seven line buffers. For each seven lines of SDIdata input, the first six lines are repeated twice, and the seventh line is repeated three times. The result is 15 lines of HD-SDIdata for each seven lines of SDI data in. The original SD-SDI image of 720 by 483 is converted to an HD-SDI image 1440 (720*2)by 1035 (483*15/7). This changes the aspect ratio of 4:3 (1.333:1) to [4*15]:[3*14] (1.429:1). The resulting image is stretchedvertically by about 7%, but matches the average line and frame rates for incoming and outgoing data. In order to generate HD-SDI line data, each pixel sample pair is repeated twice as follows.
CRnYnCBnYn+1 -> CRnY2nCBnYn+1Rn+1Yn+1CBn+1Yn+1
Figure F-1. SD-SDI to HD-SDI Upconversion Block Diagram
SD-SDI: SMPTE 259 (270 Mb/s)
HD-SDI: SMPTE 292 (1485/1.001 Mb/s)
REFCLK (FPGA Clock)
REFCLK (Programmable Clock)
Channel B Rx
Channel A Tx
FPGA (U2)
27 MHz
74.17 MHz
10
10
RXCLKB
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Clock Rate ConversionAs part of the upconversion process, the incoming SDI clock rate (27 MHz) must be converted to HD-SDI (half rate at 74.25/1.001MHz). To achieve this, both PLLs in FPGA(U2) are connected in series to get the correct frequency for transmitting. The 27-MHzclock rate from RXCLKB+ is passed through FPGA(U2), where the first PLL multiplies RXCLKB+ by 25/13, while the second PLLmultiplies the result by 10/7. This produces the desired half rate frequency of 74.17 MHz (74.25/1.001 MHz), which is sent to thereference clock for channel A (REFCLKA).
Board ModificationThe following describes the board modifications required to achieve the clock rate conversion.1. Connect JP13 (FCLKB+) and JP1 (RXCLKA+) as indicated in Figure F-2. Refer to Figure F-3 for location of the ground pins.
RXCLKB+ is connected to the first PLL in FPGA(U2), while the output of the PLL is internally connected to FCLKB+. Byconnecting JP13 and JP1 as indicated, the output of the first PLL (FCLKB+ output pin) is sent to the input of the second PLL(RXCLKA+ input pin) in FPGA(U2).
Figure F-2. Upconversion Board Modifications
Figure F-3. Ground Pin Location
Connect JP13 and JP1
Remove R205
Configure to FPGA clock
Configure to programmable clock
Configure to programmable clock
Ground Pins
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2.Remove resistor R205.The RXCLKA+ pin on FPGA(U2) is connected to the input of the second PLL in FPGA(U2). However, the RXCLKA+ outputpin of the CYV15G0404DXB chip is connected to the RXCLKA+ input pin of FPGA(U2). The removal of resistor R205 breaksthis connection and allows FCLKB to be routed through the second PLL.
3. .Configure clocking options to FPGA clock option for Channel A (JP11).This sets the reference clock for Channel A (REFCLKA) to the FPGA clock (FCLKA). Refer to theCYV15G0404DXB User’sGuide for further information on clocking options.
4. Configure clocking options to programmable clock option for Channels B, C, D.The block diagram for the resulting clock circuit is shown in Figure F-4.
Test ProcedureTransmission of the SD-SDI signal may be generated on either channel C or channel D. This application note will describe theconnections and settings required for upconverting an SD-SDI signal transmitted on channel C.
Board Connections1. Apply power to the board and connect the USB cable between the board and the computer.2. Connect output OUTC1 to input INB1 using a BNC cable.3. Connect output OUTA1 to the WFM700 using a BNC cable.Figure F-5 shows the required board connections.
Figure F-4. Upconversion Clock Circuit
FPGA(U2)
PLL 1 PLL 2 JP11RXCLKB+
FCLKB+
FCLKA+
FCLKA-
REFCLKA+
REFCLKA-
27MHz74.17 MHz
RXCLKB * (25/13) FCLKB * (10/7)
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GUI ConfigurationConfiguration of the CYV15G0404DXB GUI is comprised of the following steps. The typical settings are shown in Figure F-6.1. Enable an SD-SDI/SMPTE 259M-C signal by selecting 270 Mb/s in the Tx/Rx Rate Box of the GUI.2.Select “Up Convert Ch B” on channel A3.Run channels A, B, and C
Figure F-5. Upconversion Test Connections
MS Windowsbased PC
OU
TC1
OUTA1
INB
1
INA1
OUTD2
IND2
OUTD1
IND1
OU
TB1
INB
2
OU
TB2
INC
1
INC
2
OU
TC2
Tektronix WFM 700
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Figure F-6. Upconversion GUI Settings
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ResultsThe output of the upconverted signal may be verified by monitoring the output signal on any HD-SDI waveform monitor (exampleTektronix WFM 700). Figure F-7 and Figure F-8 show the output for an SD-SDI, HD-HDI, and upconverted HD-SDI signal respec-tively.
Unused active video samples in active outgoing video lines are set to black. This will result in the black bars at the sides of thevideo image in Figure F-8. Some active video lines at the top and bottom of the HD-SDI output are not used, and result in theblack bars above and below the image.
EZ-USB FX2 and HOTLink II are trademarks of Cypress Semiconductor Corporation. PSoC is a trademark of Cypress MicroSys-tems. Windows is a registered trademark of Microsoft Corporation. All product and company names mentioned in this documentare trademarks of their respective holders.
Figure F-7. SD-SDI Video Picture
Figure F-8. Upconverted HD-SDI Video Picture
Page 92 of 92© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the useof any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to beused for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize itsproducts for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypressproducts in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback
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