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IRP Review:A TEST CHIP FOR ELECTROMIGRATION STUDIESKarl Peterson (EE), Emmanuel Owusu (CprE), and Joshua Ellis (EE)

4/30/2010Iowa State UniversityEE492 – Senior Design II

Our project is special…

International collaboration

Product conceptualization & specification in addition to design

Integrated circuit (IC) rather than system design

Research-orientated objectives

Problem Statement Design a test chip to support

ISU research on electromigration & IC reliability

The chip must include test structures composed of actual metal interconnects in a modern silicon process

Must be capable of interfacing with a controller to allow electrothermal conditions in the chip to be varied and monitored.

The Big Picture Electromigration – a complex

physical phenomena that causes mechanical stress in metal interconnects

Important failure mechanism in ICs

Strong, non-linear dependence on current-density and temperature

Need models for electromigration that predict reliability under practical conditions

Electromigration in progress!

Electromigration testing Subject interconnects to

variable electrothermal stresses

Measure time-to-failure of many samples

Analyze statistics, develop models, fit data, etc.

Use accelerated lifetime technique

Very high temperatures and current densities!

Proposed Solution Proposed IC contains 8 identical

metal test structures Current-steering Digital-to-

Analog Converter provides 0-25mA to test structure

On-die analog temperature sensing circuits

Open-circuit detection Control logic with serial interface Process technology:

0.18 µm standard CMOS

System Diagram

DAC #2 DAC #3 DAC #4DAC #1

Test Structure

#1

Test Structure

#2

Test Structure

#3

Test Structure

#4

I<2>

Open-Circuit Detect

Open-Circuit Detect

Open-Circuit Detect

Open-Circuit Detect

I<3> I<4>I<1>

FAIL<1> FAIL<2> FAIL<3> FAIL<4>

Control Logic

...

I_EN

GND

VDD

I_WR_ENI_DATAADDR_WR_ENADDR_DATAFAIL

Temperature Sensor

Temperature Sensor

Temperature Sensor...

TEMP_1

TEMP_2

TEMP_3

Test Structure Single-layer metal

interconnect with serpentine pattern

Metal layer M1Width 0.23 µm

Equivalent length

Up to 11.5 mm

Thickness 210 nm

Material Cu

Test structure – detail Corners reinforced

to mitigate current crowding

Current-Steering DAC

Current range of 0 to 25 mA

7 bit resolution LSB Current – 200 µA Current-Steering

Architecture Binary-weighted sources Constant power

Open Circuit Detection Two inverters on the output

DAC0010110

Current-Steering DAC

Temperature sensor

Compact, CMOS-based sensor design

5 sensor distributed throughout the floor plan

Control Logic Serial interface Simple

protocol Low pin-count

Digital flow

Needed standard cell library for synthesis

Free, scalable library did not meet design rules of our process

Extensive work to customize , re-verify standard cells

Auxiliary blocks

Master current switch Reference-distribution

network

Physical Design Floorplan symmetry

to prevent uncontrolled experimental variables

Significant redundancy and reinforcement of non-test blocks for reliability

Final design is 860 µm x 860 µm

Top-Level Layout

Simulations & Verification Analog verification: relevant

performance parameters for each block tested over full PVT range with 500-run statistical simulations

Digital verification: functional simulations, timing analysis

System-level, mixed-signal verification: several long transient simulations covering typical operation sequence

Top-level Functional Simulation

#1 VDD rises

#2 Reference current starts

#3 <000> written to address reg.

#4 <0101010> written to address reg.

#5 master current switch enabled

#6 test current settles at predicted value

Questions? Comments?

Backup slides – test results DAC Temperature sensor Top-level functional

DAC Simulation Results

Temperature sensor – supply sensitivity, nominal design

Temperature Sensor – Stat. Sim.