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ProgrammableProgrammable LogicLogic DesignDesign
Grzegorz BudzyGrzegorz Budzyńń
LLectureecture 7:7:SequentialSequential circuitscircuits part 2part 2
Plan
• Sequential circuits – categories
• Regular sequential circuits
• FSM
• FSMD
Sequential circuits - categories
Sequential circuits - categories
• Based on the characteristics of the next-state logic, sequential circuits can be divided intothree categories:
– Regular sequential circuit
– FSM (finite state machine)
– FSMD (FSM with data path).
Sequential circuits - categories• Regular sequential circuit.
– The state transitions in the circuit exhibit a “regular”pattern, as in a counter or shift register. The next-state logic is constructed primarily by a predesigned, “regular” component, such as an incrementor or shifter.
s0
s2
s1s3
Sequential circuits - categories• FSM (finite state machine).
– The state transitions in the circuit do not exhibit a simple, repetitive pattern. The next-state logic is constructed by “random logic” and synthesized from scratch.
s0
s2
s1s3
Sequential circuits - categories• FSMD (FSM with data path).
– The circuit consists of a regular sequential circuit and an FSM.
– The two parts are known as a data path and a control path, and the complete circuit is known as an FSMD.
– This type of circuit is used to implement an algorithmrepresented by register-transfer (RT) methodology, which describes system operation by a sequence of data transfers and manipulations among registers.
Sequential circuits - categories• FSMD (FSM with data path).
– The job of the finite state machine is to sequence
operations on a datapath
Regular sequential circuits
Free running shift register
Universal shift register
Counter mod M
Finite State Machines (FSM)
Introduction
• An FSM (finite state machine) is used to model a system that transits among a finite number of internal states.
• The transitions depend on the current state and external input.
• Unlike a regular sequential circuit, the state transitions of an FSM do not exhibit a simple, repetitive pattern.
• Its next-state logic is usually constructed from scratch and is sometimes known as“random” logic.
Introduction – block diagram
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Introduction – FSM types
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Introduction
• An FSM is known as a Moore machine if the output is only a function of state:– Moore machine: output = func(current state)
• An FSM is known as a Mealy machine if the output is a function of state and external input:– Mealy machine: output = func(current state, inputs)
• Both types of output may exist in a complex FSM.
FSM advantages
• Their simplicity make it easy for inexperienced developers to implement with little to no extra knowledge (low entry level)
• Predictability (in deterministic FSM), given a set of inputs and a known current state, the state transition can be predicted, allowing for easy testing
• Due to their simplicity, FSMs are quick to design, quick to implement and quick in execution
FSM advantages• FSM has been around for a long time, as such it is
well proven even as an artificial intelligence technique, with lots of examples to learn from
• FSMs are relatively flexible. There are a number of ways to implement a FSM based system in terms of topology, and it is easy to incorporate many other techniques
• Easy to transfer from a meaningful abstract representation to a coded implementation
FSM advantages• Low processor overhead; well suited to domains
where execution time is shared between modules or subsystems. Only the code for the current state need be executed, and perhaps a small amount of logic to determine the current state.
• Easy determination of reachability of a state, when represented in an abstract form, it is immediately obvious whether a state is achievable from another state, and what is required to achieve the state
FSM disadvantages
• The predictable nature of deterministic FSMs can be unwanted in some domains such as computer games (solution may be non-deterministic FSM).
• Larger systems implemented using an FSM can be difficult to manage and maintain without a well thought out design.
• The conditions for state transitions are ridged, meaning they are fixed (this can be over come by using a Fuzzy State Machine (FuSM))
FSM disadvantages
• Not suited to all problem domains, should only be used when a systems behavior can be decomposed into separate states with well defined conditions for state transitions.
• All states, transitions and conditions need to be known up front and be well defined
FSM representation
• An FSM is usually specified by:– an abstract state diagram
– ASM chart (algorithmic state machine chart)
• The two representations provide the same information in a graphical representation– the FSM's input,
– the FSM's output,
– the FSM's states,
– states transitions.
State diagram• A state diagram is composed of nodes, which
represent states and are drawn as circles, and annotated transitional arcs
• A logic expression expressed in terms of input signals is associated with each transition arc and represents a specific condition
• The arc is taken when the corresponding expression is evaluated true
• The Moore output values are placed inside the circle, the Mealy outside
State diagram
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ASM chart
• An ASM chart is composed of a network of ASM blocks.
• An ASM block consists of one state box and an optional network of decision boxes and conditional output boxes
• A state box represents a state in an FSM, and the asserted Moore output values are listed inside the box.
• A decision box tests the input condition and determines which exit path to take.
ASM chart
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State diagram vs ASM chart
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State diagram vs ASM chart
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State diagram vs ASM chart
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FSM code
• The procedure of developing code for an FSM is similar to that of a regular sequential circuit
• It is very convinient to use enumerated types to represent the FSM states
• E.g.:
• During synthesis, software automatically maps the values in an enumerated data type to binary representations, a process known as state assignment.
FSM design steps
1) Define/Specify Input/Output Signals
2) Define/Specify Control Signals
3) Design the Controller ASM Chart
4) Realize Controller in HDL
5) Validate Design/Perform Timing Analysis
FSM design steps – Moore machine
• TWO processes for Moore machine:– One process is used to model the state registers
to decide the next state
– Second process models to update the next stateand output logic
FSM design steps – Mealy machine
• TWO or THREE processes for Mealy machine:– One process is used to model the state registers
to decide the next state
– Second process models to update the next state
– Third process models the output logic
– OR 2nd and 3rd combined into one process
Moore machine example
Moore machine example
state diagram
X’
XX
X
X’
X’
1/2
2/2
Mealy machine example
Mealy machine example
state diagram
S0
S2
S1S3X
’/Z<=Y
X’/Z
<=Y
X/Z
<=Y
X’/Z<=1
X/Z<=Y
X/Z<=Y
1/3
2/3
3/3
Finite State Machines with Data
path (FSMD)
Introduction• An FSMD (finite state machine with data path)
combines an FSM and regular sequential circuits.
• The FSM, which is sometimes known as a control path, examines the external commands and status and generates control signals to specify operation of the regular sequential circuits, which are known collectively as a data path.
• The FSMD is used to implement systems described by RT(register transfer) methodology, in which the operations are specified as data manipulation and transfer among a collection of registers
Register Transfer Methodology
• A simple „dataflow” type implementationfeatures:– Simplicity
– No memory elements
– Algorithm is converted into combinational circuit
• Drawbacks of the „dataflow” typeimplementation :– Can only be applied to trivial algorithm
– Not flexible
Register Transfer Methodology• Algorithm is realized in hardware
• Registers are used to store intermediate data and
imitate variable
• Data path is used to realize all register operations
• Control path (FSM) is used to specify the order of
register operation
• The system is specified as sequence of data
manipulation/transfer among registers
• Realized by FSM with a data path (FSMD)
Single RT operation
• Basic form:
• An RT operation specifies data manipulation and transfer for a single destination register
• The contents of the source registers are fed to the internal circuit by a combinational circuit
• The result is passed to the input of the destination register and stored in the destination register at the next rising edge of the clock
Single RT operation
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FSMD block diagram• FSMD is divided into a data path and a control
path
• The data path performs the required RT operations. The control path is an FSM.
• FSMD consists of:– Data registers: store the intermediate computation
results
– Functional units: perform the functions specified by the RT operations
– Routing network: routes data between the storage registers and the functional units
FSMD block diagram
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FSMD block diagram• FSMD should be described behaviorally
FSMD block diagram• Structural description is much more difficult to
read
Example – division circuit
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Example – division circuit• Algorithm:
– 1. Double the dividend width by appending 0’s in front and align the divisor to the leftmost bit of the extended dividend.
– 2. If the corresponding dividend bits are greater than or equal to the divisor, subtract the divisor from the dividend bits and make the corresponding quotient bit Otherwise, keep the original dividend bits and make the quotient bit 0.
– 3. Append one additional dividend bit to the previous result and shift the divisor to the right one position.
– 4. Repeat steps 2 and 3 until all dividend bits are used.
Example –
division circuit
sta
rt’
n_
next!
=1
Example – division circuit
Example – division circuit
Example – division circuit
Thank you for your attention
References[1] „Combinational Circuits”, http://www.cs.Princeton.EDU/~cos126
[2] http://www.cs.umbc.edu/portal/help/VHDL/
[3] http://eesun.free.fr/DOC/vhdlref/refguide/language_overview/objects__data_types_and_operators/understanding_vhdl_attributes.htm
[4] http://www.xilinx.com/itp/xilinx10/books/docs/cgd/cgd.pdf
[5] http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf
[6] http://highered.mcgraw-hill.com/sites/dl/free/0072460857/173199/vra60857_ch06.pdf
[7] http://ftp.utcluj.ro/pub/users/calceng/SSC/Ssc06/SSC06-e.pdf
[8] http://vhdl.renerta.com/source/vhd00058.htm
[9] http://teacher.sicnu.edu.cn/upload/liaolei/file/560486551.pdf
[10] http://www.lcc.ufrn.br/~mocruz/VHDL.pdf
[11] http://www.eit.lth.se/fileadmin/eit/courses/eitf35/2011/Slides/L03_FSMD.pdf
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