Power Dissipation - University of Waterloomhanis/ece637/lecture9.pdf · Thus, the choice of V T...

Power DissipationPower Dissipation

Where Does Power Go in CMOS?Where Does Power Go in CMOS?

• Dynamic Power Consumption

• Short Circuit Currents

• Leakage

Charging and Discharging Capacitors

Short Circuit Path between Supply Rails during Switching

Leaking diodes and transistors

Dynamic Power DissipationDynamic Power Dissipation

Energy/transition

Power = Energy/transition * f = CL * Vdd2 * f

Need to reduce CL, Vdd, and f to reduce power.

Vin Vout

CL

Vdd

From equation, not a function of transistor sizes! (In reality it is)

Each time the capacitor gets charged through the PMOS transistor, its voltage rises from 0 to VDD, and a certain amount of energy is drawn from the power supply. Part of this energy is dissipated in the PMOS device, while the remainder is stored on the load capacitor. During the high-to-low transition, this capacitor discharged, and the stored energy is dissipated in the NMOS transistor.

∫∫∫ ====∞∞ DDV

DDLoutDDLout

LDDDDDDVDD VCdvVCdtdt

dvCVdtVtiVE

0

2

00

)(

f represents the frequency of energy-consuming transitions (0 -> 1)

Modification for Circuits with Reduced Swing

CL

Vdd

Vdd

Vdd -Vt

E0 1→ CL Vdd Vdd Vt–( )••=

Can exploit reduced swing to lower power(e.g., reduced bit-line swing in memory)

Node Transition Activity and PowerNode Transition Activity and PowerConsider switching a CMOS gate for N clock cycles

EN CL Vdd• 2 n N( )•=

n(N): the number of 0->1 transition in N clock cycles

EN : the energy consumed for N clock cycles

Pavg N ∞→lim

ENN

-------- fclk•= n N( )N

------------N ∞→

lim C•

LVdd•

2 fclk•=

α0 1→n N( )

N------------

N ∞→lim=

Pavg = α0 1→ C• LVdd• 2 fclk•

Short Circuit CurrentsShort Circuit Currents

Vin Vout

CL

Vdd

I VD

D(m

A)

0.15

0.10

0.05

Vin (V)5.04.03.02.01.00.0

How to keep ShortHow to keep Short--Circuit Currents Low?Circuit Currents Low?

Vin

Vout

CL

Vdd

Isc~ 0

Vin Vout

CL

Vdd

Isc~ Imax

Large CL

Small CL

LeakageLeakage

Vout

Vdd

Sub-ThresholdCurrent

Drain JunctionLeakage

Sub-threshold current one of most compelling issuesin low-energy circuit design!

Np+ p+

Reverse Leakage Current

+

-Vdd

GATE

IDL = JS × A

SubthresholdSubthreshold Leakage ComponentLeakage ComponentCurrent does not drop abruptly to 0 at VGS=VT. The device is partly conducting -> subthreshold conduction or weak-inversion conduction. Current decays in an exponential fashion for VGS< VT .The current in this region is approximated by:

0 0.5 1 1.5 2 2.510-12

10-10

10-8

10-6

10-4

10-2

VGS(V)

I D(A

)

VT

Exponential

The closer the threshold voltage is to zero, the larger the subthreshold leakage current at VGS=0V

Thus, VT is not kept smaller than 0.4V. However, with scaling of VDD, this results in a loss of performance.

Thus, the choice of VT presents a trade-off between static power and performance (Use of dual-VT).

Device designers try to reach the highest Ion/Ioff for a device, with a sharp turn-off characteristics.

Performance vs. Power TradePerformance vs. Power Trade--offs.offs.

Leakage currents cause a rise in static power.

This is offset by dropping VDD, which is enabled by reducing VT at no cost in performance, and results in quadratic reduction in dynamic power.

For a 0.25um CMOS process, circuit configurations obtain the same performance with: 3V supply – 0.7V VT; and 0.45V supply – 0.1V VT.

How are those 2 cases compared in terms of dynamic and static power?

Static Power ConsumptionStatic Power Consumption

Vin=5V

Vout

CL

Vdd

Istat

Pstat = P(In=1).Vdd . Istat

Wasted energy …Should be avoided in almost all cases

Principles for Power ReductionPrinciples for Power Reductionq Prime choice: Reduce voltage!§ Recent years have seen an acceleration in supply voltage

reduction§ Design at very low voltages still open question (0.6 … 0.9 V

by 2010!)q Reduce switching activity (at logic level)q Reduce physical capacitance§ Device Sizing: for F=20

– fopt(energy)=3.53, fopt(performance)=4.47

Power-Delay-Product (PDP) is used as a metric to balance between low delay and power.

Impact ofImpact ofTechnology Technology ScalingScaling

Goals of Technology ScalingGoals of Technology Scaling

qMake things cheaper:§ Want to sell more functions (transistors)

per chip for the same money§ Build same products cheaper, sell the

same part for less money§ Price of a transistor has to be reduced

qBut also want to be faster, smaller, lower power

Technology ScalingTechnology Scaling

q Goals of scaling the dimensions by 30%:§ Reduce gate delay by 30% (increase operating

frequency by 43%)§ Double transistor density§ Reduce energy per transition by 65% (50% power

savings @ 43% increase in frequency

q Die size used to increase by 14% per generation

q Technology generation spans 2-3 years

Technology Evolution (2000 data)Technology Evolution (2000 data)

International Technology Roadmap for Semiconductors

18617717116013010690Max µP power [W]

1.4

1.2

6-7

1.5-1.8

180

1999

1.7

1.6-1.4

6-7

1.5-1.8

2000

14.9-3.6

11-37.1-2.53.5-22.1-1.6Max frequency [GHz],Local-Global

2.52.32.12.42.0Bat. power [W]

109-10987Wiring levels

0.3-0.60.5-0.60.6-0.90.9-1.21.2-1.5Supply [V]

30406090130Technology node [nm]

20142011200820042001Year of Introduction

Node years: 2007/65nm, 2010/45nm, 2013/33nm, 2016/23nm

Technology Evolution (1999)Technology Evolution (1999)

Technology Scaling (1)Technology Scaling (1)

Minimum Feature SizeMinimum Feature Size

1960 1970 1980 1990 2000 201010

-2

10-1

100

101

102

Year

Min

imum

Fea

ture

Siz

e (m

icro

n)

Technology Scaling (2) Technology Scaling (2)

Number of components per chipNumber of components per chip

Technology Scaling (3)Technology Scaling (3)

Propagation DelayPropagation Delay

tp decreases by 13%/year50% every 5 years!

Transistor ScalingTransistor Scaling(velocity(velocity--saturated devices)saturated devices)

2010 Outlook2010 Outlook

q Performance 2X/16 months§ 1 TIP (terra instructions/s)§ 30 GHz clock

q Size§ No of transistors: 2 Billion§ Die: 40*40 mm

q Power§ 10kW!!§ Leakage: 1/3 active Power

P.Gelsinger: µProcessors for the New Millenium, ISSCC 2001

Some interesting questionsSome interesting questions

qWhat will cause this model to break?qWhen will it break?qWill the model gradually slow down?§ Power and power density§ Leakage§ Process Variation