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Penn ESE370 Fall2013 -- DeHon1
ESE370:Circuit-Level
Modeling, Design, and Optimization for Digital Systems
Day 28: November 15, 2013
Memory Periphery
Today
Memory Periphery
• Sensing
• Driving
• Decode
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Sensing
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SRAM Memory bit
Simulation Waccess=20
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Sense Small Swings
• What do we have to worry about?
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Sense Small Swings
• Variation– Shift where inverter trip point is
• Systematic shifts that effect both lines– “Common mode” noise– E.g.
• Noise• Voltage droop
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Two Sense Amps
1. Clocked / Regenerative Feedback
2. Not clocked / Differential Sense Amp
• Goal: amplify small signal difference
reject common mode noise
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Differential Sense Amp
• Goal:– Reject
common shift
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Warmup
• What does this do?
• How do we size transistor?
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Voltage Controlled
• Consider Vctrl asan analog inputbetween 0 and Vdd-Vth
• What does this do?
• How does the voltage on Vctrl control operation?
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DC Transfer
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Idea• Control Resistance to control trip point
• Set trip point based on second line
• Q: how set Vctrl?
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Differential Sense Amp
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What does this do?
• Output when:– In=Gnd?– In=Vdd?– Transfer curve?
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“Inverter”
• Input high– Ratioed like
grounded P
• Input low– Pulls itself up
– Until Vdd-VTP
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DC Transfer Function
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Differential Sense Amp
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Diffamp Transfer Function• in=/in, looks like “inverter”
• Deliberately low gainin mid region
• Ideal might be flat?
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Differential Sense Amp
• “Inverter” output controls PMOS for second inverter
• Sets PMOS operating point– Voltage controlled
resistance– Sets trip point
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Differential Sense Amp
• What happens wheno /in > in?o /in < in?
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Differential Sense Amp
• View:– Current mirror– Biases where
inverter operating
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Differential Sense Amp
• View:– adjusting the pullup
load resistance– Changing the trip
point for “inverter”
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DC Transfer /in with in=0.5V
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DC Transfer Various in
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DC Transfer Various in
• What is trip point when:
• In=0.3V?• In=0.4V?• In=0.5V?• In=0.6V?• In=0.7V?
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After Inverter
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Ramp 50mV Offset
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Closeup 50mV Offset
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Differential Sense Amp
• Does need to be sized
• There is a ratioed logic effect here
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Regenerative Feedback
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Connect to Column
• Equalize lines during precharge
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Singled-Ended Read
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5T SRAM
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Single Ended
• Given same problems– How sense small swing on single-ended
case?
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Single Ended
• Need reference to compare against
• Want to look just like bit line
• Equalize with bit line
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Split Bit Line
• Split bit-line in half
• Precharge/equalize both
• Word in only one half– Only it switches
• Amplify difference
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Open Bit Line Architecture
• For 1T DRAM
• Add dummy cells
• Charge dummy cells to Vdd/2
• “read” dummy in reference half
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Memory Bank
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Row Select
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Memory Bank
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Row Select
• Logically a big AND– May include an enable for timing in
synchronous
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How tall is a row?
• Side length for cell of size:– 1000 2
– 600 2
– 100 2
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44
How tall is an AND?
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2
66
3
2
2
44
Row Select
• How can we do better?– Area– Delay– Match to pitch of
memory row
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Row Select
• Compute inversions outside array– Just AND appropriate line (bit or /bit)
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Row Select
• Share common terms
• Multi-level decode
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Row Select
• Same number of lines
• Half as many AND inputs inside the rowPenn ESE370 Fall2013 -- DeHon
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Row Select: Precharge NAND
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Row Select: Precharge NOR
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Bus Drivers
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Memory Bank
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Tristate Driver
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Tri-State Drivers
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Idea
• Minimize area of repeated cell• Compensate with periphery
– Amplification (restoration)
• Match periphery pitch to cell row/column– Decode– Sensing– Writer Drivers
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Admin
• Monday: in Detkin Lab– Read lab2 assignment before coming to class
• Tuesday: Proj2 Milestone due
• Wednesday: Lecture
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