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8/2/2019 Patterning Troubles
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Patterning Troubles for
Standard CellsDavid Pietromonaco
ARM R&D
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Contents
Why double patterning?
Introduction Types of double patterning
What is stitching?
Trouble for Standard cells
LOTS of trouble for standard cells
Average density vs. Peak density
More trouble for standard cells
It gets even worse for standard cells, too
A few words about contacts
Conclusions
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Why Double Patterning?
Its been looming in the room for some time due to the
physics Nobody wanted to acknowledge it, really
Much harder for everybody foundry, designers, tools
Scaling has reached levels such that double patterning cant
be ignored, anymore.
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Double Patterning Introduction
Scaling to the bitter end of optical lithography
~200nm illumination wavelength the current standard
making ~20nm features with that isnt really possible without tricks
Limit is about 80nm pitch for parallel lines, 100nm for vias.
By the way, 20nm is as small as the smallest viruses
EUV isnt really optical and it isnt ready.
E-beam lithography isnt ready, either.
Double patterning necessary to keep scaling going until someother way to image patterns becomes available.
Several types of double patterning fall into 3 main categories
Double patterning you dont know about no obvious restrictions
No frequency doubling, either, only fractional improvement
Non self aligned double patterning for frequency doubling
Self aligned types of double patterning for frequency doubling
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Double Patterning Types (1)
The ones you dont know about
Foundries have been using asymmetrical illumination and doublepatterning occasionally and quietly.
You can think of this as breaking up the horizontal lines from thevertical lines and shooting each set with light optimized for each*
One exposure to squeeze horizontal
Additional exposure to squeeze vertical
Rules are nearly the same as what youve
been used to all along.
Dont get true frequency doubling this way
Helped get us to 80nm bidirectional line pitches!
Need something with more enhancement power to get morescaling than this
*Its not quite that simple of course, but it is basically the same net effect
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Double Patterning Types (2)
Non Self Aligned Double Patterning (LELE, Pitch Split, etc.)
The simplest form of frequency doubling double patterning
Simply create the layer in two steps.
Each time create a different part of it
You can double frequency by
alternating the exposure of objects This is currently the most mature
method.
For design tools and processing
Easiest to work with Stitching can be allowed
Different sized objects can be allowed
Well discuss this the most.
Step1
PlusStep
2
Final
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Wait, what is stitching?
Stitching simply refers to merging objects from the two
processing steps. So, from our previous example:
Step1
PlusStep
2
Final
Stitch
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Double Patterning Types (3)
Self aligned double patterning
The most difficult types because the patterning correlates moreclosely to the spaces between what you are trying to create
This is true for design tools, humans and processing
Two main types
Both use the sidewalls of printed objects as the foundation forcreating the desired objects
Since each printed object has two sidewalls in each direction,frequency doubling occurs.
Sadly, one type cannot be stitched, the other type cannot
have different width lines The unstitchable kind is the simpler one and gaining some attention.
For layout rules, it is basically the same as non self aligneddouble patterning but stitching is not allowed.
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Pictures! We like Pictures!
(Try not to think too hard how this works on complicated layout)
DesiredLayout
SacrificialMandrel
Sidewall
Block Mask
DesiredLayout
Is Metal Is Dielectric
Fixed width metal onlyVariable spacing
Stitching possible
Variable width metalFixed spacing
Stitching not possibleMost common SASL type
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Trouble for Standard Cells
Two patterns can be used to put any two objects close together
Subsequent objects must be spaced at the same-mask spacing Which is much, much bigger
Classic example: horizontal wires running next to vertical ports
Bad
OK
Bad
OK
OK OK
OK OK
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More Trouble for Standard Cells
If there are two horizontal metal tracks, it can be even worse
Any use of stitching means the second track has to also moveout to the same-layer spacing
Stitching is pretty common, too
in folded circuits
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Even More Trouble for Standard Cells
Power rails further complicate things
Via spacing, metal tips, etccan all create even more problems ????
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Average Density Vs. Peak Density
What just happened?
Our worst case cell size just exploded by adding 2 tracksworth of same-mask spacing to each side (only the top wasshown)
Eg. 9 track cell just became 13
Defeats the whole purpose of double patterning then!
But not all cases are the worst cases
Unfortunately, the cases that have only two objects involvedhistorically had some other way to solve them so no gain
IE. If you had a problem tip-side space and nothing else nearby, youcould change the tip to an L shape and get the side-side spacing.
Average density is actually closer to the same-mask density,not the different-mask density
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Yet Even More Troubles for Cells
Patterning difficulties dont end, there.
No small U shapes
No opposing L sandwiches
So several popular structures cant be made
No ColoringSolution
Have to turnvertical overlaps
into horizontal ones
But that blocksneighboring sites
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The Problems Keep On Coming
Some processes may not allow stitching
May be preparing for SASL
Or just think explicitly drawing two mask layers is too confusing
Either way, it is terribly difficult to solve
And cant just add pitches vertically to fix IT NEVER SOLVES
This can neverbe solved
without stitching
Have to usesome other layer
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Do the Troubles for Cells Ever Stop?!?
If all that were the total of problems, it might not be so bad
Actually, it would be pretty bad. But it gets even worse, though.
Minimum metal areas arent decreasing as rapidly as the
scaling
Double patterning doesnt help this at all
Ports are relatively huge
Can hardly fit a M1 landing pad to jump straight to M2.
You wouldnt be jumping to M2 if you had room on M1
And minimum M2 blocks more ports than it used to, making multipleports in a row a big problem, too.
Dont even get me started on contact scaling
Or lack thereof
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A Few Words About Contact Scaling
Contact density slipping even farther behind line density
So far behind, they arent even small enough to contact diffusion
Entering the local interconnect age for the same reasonswere entering the double patterning age
Sadly, local interconnect doesnt really help standard cells
very much. Safe cells have transmission gates in their feedback inverters
Theres generally no connection from diffusion to neighboring poly
Helps memory cells more
Generally only useful to offset various connections a little bit
But you still have contacts to connect to the local interconnect
And the pitches for those contacts are still pretty large
So it only got more complicated, not really better
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Conclusions
The double patterned elephant is here to say in the room
It cant be avoided
It makes layout much more challenging
Cell density estimates need to be realistic
Cant achieve full double patterning scaling due to the interaction
limitations of double patterning
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