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Multitrack Power Factor Correction Architecture
Minjie Chen, Sombuddha Chakraborty, David Perreault
Princeton University
Texas Instruments
Massachusetts Institute of Technology
978-1-5386-1180-7/18/$31.00 ©2018 IEEE 1713 1 of 20
Typical isolated PFC architectures
2 of 20
Design targets:
(1)Higher efficiency
(2)Higher density
(3)Better grid interface
Challenges and opportunities:
(1)Smaller passive component size
(2)Higher frequency
(3)ZVS with universal input
Vgrid
Diode
RectifierPower Factor
Correction
Isolated dc-dc
Converter
RloadLR
n:1
CB
VB
+
Energy
Buffer
Needed in a wide range of applications
Telecom supplies / EV chargers / Adapters / Industry Applications
Existing solutions and design targets
3 of 20
TI UCC25600 PFC DemoConventional “single-target” methods
• Diode loss: bridgeless, totem-pole
• Boost inductor: FCML, Ćuk/SEPIC
• Energy buffer size: active energy buffer
• Isolated dc-dc efficiency: DAB, LLC
• Smaller magnetics: higher frequency
Develop a systems method to create mutual advantages
o New architecture
o 5x - 10x Higher frequency
o 50W/inch3, 92% efficiency
~ 10W/inch3, 200kHz
~ 92% efficiency
5x smaller ?
Multitrack PFC architecture
4 of 20
Deliver power in two or more balanced TRACKs
AC DC
vOUT-DC
DA
SA
DB
SB
S1
S2
S3
S4
CB
vIN-AC
LR
Q1
Q2
Q3
Q4
C1
C2
LM
vIN
Cres1
C3
Switched
Inductor
Switched Capacitor
Rectifier
Multi-winding
Transformer
CIN
COUT
vX
vY
vBUS
Isolation Stage PFC Stage
LM
Lres1
Cres2 Lres2
Rectifier
Advantages of the Multitrack PFC
5 of 20
vOUT-DC
DA
SA
DB
SB
S1
S2
S3
S4
CB
vIN-AC
LR
Q1
Q2
Q3
Q4
C1
C2
W1
W2
vIN
Z1
Z2
C3
W3
Switched
Inductor
Switched Capacitor
Rectifier
Magnetics Isolation
CIN
COUT
vX
vY
vBUS
Reduced inductor size (Multilevel)Reduced device rating
ZVS of switched-cap
ZVS for universal line
Reduced dv/dt
High Performance DCX
Reduced interleaved
winding capacitance
Smaller inductor size and ZVS
6 of 20
DB
SB
DA
SA
CB
Vgrid
D
S
CBVgrid
210 V
420 V 420 VBoost PFC Multitrack PFC
DB
SB
SADB
SB
DA
DB
DA
SA
|Vgrid|<105V 105V<|Vgrid|<210V 210V<|Vgrid|<420V
420V210V 420V
210V
Low Line Mid Line High Line
Hard switching at high line Full range ZVS
Three operation modes
Control function blocks of the Multitrack PFC
7 of 20
110V
220V
330V
1 3
440V
265VAC
85VAC
vTH
2 4 5 1 32 4 5 4 3 21
vIN
vIN
1 3
220VAC
2 21
vIN
4 3
vOUT-DC
DA
SA
DB
SB
S1
S2
S3
S4
CB
vIN-AC
LR
Q1
Q2
Q3
Q4
C1
C2
W1
W2
vIN
Z1
Z2
C3
W3
Switched
Inductor
Switched Capacitor
Rectifier
Magnetics Isolation
CIN
COUT
vX
vY
vBUS
• Voltage Regulation
• Current Modulation
• ZVS Timing
• Mode Selection
DCX ControllerMultitrack PFC Controller
ZVS valley-detection circuits at MHz
8 of 20
+- +
-
vds
vL
Rd
Cd
Vref
iLvd
Iref
NOR
vgs
Sd
monitor inductor current
(no current sensor)
monitor drain
voltage
• QSW-ZVS at 1-4 MHz
• Implemented as logic gatesDB
SB
DA
SA
CB
Vgrid
ZVS Controller 1
ZVS Controller 2
[S. Lim, J. Ranson, D. M. Otten and D. J. Perreault, “Two-Stage Power Conversion Architecture
Suitable for Wide Range Input Voltage,” IEEE Transactions on Power Electronics, 2015.]
Complete Multitrack PFC controller
9 of 20
Mode
Selection &
Current
modulation
Voltage
Regulation
ZVS #1
ZVS #2 vIN
vY
vX
VGY
VGX
vY
vIN
vX
VGRID
+
-
+
-
+
-
+
-
-
+
-
+
Mode
Selection
ctrlX
disXdisY
disX
ctrlX
ctrlY
disY
onY
ctrlY
onY
DAC
ADC
VREF VBUS/VOUT
ADC
vBUS1
vIN
vBUS1
DAC DAC
VthX VthY
ZVS Loop 1
VBUS regulation
SA
SBDA
DB
LR
ZVS Loop 2
ILR modulation
Multitrack PFC DCX
ZVS Controller #1
ZVS Controller #2
Voltage/Current
DCX Control
TI C2000
MCU
Logic gates
Startup and pre-charge of the Multitrack PFC
10 of 20
vOUT-DC
DA
SA
DB
SB
S1
S2
S3
S4
CB
vIN-AC
LR
Q1
Q2
Q3
Q4
C1
C2
W1
W2
vIN
Z1
Z2
C3
W3
Switched
Inductor
Switched Capacitor
Rectifier
Magnetics Isolation
CIN
COUT
vX
vY
vBUS
Startup Strategy:
• Step 1: Inrush to 210V - keep SC operating, SA off, SB on
until bus voltage reach 210V (50% of 420V).
• Step 2: Boost to 330V - force SA on for a period (e.g., 100ns,
10% duty ratio), keep SB off until bus voltage reach 315V.
• Step 3: PI + Non-ZVS - start PI regulation, non-ZVS.
• Step 4: PI + ZVS - continue PI regulation, maintain ZVS.
85VAC-265VAC
420VDC
210VDC
12VDC
8:1
210V
420V
330V
410V
Time (s)
VBUS
S1 S2 S3 S4
Design of the Multitrack DC transformer
11 of 20
C1
C2
SA
SB
Q3
Q1
Q4
Q2
Cout
Cres1
Lres1
SC
SDCres2
Lres2C3
Rload
2:1 switched cap converter
2-input 1-output LLC converter785 nH
776 nH
0.7 uH
1.9 nH
8:1
8:1
172 pF
63 pF
7 nF
7 nF171 pF
11 uH
11 uH
Extracted magnetics model
Low-Q LLC operation with ZVS
M. Chen, M. Araghchini, K. K. Afridi, J. H. Lang, C. R. Sullivan, and D. J. Perreault, “A Systematic Approach to
Modeling Impedances and Current Distribution in Planar Magnetics,” IEEE Transactions on Power Electronics, 2016.
Ultra-thin prototype
12 of 20
vOUT-DC
DA
SA
DB
SB
S1
S2
S3
S4
CB
vIN-AC
LR
Q1
Q2
Q3
Q4
C1
C2
W1
W2
vIN
Z1
Z2
C3
W3
Switched
Inductor
Switched Capacitor
Rectifier
Magnetics Isolation
CIN
COUT
vX
vY
vBUS
3.5 inch
2.15 inch
0.4 inch
Volume: 3 inch3
Power: 150W
Efficiency target: 92%
Peak loss: 15W
Electrolytic cap
sets the height limit
Steady-state grid interface waveforms
13 of 20
DB
SB
DA
SA
CB
Vgrid
Low Line: 110 VAC, 50 W Mid Line: 220 VAC, 100 W High Line: 250 VAC, 120 W
Multitrack PFCVSW
VSW210V
420V
Soft-switching operation
14 of 20
QSW-ZVS of the Multitrack PFC LLC-ZVS of the Swtched Cap An unique Multitrack ZVS mechanism
VY
VX
iR
Capacitive
divider ZVS
Startup waveforms
15 of 20
Inrush current Boost PI control operation with ZVSAbout 500ms
Startup Strategy:
• Step 1: Inrush to 210V - keep SC operating, SA off, SB on until bus voltage reach 210V.
• Step 2: Boost to 330V - force SA on for a period (e.g., 100ns, 10% duty ratio), keep SB off.
• Step 3: PI + Non-ZVS - start PI regulation, non-ZVS.
• Step 4: PI + ZVS - continue PI regulation, maintain ZVS.
Measured efficiency
16 of 20
• High line efficiency: 92.0%
• Low line efficiency: 90.5%
• Light load: switched-cap loss
• Heavy load: rectifier loss
Summary
• A Multitrack PFC architecture for
single-phase grid-interface.
• Density 50W/inch3.
• 92.0% efficiency with 220V input.
• 90.5% efficiency with 110V input.
• Reduced inductor size.
• Reduced dv/dt on transformer.
• ZVS for MHz grid-interface.
• ZVS on switched capacitor.
• 1MHz-4MHz operation, potential
to operate at higher frequencies.
• A new design concept of
creating mutual advantages.
17 of 20
Power Density (W/inch3)
End-to-end Efficiency (%)
10 20 30 40 50 60
91
92
93
94
95
96
TI 310W 24V
PMP9640
demo board*
This work
150W 12V
MIT 250W 24V
APEC18
MIT 50W 12V
non-universal
Towards high density universal-input low
voltage single-phase Isolated PFCs97
Toronto 400W
200kHz TPEL15*
On-Semi 60W
12V, APEC17*
CoPEC 600W 24V
electrolytic-free
APEC16
CPES 65W
20V APEC16
Stanford 250W
450kHz TPEL18*
*estimated
density
Thermal imaging of the Multitrack PFC
18 of 20
110Vin, ~50W
220Vin, ~50W
110Vin, ~100W
220Vin, ~100W
• System works
in low line
• Switched cap
circuit has high
stress
• System works
in low line
• Rectifier loss
dominating
• System works
in high line
• Switched cap
circuit has
lower stress
• System works
in high line
• Rectifier loss
dominating
• Primary side
is very
efficient
~200LPF forced air flow from left to right
Place your logo here
Multitrack PFC Architecture
Minjie Chen
Sombuddha Chakraborty
David Perreault
Princeton University
Texas Instruments
Massachusetts Institute of Technology
1713978-1-5386-1180-7/18/$31.00 ©2018 IEEE
Thanks + Q&A
Benchmark references
• [TI Demo Board] TI PMP9640 PFC Demo Board: http://www.ti.com/tool/PMP9640
• [MIT Thesis] S. Lim, “High Frequency Power Conversion Architecture for Grid Interface”, Ph.D. Thesis,
MIT, 2016.
• [CPES APEC16] Y. C. Li, F. C. Lee, Q. Li, X. Huang and Z. Liu, “A novel AC-to-DC adaptor with ultra-
high power density and efficiency,” IEEE Applied Power Electronics Conference and Exposition (APEC),
2016.
• [On-Semi APEC17] S. Moon, B. Chung, G. Koo, J. Guo and L. Balogh, “A conduction band control AC-
DC Buck converter for a high efficiency and high power density adapter,” IEEE Applied Power
Electronics Conference and Exposition (APEC), 2017.
• [MIT APEC18] Juan Santiago-Gonzalez, David Otten, Seungbum Lim, Khurram Afridi, and David
Perreault, “Single Phase Universal Input PFC Converter Operating at HF”, IEEE Applied Power
Electronics Conference and Exposition (APEC), 2018.
• [CoPEC ECCE17] S. Pervaiz, A. Kumar and K. K. Afridi, "GaN-based high-power-density electrolytic-
free universal input LED driver," IEEE Energy Conversion Congress and Exposition (ECCE), 2017.
• [Toronto TPEL15] B. Mahdavikhah and A. Prodić, "Low-Volume PFC Rectifier Based on Nonsymmetric
Multilevel Boost Converter," IEEE Transactions on Power Electronics, 2015.
• [Stanford TPEL18] L. Gu, W. Liang, M. Praglin, S. Chakraborty and J. M. Rivas Davila, "A Wide-Input-
Range High-Efficiency Step-down Power Factor Correction Converter Using Variable Frequency
Multiplier Technique," IEEE Transactions on Power Electronics, 2018.20 of 20
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