Low dropout regulator(ldo)

ECE5590 ANLow Dropout Regulator(LDO)

-Aadit Modi(ID#16037399) -Altaf Hirani (ID#12197304)

LDO

• Linear Voltage DC regulators.• Regulation maintained with small differences.• Output current in range of 50-100mA.• Pass transistor, error amplifier and voltage

reference.• Low quiescent current.

•Design a low dropout voltage regulator to provide an output voltage of 3.3V.

Goals:

For the calculations we assume the following constants:

• - Pass transistor current = 1mA

• - Vout = 3.3V

• - Dropout voltage

• - VDD=5V

Block Diagram• Pass transistor & error amplifier.

CALCULATIONS:

Efficiency calculation

Iq (quiescent current) = 112 uAIo (output current) = 1.39 mAVo (output voltage) = 3.37 VVi (input voltage) = 5 V

Eff. = Io*Vo/(Io + Iq)*Vi x 100

Using the above equation yields and efficiency of about 61.1%.

- Summary of calculated transistor sizes vs the transistor simulation sizes

TransistTor Calculated Size Actual Size Used

Width(µm) Length(µm) Width(µm) Length(µm)

M1 100 0.6 100.05 0.6

M2 100 0.6 100.05 0.6

M3 50 0.6 49.95 0.6

M4 50 0.6 49.95 0.6

M5 20 0.6 19.95 0.6

M6 250 0.6 250 0.6

TRANSISTOR SIZE TABLE

Final Schematic

Typical LDO Circuit

Calculations:- Calculation of a range of Vbias1

1. To find Ibias1:

From the desired a photodiode range, the minimum value of Ibias1:

VGS3

=Vphmin

Ibias1 = ½ K1(W/L)3(V

GS3-V

THN)2 = ½ * 50 * 10-6 A/V2 *

3µm/0.6µm * (0.8V – 0.617)2 = 4.186µA =4µA

The maximum value of Ibias1:

Ibias1 = ½ K1(W/L)3(V

GS3-V

THN)2 = ½ * 50 * 10-6 A/V2 *

3µm/0.6µm * (3.0V – 0.617)2 = 0.7mA

Calculations:- Calculation of sizes of the transistors M5, M4

1. To determine W5

From requirement to keep M5 in saturation region:

VTH

≤VGS5

= Vbias1(min) + VTHp

– Vph

(max) =

2.8V +0.9V – 3.0V = 0.7V

W5 = (2InL5)/(K

1(V

GS5-V

THN)2) = (2 * 1.2µA *

0.6µm)/(50µA/V2* (0.7V – 0.617V)2) = 4µm

Calculations:- Calculation of sizes of the transistors M5, M4

2. To determine W4

VDS4

≥VGS4

– VTHN

VDS4

= Vph

(min) = 0.8V

Assumed VGS4

= 0.75V

W4 = (2InL4)/(K

1(V

GS4-V

THN)2) = (2 * 1.2µA *

0.6µm)/(50µA/V2* (0.75V – 0.617V)2) = 1.60µm

Calculations:

- Calculation of the gain for the current mirror transistors M1, M2, M7

1. To find VGS

for M1, M2, M7

VGS1

= VDS1

= VGS2

= VGS1

= √[(2Iout)/(K2(W/L)

2,7] + V

THp = √(2 *

1.2µA)/(25µA/V2* (20/2.4)) + 0.915V = 0.107V + 0.915V = 1V

Calculations:- Calculation of the gain for the current mirror transistors M1, M2, M7

2. To find VDS

for current mirror:

Next we find VDS2

and VDS7

(which are the same in value)

VDS2,7

= VDD

– VDS6

= VDD

- √[(2Iout)/(K1(W/L)

6] - V

THN =

5V - √(2 * 1.2µA)/(50µA/V2* (1.5/8.55)) - 0.617V = 3.85V

Calculations:- Calculation of the gain for the current mirror transistors M1, M2, M7

3. To determine W1:

Finally, we calculate the size of transistor M1. It's required that Iin = Iout.

Consequently, the current conveyor ought to have I1 = I2,7.

Assuming L1= L2,7:

W1/L1* (1 + ƛpDS2,7) = W2,7/L2,7(1 + ƛpDS2,7)

W1 = 2(1 + ƛpDS2,7)/(1 + ƛpDS1)

W1 = (20µm*(1+0.2*3.85V)/(1+0.2*1V) = 29.5µm

Layout

PRE-LAYOUT DC INPUT TEST

Post-layout Line Regulation (Changing input voltage)

Post-layout Line Regulation (Changing input voltage)

THANK YOU.