Lecture05: CascodeConfiguration - UMBC | ECLIPSE Cluster · 2016. 3. 21. · Lecture05:...

Lecture 05: Cascode ConfigurationAnalog IC Design

Dr. Ryan Robucci

Department of Computer Science and Electrical Engineering, UMBC

Spring 2015

Dr. Ryan Robucci Lecture V 1 / 19

Lowered Resistance Looking into Source

Placing a FET in series such that we are examining the resistancelooking into the source tends to lower the effective resistance.

Reff =RD + rds1+gs rds

Dr. Ryan Robucci Lecture V 2 / 19

Current Buffer and Shielding

Looking into source,FET behaves as acurrent buffer

reducing inputvoltage variationw/current (lowinput resistance)shielding input fromvariations of voltageon outputproviding highoutput resistance onthe output drainside

Dr. Ryan Robucci Lecture V 3 / 19

Cascode Configuration (looking into drain)

Placing a FET in series such that we are looking into the draintends to have a higher resistance. The current changes less whenthe voltage changes.Reff = gs rdsRS + rds +RS henceforth to be known as the cascodeequation

Dr. Ryan Robucci Lecture V 4 / 19

Cascoded C.S. Amplifier

M1 M2

M1

M2

M1

Dr. Ryan Robucci Lecture V 5 / 19

Cascoded C.S. Amplifier

Common Source Amplifier:Gm =−gmRout = RD ||rdsIncreasing RD increases Av ,Rout < rds

Cascoded C.S. Amplifier:Assume sat. for both FETsUse Cascode EquationRout = RD ||gs2rds2rds1+ ro2+ ro1Under common assumptions (beable to state them)Rout ≈ RD ||gs2rds2rds1Now Rout can be much larger as RDis increased (But rememberRoutCout increases, possiblyreducing BW)

Dr. Ryan Robucci Lecture V 6 / 19

Cascode Effect on Gm

M2

M1

A

0V0V

A A

0V0V A

0V0V

Use current division equation:A

0V0V

current split

iy =−vigm1 ·(

rds1rds1+

1gs2||rds2

)Gm =

iyvi=−gm1 ·

(rds1

rds1+1

gs2||rds2

)if 1

gs2� rds1,

Gm ≈−gm1

Dr. Ryan Robucci Lecture V 7 / 19

Cascode: Effective High-rds FET

M2

M1 M1

FET

High-rdsLarge VDS ,SAT

Approximately same gmMay allow higher DC gain due to larger output resistance,perhaps with associated cost of BW

Dr. Ryan Robucci Lecture V 8 / 19

Effect on output range and how to set Vcas

M2

M1

M2 sat condition: Vout >= Vcas −VTH2 = Vout,min

When Vout < Vcas −VTH2, rds2and gs2 reduce, causing thegain to reduce. This causes a distortion.

M1 sat condition: Vx > Vin,bias −VTH1 , Vx > Vov1

(Vin,bias is designed though Ibias ,(W

L

)1)

Dr. Ryan Robucci Lecture V 9 / 19

Effect on output range and how to set Vcas

Vcas is a design variable. To design we must examine Vx :node Vx is typically a low resistance node and does not changein voltage much as the current of M1 is changed

Vcas must support the bias current through M2 requiring somepotential above the source:

Vcas −Vx −VTH2 = VOV2Vcas = Vov2+VTH2 (threshold plus overdrive)Thus Vcas −Vx > Vov1+Vov2+VTH2

As Vcas is set, Vx tends to follow it according to the sourcefollower behavior:

M2

M1

Dr. Ryan Robucci Lecture V 10 / 19

Effect on output range and how to set Vcas

If Vcas is set too low, Vx is pushed below Vov1 and M1 leavessat

(Design tip: if you run DC sim and find that M1 is not sat,increase Vcas)

If Vcas is set too high, it needlessly limit Vout (sets Vout,min)and jeopardizes M2 satOutput Limitation:

Vout > Vout,min = Vcas −VTH2BEST CASE:

Vcas = Vov1+Vov2+VTH2Vout,min = Vov1+Vov2

Common mistake: assume Vout,min = Vov1+Vov2 withoutconsidering actual value of Vcas

(I tend to ask a related question on exams)

Dr. Ryan Robucci Lecture V 11 / 19

Example Circuit:

M1M2

M1

M3M3

Study effect of M2 on Av in two parts:M2 effect on ROUT ?

Non-cascoded: Rout = rds3||rds1 maybe rds2

Cascoded: Rout = rds3||rds1gs2rds2+ rds1+ rds2 maybe rdsSo effect on ROUT is not large

Dr. Ryan Robucci Lecture V 12 / 19

Example Circuit:

Effect on GM:

Non-cascoded: Gm = gm

Cascoded: Gm =−gm1gs2+

1rds2

gs2+1

rds2+ 1

rds1

?≈−gm1

So effect on is very small

So, “one-sided” cascode does not have a large effect overall

Dr. Ryan Robucci Lecture V 13 / 19

Fully-Cascoded Amplifier

M1M2

M1

M3M4

M4

Rout = (rds3gs3rds4+ rds3+ rds4) ||(rds1gs2rds2+ rds1+ rds2)

Rout?≈ (rds3gs3rds4) ||(rds1gs2rds2)

Rout?≈ 1

2gs r2ds

Gm =−gm1gs2+

1rds2

gs2+1

rds2+ 1

rds1

?≈−gm1

Dr. Ryan Robucci Lecture V 14 / 19

Fully Cascoded Amplifier

M1M2

M1

M3M4

M4

Non-cascoded: AV = gm 12 rd

Cascoded: AV ,cas = gm 12gs r2

dsAv ,casAV

= gs rds(gain multiplied by intrinsic gain)(sometimes thought of as two gain stages)

Dr. Ryan Robucci Lecture V 15 / 19

Output Range

Vcasn−VTH2 = Vout,min < Vout < Vout,max = Vcasp+ |VTH3|Best case allows output to reach within two overdrive voltagesof supply rails:

If this condition on Vcasn AND Vcasp is TRUE:

Vcasn = VTH1+Vov1+VTH2+Vov2 andVcasp = VDD −|VTH4|−Vov4−|VTH3|−Vov3

Then:

Best case is achieved:Vov1+Vov2 < Vout < Vdd −Vov2−Vov3

I define PFET overdrive voltages as Vs −Vg −∣∣VTHp

∣∣ to keepthe values typically positive

Dr. Ryan Robucci Lecture V 16 / 19

DC Transfer Curve

Dr. Ryan Robucci Lecture V 17 / 19

Overall Points for Fully Cascoded Amplifier

Output range:

about a loss of two overdrive voltages (one toward each supplyrail) as compared to non-cascoded version

Gain:

multiplied by intrinsic gain

Rout:

multiplied by intrinsic gain

BW:

due to increased Rout, possible loss of BW, divided by intrinsicgain

Dr. Ryan Robucci Lecture V 18 / 19

Circuit Debugging notes/tips:

M1 not sat:Try increase Vcasn to raise VD1 ordecreasing Vov1 or Vov2

M4 not sat:Try decrease Vcasp to lower VD4 ordecrease Vov3 or Vov4

M2 not sat:try decease Vcasn ordecrease Vov2 ordecrease Vcasn and Vov1

M3 not sat:try decease Vcasp ordecrease Vov3 orincrease Vcasp and decrease Vov4

How to affect a given VOV ? Consider WL and Ibias

Note decreasing Vov1 means lower input voltage bias pointDr. Ryan Robucci Lecture V 19 / 19