LECT03 Digital Design

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 3-1Electrical & Computer Engineering

Digital Systems Design

Review of VHDL for Sequential Circuits

Overview

• Basic storage elements– Structural design using library components

– Behavioral design: D latches and D flip-flops• Options including

– Synchronous and asynchronous reset

– Multiplexed inputs

– Enable inputs

• Counters

• Shift Registers

• Arbitrary finite state machines (FSM)– Mealy and Moore model designs

Structural VHDL Using a D flip-flop package

LIBRARY ieee ;USE ieee.std_logic_1164.all ;LIBRARY altera ; USE altera.maxplus2.all ;

ENTITY flipflop IS PORT ( D, Clock : IN STD_LOGIC ;

Reset_n, Preset_n : IN STD_LOGIC ; Q : OUT STD_LOGIC ) ;

END flipflop ;

ARCHITECTURE Structure OF flipflop IS BEGIN

dff_instance: dff PORT MAP ( D, Clock, Reset_n, Preset_n, Q ) ; END Structure ;

Resetn and Presetn: Active low signals

The dff component is only oneof several built-in componentsfor storage elements.

Code for a gated D latch

LIBRARY ieee ; USE ieee.std_logic_1164.all ;

ENTITY latch IS PORT ( D, Clk : IN STD_LOGIC ;

Q : OUT STD_LOGIC) ; END latch ;

ARCHITECTURE Behavior OF latch IS BEGIN

PROCESS ( D, Clk ) BEGIN

IF Clk = '1' THEN Q <= D ;

END IF ; END PROCESS ;

END Behavior ;

USES IMPLIED MEMORY

If no assignment is made,the last assignment isremembered.

Code for a D flip-flop

Q : OUT STD_LOGIC) ; END flipflop ;

ARCHITECTURE Behavior OF flipflop IS BEGIN

PROCESS ( Clock ) BEGIN

IF Clock'EVENT AND Clock = '1' THEN Q <= D ;

END Behavior ; POSITIVE EDGE TRIGGERED

Code for a D flip-flop (alternate)

PROCESS ( Clock ) BEGIN

IF RISING_EDGE(Clock) THEN Q <= D ;

END Behavior ; POSITIVE EDGE TRIGGERED. USEFALLING_EDGE FOR NEGATIVE EDGE

Code for a D flip-flop (alternate)

LIBRARY ieee; USE ieee.std_logic_1164.all;

Q : OUT STD_LOGIC ) ; END flipflop ;

PROCESSBEGIN

WAIT UNTIL Clock'EVENT AND Clock = '1' ;Q <= D ;

END PROCESS ; END Behavior ;

POSITIVE EDGE TRIGGERED

D flip-flop with synchronous reset

ENTITY flipflop IS PORT ( D, Reset_n, Clock : IN STD_LOGIC ;

PROCESSBEGIN

WAIT UNTIL Clock'EVENT AND Clock = '1' ;IF Reset_n = '0' THEN

Q <= '0' ; ELSE

Q <= D ; END IF ;

END PROCESS ;END Behavior ;

D flip-flop with MUX input

LIBRARY ieee ;USE ieee.std_logic_1164.all ;

ENTITY muxdff ISPORT ( D0, D1, Sel, Clock : IN STD_LOGIC ;

Q : OUT STD_LOGIC ) ;END muxdff ;

ARCHITECTURE Behavior OF muxdff ISBEGIN

PROCESSBEGIN

WAIT UNTIL Clock'EVENT AND Clock = '1' ;IF Sel = '0' THEN

Q <= D0 ;ELSE

Q <= D1 ;END IF ;

D flip-flop with enable input

ENTITY flipflop ISPORT ( enable, d, clk : IN STD_LOGIC ;

q : OUT STD_LOGIC ) ;END flipflop ;

ARCHITECTURE Behavior OF flipflop ISBEGIN

PROCESS(clk)BEGIN

IF enable=‘0’ THEN null;ELSIF RISING_EDGE(clk) THEN

q <= d;END IF;

This will be our preferred method for creating a D flip-flop or a multibit register with enable.

D flip-flop with asynchronous reset

ENTITY flipflop ISPORT ( reset_n, d, clk : IN STD_LOGIC ;

q : OUT STD_LOGIC ) ;END flipflop ;ARCHITECTURE Behavior OF flipflop ISBEGIN

PROCESS(clk,reset_n)BEGIN

IF reset_n =‘0’ THENq<= ‘0’;

ELSIF RISING_EDGE(clk) THENq <= d;

END IF;END PROCESS ;

END Behavior ;

This will be our preferred method for creating a D flip-flop or a multibit register with reset.

Counter Modeling with VHDL

• Counters are simple examples of sequential circuits

• Counters can be modeled as arbitrary FSMs, but this is not the most straightforward method of modeling these circuits

• Counters can be easily modeled using basic arithmetic expressions

• Options include:– Arithmetic operations on STD_LOGIC_VECTOR signals

– Use of the INTEGER data type

Up Counter Using STD_LOGIC_VECTOR

LIBRARY ieee;

USE ieee.std_logic_1164.all;

-- use std_logic_arith and std_logic_unsigned to support

-- unsigned arithmetic operations on STD_LOGIC_VECTOR data types

USE ieee.std_logic_arith.all;

USE ieee.std_logic_unsigned.all;

ENTITY count_std_logic IS

PORT( clock : IN STD_LOGIC;

sload : IN STD_LOGIC;

data : IN STD_LOGIC_VECTOR(4 DOWNTO 0);

result : OUT STD_LOGIC_VECTOR(4 DOWNTO 0));

END count_std_logic;

Up Counter Using STD_LOGIC_VECTOR

ARCHITECTURE rtl OF count_std_logic IS

SIGNAL result_reg : STD_LOGIC_VECTOR(4 DOWNTO 0);

PROCESS (clock)

IF (clock'EVENT AND clock = '1') THEN

IF (sload = '1') THEN

result_reg <= data;

result_reg <= result_reg + "00001";

END IF;

END PROCESS;

result <= result_reg;

END rtl;

Up Counter Using INTEGER

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY count IS

PORT( clock : IN STD_LOGIC;

sload : IN STD_LOGIC;

-- INTEGER data types are a default size of 32 bits

-- use a RANGE specifier to limit the number of bits

-- generated for the register (5 bits in this case)

data : IN INTEGER RANGE 0 TO 31;

result : OUT INTEGER RANGE 0 TO 31;

END count;

Up Counter Using INTEGER

ARCHITECTURE rtl OF count IS

SIGNAL result_reg : INTEGER RANGE 0 TO 31;

PROCESS (clock)

IF (clock'EVENT AND clock = '1') THEN

IF (sload = '1') THEN

result_reg <= data;

result_reg <= result_reg + 1;

END IF;

END PROCESS;

result <= result_reg;

END rtl;

VHDL Shift Register Design

-- VHDL code for an 8-bit shift-left register with a positive-edge clock

-- asynchronous clear, serial in, and serial out.

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY shift IS

PORT( -- clk is the clock for the shift operation

-- si is a 1-bit serial input into the LSB of the shift register

-- clr is an asynchronous active high clear control signal

clk, si, clr : IN STD_LOGIC;

-- so is a 1-bit serial output from the MSB of the shift register

so : OUT STD_LOGIC);

END shift;

VHDL Shift Register Design

ARCHITECTURE Behavior OF shift IS

SIGNAL s_reg: STD_LOGIC_VECTOR(7 DOWNTO 0);

PROCESS(clk,clr)

IF(clr='1') THEN

s_reg <= "00000000";

elsif RISING_EDGE(CLK) THEN

s_reg <= s_reg (6 DOWNTO 0) & si;

END IF;

END PROCESS;

so <= s_reg(7);

END Behavior;

Arbitrary FSM design using CAD tools

• VHDL provides a number of constructs for designing finite state machines

• There is not a standard way for defining an FSM• Basic approach

– Create a user-defined data type to represent the possible states of an FSM

– This signal represents the outputs (state variables) of the flip-flops that implement the states in the FSM

– VHDL compiler chooses the appropriate number of flip-flops during the synthesis process

– The state assignment can be done by the compiler or can be user specified

User defined data types

• The TYPE keyword will be used to define a new data type used to represent states in the FSM

TYPE fsm_state IS (A, B, C);

A user-defineddata type definition

Data typename

Valid values forthe data type

Defines a data type (called fsm_state) that cantake on three distinct values: A, B, or C).

Representing states

• A SIGNAL is defined, of the user-defined fsm_state, to represent the flip-flop outputs

TYPE fsm_state IS (A, B, C);

SIGNAL y: fsm_state;

The signal, y, can be used to represent theflip-flop outputs for an FSM that has three states

Design example

• Create a VHDL description for a circuit that detects a ’11’ input sequence on an input, w

A/z=0w=0

B/z=0w=1

w=1w=0w=0

Recall the Moore statediagram for the circuit

VHDL design example

LIBRARY ieee ;

USE ieee.std_logic_1164.all ;

ENTITY detect IS

PORT( clk, reset_n, w : IN STD_LOGIC ;

z : OUT STD_LOGIC) ;

END detect ;

ARCHITECTURE Behavior OF detect IS

TYPE fsm_state IS (A,B,C) ;

SIGNAL y: fsm_state ;

VHDL design example continued

PROCESS ( reset_n, clk )BEGINIF reset_n = ‘0’ THEN

y <= A;ELSIF RISING_EDGE(clk) THEN

CASE y ISWHEN A =>

IF w=‘0’ THENy <= A;

ELSEy <= B;

END IF;WHEN B =>

IF w=‘0’ THENy <= A;

y <= C;

END IF;

WHEN C =>

IF w=‘0’ THEN

y <= A;

y <= C;

END IF;

END CASE;

END IF;

END PROCESS;

z <= ‘1’ WHEN y=C ELSE ‘0’;

END Behavior;

Alternative style of VHDL code

• Another form for describing the circuit in VHDL is to define two signals to represent the state of the FSM– One signal, y_present, defines the present state of the FSM

– The second, y_next, defines the next state of the machine

• This notation uses y (present state) and Y (next state) for state information

• Two PROCESS statements will be used to describe the machine– The first describes the STATE TABLE as a combinational circuit

– The second describes the flip-flops, stating that y_present should take on the value of y_next after each positive clock edge

Alternate VHDL description

ARCHITECTURE Behavior OF detect ISTYPE fsm_state IS (A,B,C);SIGNAL y_present, y_next: fsm_state;

BEGINPROCESS(w,y_present)BEGIN

CASE y_present ISWHEN A =>

IF w=‘0’ THENy_next <= A;

ELSEy_next <= B;

WHEN B =>IF w=‘0’ THEN

y_next <= A;ELSE

y_next <= C;

WHEN C =>IF w=‘0’ THEN

y_next <= A;ELSE

y_next <= C;END CASE;

END PROCESS;PROCESS(clk,reset_n)BEGIN

IF reset_n=‘0’ THENy_present <= A;

ELSIF RISING_EDGE(clk) THENy_present <= y_next;

END IF;END PROCESS;z <=‘1’ WHEN y_present=C ELSE ‘0’;END Behavior;

Specifying a state assignment

• With the previous designs, state assignment is done by the VHDL compiler

• State assignments can be user specified using the following constructs

ARCHITECTURE Behavior OF simple ISTYPE fsm_state IS (A, B, C) ;ATTRIBUTE ENUM_ENCODING : STRING ;ATTRIBUTE ENUM_ENCODING OF fsm_state : TYPE IS "00 01 11" ;SIGNAL y_present, y_next : fsm_state;

ARCHITECTURE Behavior OF simple ISSIGNAL y_present, y_next : STD_LOGIC_VECTOR(1 DOWNTO 0);CONSTANT A : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00" ;CONSTANT B : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01" ;CONSTANT C : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11" ;

VHDL code of a Mealy FSM

• A Mealy FSM can be described in a similar manner as a Moore FSM

• The state transitions are described in the same way as the original VHDL example

• The major difference in the case of a Mealy FSM is the way in which the code for the output is written

• Recall the Mealy state diagram for the ’11’ sequence detector

1/10/0

Mealy ’11’ detector VHDL code

ARCHITECTURE Behavior OF detect ISTYPE fsm_state IS (A,B) ;SIGNAL y: fsm_state;

BEGINPROCESS(reset_n,clk)BEGIN

IF reset_n=‘0’ THENy <= A;

ELSEIF RISING_EDGE(clk) THENCASE y IS

WHEN A =>IF w=‘0’ THEN y<= A;ELSE y<= B;END IF;

WHEN B =>IF w=‘0’ THEN y<= A;ELSE y<= B;END IF;

END CASE;END IF;

END PROCESS;PROCESS(y,w)BEGIN

CASE y ISWHEN A =>

z <=‘0’;WHEN B =>

z <= w;END CASE;

END PROCESS;END Behavior;

LECT03 Digital Design

Documents

Design principles for essentially digital governanceeprints.lse.ac.uk/64125/1/Essentially Digital Governance.pdf · Design principles for essentially digital governance ... Design

Digital Filter Design/Digital Filter Design Lite - Invalid Request

ENG2410 Digital Design “Introduction to Digital Systems”islab.soe.uoguelph.ca/sareibi/TEACHING_dr/ENG241_html_dr/outline... · Digital Design “Introduction to Digital Systems

Lecture 03: Stress - Worcester Polytechnic Instituteusers.wpi.edu/~cfurlong/es2502/lect03/Lect03.pdf · force and moment at the section ... specific plane passing through a point

TKTTKT--1426 Digital design for 1426 Digital design for … · TKTTKT--1426 Digital design for 1426 Digital design for FPGA, 6cp ... • Design fundamentals: ... (VHDL) 6 31.8.2011

Lect03 handout

NVC Bio105 Lect03 Bio Molecules Fa16 - Napa …...molecules?

Lect03 Qual Metrics

2012 Lect03 UIGuideline Student

Digital Design - Wild Dog Design

Digital Logic and Design 01 - sanlp.org Logic and Design 01.pdf · Digital Logic and Design (ELE-241) ... Digital Logic and Design yText book Digital Design 2nd Ed., ... 9Digital

Lect03 System Calls

Bert Hagendoorn (Dutch Digital Design) @ CMC Digital Design

Summer12 Lectures Lect03

Today’s Topics Digital Logic Design Digital Logic Design Boolean Logic Boolean Logic Digital Logic Circuits Digital Logic Circuits

Digital Design to Digital Production

Introduction to CMOS VLSI Design (E158) Harris Lecture 3: Transistors and Gatespages.hmc.edu/harris/class/e158/01/lect03.pdf · 2014-08-12 · MAH E158 Lecture 3 1 David Harris Harvey

COMMUNICATION DESIGN (DIGITAL DESIGN) · COMMUNICATION DESIGN (DIGITAL DESIGN) Vector Techniques 201 Typography 202 Motion Design for Designers 203 Design for Digital Media 204 Experimental

Digital design

Digital Design Concepts - Kettering Universitygtewolde/ce310/Lectures/...Digital Design Concepts Ł Digital Hardware Components Ł The Design Process Digital Hardware Components Ł