Introduction to Computer Engineering ECE...

Introduction to Computer Engineering

ECE 203

Northwestern University

Department of Electrical Engineering and Computer Science

Teacher: Robert DickOffice: L477 TechEmail: dickrp@ece.northwestern.eduPhone: 467–2298Webpage: http://www.ece.northwestern.edu/˜dickrp/ece203Teaching Assistants Zhenyu Gu (L470)

Debasish Das (M314)

Homework index

1 How to get lab supplies . . . . . . . . . . . . . 18

2 Mailing list . . . . . . . . . . . . . . . . . . . 19

3 Reading assignment (for next class) . . . . . . 67

4 Reading assignment . . . . . . . . . . . . . . 155

10Homework assignment two . . . . . . . . . . . 412

11Reading assignment . . . . . . . . . . . . . . 478

13Homework three . . . . . . . . . . . . . . . . 562

16Assigned reading . . . . . . . . . . . . . . . . 635

Topics covered

• Analog vs. digital signals, thresholds

• Switch model

• NMOS and PMOS transistors as switches, reason for

NMOS/PMOS difference

• Basic logic gates and transmission gates from CMOS

• More complex devices from basic gates and transmission gates

Topics covered

• Truth tables

• Basic facts about TTL use (lab kits)

• Boolean algebra, De Morgan’s Laws = bubble pushing

• Two-level logic forms

• Karnaugh maps

• Quine-McCluskey algorithm

Topics covered

• Encoders, decoders, MUXs, DMUXs

• Safe implementation with TGs

• Number bases: decimal, binary, hex, etc.

• High-level understanding of ASCII and Unicode

• Signed and unsigned numbers, different signed representations,

Gray code

• Arithmetic units in digital logic, carry select, main idea of carry

lookahead

Assigned reading

• M. M. Mano and C. R. Kime, Logic and Computer Design

Fundamentals. Prentice-Hall, Englewood Cliffs, NJ, third ed.,

– Sections 1.1–1.7

Assigned reading

• CMOS handout from M. M. Mano, Digital Design. Prentice-Hall,

Englewood Cliffs, NJ, third ed., 2002

• TTL handout from D. Lancaster, TTL Cookbook. Howard W.

Sams & Co., Inc., 1974

• Quine–McCluskey from R. H. Katz, Contemporary Logic Design.

The Benjamin/Cummings Publishing Company, Inc., 1994 and

J. P. Hayes, Introduction to Digital Logic Design. Addison-Wesley,

Reading, MA, 1993

Today’s topics

• Reason for late start

• Brief course overview

• Majors

• Administrative stuff

– The fun stuff starts on Monday!

Brief course overview

• Hardware design

• Low-level programming

• Computer geek culture

What’s your major?

Computer geek already?

• Good!

• You’ll still probably see a lot of new things in this course

• Go ahead and ask questions that push beyond the basic material

• If you want to go beyond the normal labs, I’ll be happy to make

suggestions

• ECE 203 should lay the foundations for logic design and

understanding the connections between electrons and software

Not a computer geek yet? Good!

• You’re going to be working with computers in almost any field

• Understanding how they work at the lowest levels and knowing

how to build them will put you ahead your peers

• If you’re not a computer geek yet, sit in the front of the classroom

and ask questions!

– It’s the best way to keep the course’s pace sane

Backgrounds

• Different backgrounds

• ECE 203 can be a hard course

• However, if you work hard, I’m totally confident that you will learn

how to build useful computers

– TAs and I will help

• In the past, many Materials Science, BME, and IEMS did

absolutely amazing work

• If something in lecture doesn’t make sense, please ask

– If it doesn’t make sense to you, others have the same

question!

• Do you feel like there is a gap in your background, e.g., forgot

about resistance and capacitance?

– It’s O.K. I have handouts and office hours to help but don’t fall

behind!

• You’re paying a huge amount of money for this

• I expect a lot

• However, I’ll do whatever I can to make sure you get as much out

of this course as you put in

Core course goal

By the end of this course,

I want every one of you to be capable of

designing and building simple but useful

computer systems from integrated circuits, wires, and

assembly language instructions

In fact, it’s a requirement

Administrative stuff

• How to get lab supplies

• How to subscribe to mailing list

• Some good references

• Decide grading policies

• Plan office hours

• Course overview (if time permits)

How to get lab supplies

• Each student is required to pay $20 for lab supplies

– Integrated circuits, wires, capacitors, resistors, etc.

• Make check to Northwestern University

• Take the check to the Bursar’s office

• Take the receipt to Albert Lyerla in EG27 to pick up lab kits after

class on Monday

Mailing list

• Please subscribe to the ECE203 mailing list by sending an email

to listserv@listserv.it.northwestern.edu with no subject and a

body of “SUBSCRIBE ECE203 Firstname Lastname”.

• I encourage you to use the mailing list for discussion.

• Please don’t hesitate to use the list. If anybody thinks the traffic is

too high, I’ll set up separate “Announce” and “Discuss” lists.

• In general, if I answer somebody’s question via email, I will also

post the answer to the mailing list (without including the person’s

name).

• Do this today! The mailing list is an important and required

component of the course – used for announcements.

References

• Primary reference: M. M. Mano and C. R. Kime, Logic and

Computer Design Fundamentals. Prentice-Hall, Englewood

Cliffs, NJ, third ed., 2004

• Z. Kohavi, Switching and Finite Automata Theory. McGraw-Hill

Book Company, NY, 1978

• R. H. Katz, Contemporary Logic Design. The

Benjamin/Cummings Publishing Company, Inc., 1994

• J. Hennessy and D. Patterson, Computer Architecture: A

Quantitative Approach. Morgan Kaufmann Publishers, CA, 1995

Grading

• I’m open to reasonable options

• Class needs to agree on scheme within the first week

• Once an option is chosen, it’ll be my job to stick to it

• One possible option follows

Possible grading scheme

• 15% homeworks

• 35% labs

• 20% midterm exam

• 30% final exam

Late homework assignments

• After the class, on the due date: -5%

• After that, 10% per day penalty

• Three or more working days late: No credit

– I’ll hand out solutions

Late lab assignments

• Late lab verifications will be done at the discretion of the TAs

• In other words, although this will sometimes be possible, I’m not

going to force the TA to skip their classes, research work, or

meals to hold extra lab verification hours

• Late lab checks (without prior approval): -20%

• Three or more working days late: No credit

When to start labs

• The TAs spend a huge amount of time checking labs

• Having them do lab checks outside of the scheduled hours

makes it difficult to keep up in their own classes and research

• Start labs early to see if you have questions

• The TAs and I will be happy to help

• Will need time to finish after pointed in right direction

• Open labs

• Tech EG27

• The TAs and I may leave a note and go from our offices to EG27

during office hours to answer lab questions

• You will need to sign up for a lab time slot

Lab check times

• Labs will be assigned on Fridays

• Can lab checks be held on Wednesday and Thursday throughout

the day?

• Thursday and Friday would give you more time but might make it

more difficult for those checked on Friday to attend the help

sessions

• First lab much quicker than others

• Need to get go to get kit by Monday, though

Office hours options

1. Tuesday/Thursday throughout day

2. Monday/Thursday throughout day

3. Every day in morning

4. Every day in evening

Course overview

• Know what is computer engineering is

• Know some reasons to learn computer engineering

• Understand course goals

• Know which future courses ECE 203 can prepare you for

• Know course topics

• Start learning basic logic definitions

What is computer engineering?

• Design and implementation of computer systems

• Hardware and software design

• Related to electrical engineering and computer science with an

emphasis on digital circuits

• The best computer engineers are also good at electrical

engineers and computer science

• Knowing fundamentals helps in fields where computers are used

What is computer engineering?

• You need something solid to stand on

• Applications make more sense if you understand programming

• Programming makes more sense if you understand processors

• Processor make more sense if you understand logic design

• Logic design makes more sense if you understand circuits and

discrete math

• Circuits make more sense if you understand transistors

• Every understanding rests on others

• Computer engineering requires understanding the many levels

and the ways they fit together

Why computer engineering

• Why are you taking this class?

• What do you want to learn?

• What kind of background do you have?

– When you see something cool do you reach for a screwdriver?

– Who was electrocuted as a young child trying to figure out

how something works?

– Who has written code?

– Who has designed something complicated for the fun of it?

Why computer engineering? Fun

• Computers are almost magical

– You’ll learn how they work and how to build new ones

• You’ll learn (discrete) math, semiconductor physics, and the

theory of algorithms

• You’ll be able to use your knowledge creatively

Why computer engineering? Fun

• In the end, your creations will be tested against unforgiving

physical laws in the real world

• There are many right ways (ways that work) to design a computer

but there are also many wrong ways (ways that don’t work)

– There are measurable and clear differences between the

quality of different designs

• You’ll spend a lot of time with hard-working people who share

your interest in designing machines that make life better

Why computer engineering? Flexible

Learn hardware and software design, can move in either direction

• Embedded system design

• Computer architecture

• VLSI design

• Digital circuit design

• Software engineering

• Algorithm design

• Information technology

If you finish a Ph.D., many other doors also open

Why computer engineering? Money

• 2004 CNN survey: Most lucrative undergraduate degree

• 2005 National Association of Colleges and Employers survey

Field Average salary ($)

Computer Engineering 52,464

Electrical Engineering 51,888

Computer Science 50,820

Mechanical Engineering 50,236

Biomedical Engineering 48,503

Civil Engineering 43,679

Why computer engineering? Money

• Also compare to business administration ($37,368) and

psychology ($25,032)

• Of course, this alone is not a good reason to pick a major

• Do what you love!

– . . . but if you love computer engineering, the financial stuff

might make it easier to justify to your relatives

Future courses

• Advanced digital logic design

• Computer architecture

• Design and analysis of algorithms

• Fundamentals of computer system software

• Introduction to computer networks

Future courses

• Introduction to VLSI CAD

• Introduction to mechatronics

• Microprocessor system design

• Programming for computer engineers

• VLSI systems design

Course topics in context

• Logic gates

– Basic units of digital logic design

• Truth tables

– Simple Boolean function representation

• Boolean algebra

– Another way of representing and manipulating Boolean

functions

• Two-level logic forms

Course topics

• Logic minimization: Boolean algebra, Karnaugh maps, and

Quine-McCluskey’s method (if time permits)

– Reduce area, power consumption, or improve performance

• Hazards

• Implementation in CMOS

• Number systems: decimal, binary, octal, hex, and Gray codes

• Signed and unsigned numbers

Course topics

• Arithmetic circuits, decoders, encoders, and multiplexers

• Sequential logic: Latches, flip-flops

• Finite state machines

• Assembly language programming

Course topics

• Overview of compilation of higher-level languages

• Computer organization

• Microcontrollers

Software

• Easy to change and design

• Usually has low performance compared to hardware

implementation

• High power consumption

• General-purpose processor

• Digital signal processor (DSP)

• Field programmable gate array (FPGA)

• Application specific integrated circuit (ASIC)

Hardware

• Usually difficult to design and implement compared to software

– Hardware description languages can make this easier

• Necessary (all software runs on hardware)

• High performance

• Low power

Hardware/software rules of thumb

• If you can do it in software, do it in software

– However, some things can’t be done in a sane way with

software

• If you can’t do it in software but you can do it with an HDL, do it

with an HDL

– Sometimes the results of automation aren’t good enough

• If you’re tired, don’t do hardware implementation

– Software design errors usually mean wasted time

– Hardware design errors often mean fried chips

Embedded systems

• Special-purpose computers, computers within devices which are

generally not seen to be computers

• Larger market than general-purpose computers by volume and

monetary value

• Microcontrollers rule

• Cool application-specific optimizations

– Power

– Size

– Reliability

– Hard deadlines

Market

• How large is the semiconductor market?

• $164.4×109 for 2003 and growing fast

– Semiconductor Industry Association

• $213×109 in 2004

Market

• $213×109 in 2004

Market

• $213×109 in 2004

Digital and analog signals

time (µs)

• Analog: Continuously varying signal

• Digital: Discrete values, assumed instantaneous transition

• In reality, digital assumption is approximation

• Use thresholds

time (µs)

• Use thresholds

time (µs)

• Use thresholds

undefined

time (µs)

• Use thresholds

Digital voltage regeneration

0VIN 3.30

Error in input appears on output

0VIN 3.30

Voltage regeneration hides input variation

Boolean algebra

• The only values are 0 (or false) and 1 (or true)

• One can define operations/functions/gates

– Boolean values as input and output

• A truth table enumerates output values for all input value

combinations

a b a · b

ba a b

a AND b = a ∧ b = a · b = a b

a b a + b

ab a + b

a OR b = a ∨ b = a + b

NOT a = a’ = a

Combinational vs. sequential logic

plain old combinational logicq

D flip−flopsa b

• No feedback between inputs and outputs – combinational

– Outputs a function of the current inputs, only

• Feedback – sequential

D flip−flopsa b

Sequential logic

• Outputs depend on current state and (maybe) current inputs

• Next state depends on current state and input

• For implementable machines, there are a finite number of states

• Synchronous

– State changes upon clock event (transition) occurs

• Asynchronous

– State changes upon inputs change, subject to circuit delays

Summary

• Brief overview

• Administrative stuff

• Introduction and definitions

Reading assignment (for next class)

• Sections 1.1, 2.1, and 2.2

• CMOS handout from M. M. Mano and C. R. Kime, Web

supplements to Logic and Computer Design Fundamentals.

Prentice-Hall, Englewood Cliffs, NJ, 2004.

http://www.writphotec.com/mano/Supplements

• Read these by the next class

Computer geek culture references

• Zi+1 = Z2i+K

Mandelbrot set display code

threshold = 1000

iter = 500

def f(c, iter):

a = (0 + 0j)

for i in xrange(iter):

a = a**2 + c

if abs(a) > threshold:

return a

desc = [[complex(x, y) for x in xfrange(-2, 2, 0.0015)]

for y in xfrange(1, -1, -0.0015)]

Mandelbrot set image produced by code

Computers enabled many inventions

• Simulation, automation, knowledge discovery

• In astrophysics, chemistry, biology, medicine, etc.

Today’s goals

• Adminstrative stuff

• Review

• Combinational logic design example

• Understand switch model and CMOS

• Be capable of manipulating Boolean formulas

Possible grading scheme

• 15% homeworks

• 35% labs

• 30% final exam

Grading

Some requested additional homework weight

• 20% homeworks

• 35% labs

• 27% final exam

Planned schedule

• Mondays: Labs assigned and collected

• Wednesdays: Homeworks collected and assigned

• Friday’s class will normally focus on the lab and homework of the

week, and will be given by Zhenyu Gu

Review

• What is a truth table?

• Combinational vs. sequential logic?

• Symbol and notation for AND, OR, NOT?

• Other gates also exist, e.g., NAND, NOR, XOR, XNOR

Case study of simple combinational logic design

Seven-segment display

• Given: A four-bit binary input

• Display a decimal digit ranging from zero to nine

• Use a seven-segment display

Case study of simple combinational logic design

Seven-segment display

• Given: A four-bit binary input

• Display a decimal digit ranging from zero to nine

• Use a seven-segment display

Case study – Seven-segment

i3 i2 i1 i0 dec

0 0 0 0 00 0 0 1 10 0 1 0 20 0 1 1 30 1 0 0 40 1 0 1 50 1 1 0 60 1 1 1 71 0 0 0 81 0 0 1 9

i3 i2 i1 i0 dec L1 L2 L3 L4 L5 L6 L7

0 0 0 0 0 1 0 1 1 1 1 1

0 0 0 1 1 0 0 0 0 0 1 1

0 0 1 0 2 1 1 1 0 1 1 0

0 0 1 1 3 1 1 1 0 0 1 1

0 1 0 0 4 0 1 0 1 0 1 1

0 1 0 1 5 1 1 1 1 0 0 1

0 1 1 0 6 1 1 1 1 1 0 1

0 1 1 1 7 1 0 0 0 0 1 1

1 0 0 0 8 1 1 1 1 1 1 1

1 0 0 1 9 1 1 0 1 0 1 1

i3 i2 i1 i0 dec L1 L2 L3 L4 L5 L6 L7

0 0 0 0 0 1 0 1 1 1 1 1

0 0 0 1 1 0 0 0 0 0 1 1

0 0 1 0 2 1 1 1 0 1 1 0

0 0 1 1 3 1 1 1 0 0 1 1

0 1 0 0 4 0 1 0 1 0 1 1

0 1 0 1 5 1 1 1 1 0 0 1

0 1 1 0 6 1 1 1 1 1 0 1

0 1 1 1 7 1 0 0 0 0 1 1

1 0 0 0 8 1 1 1 1 1 1 1

1 0 0 1 9 1 1 0 1 0 1 1

i3 i2 i1 i0 dec L1 L2 L3 L4 L5 L6 L7

0 0 0 0 0 1 0 1 1 1 1 1

0 0 0 1 1 0 0 0 0 0 1 1

0 0 1 0 2 1 1 1 0 1 1 0

0 0 1 1 3 1 1 1 0 0 1 1

0 1 0 0 4 0 1 0 1 0 1 1

0 1 0 1 5 1 1 1 1 0 0 1

0 1 1 0 6 1 1 1 1 1 0 1

0 1 1 1 7 1 0 0 0 0 1 1

1 0 0 0 8 1 1 1 1 1 1 1

1 0 0 1 9 1 1 0 1 0 1 1

i3 i2 i1 i0 dec L1 L2 L3 L4 L5 L6 L7

0 0 0 0 0 1 0 1 1 1 1 1

0 0 0 1 1 0 0 0 0 0 1 1

0 0 1 0 2 1 1 1 0 1 1 0

0 0 1 1 3 1 1 1 0 0 1 1

0 1 0 0 4 0 1 0 1 0 1 1

0 1 0 1 5 1 1 1 1 0 0 1

0 1 1 0 6 1 1 1 1 1 0 1

0 1 1 1 7 1 0 0 0 0 1 1

1 0 0 0 8 1 1 1 1 1 1 1

1 0 0 1 9 1 1 0 1 0 1 1

i3 i2 i1 i0 dec L1 L2 L3 L4 L5 L6 L7

0 0 0 0 0 1 0 1 1 1 1 1

0 0 0 1 1 0 0 0 0 0 1 1

0 0 1 0 2 1 1 1 0 1 1 0

0 0 1 1 3 1 1 1 0 0 1 1

0 1 0 0 4 0 1 0 1 0 1 1

0 1 0 1 5 1 1 1 1 0 0 1

0 1 1 0 6 1 1 1 1 1 0 1

0 1 1 1 7 1 0 0 0 0 1 1

1 0 0 0 8 1 1 1 1 1 1 1

1 0 0 1 9 1 1 0 1 0 1 1

i3 i2 i1 i0 dec L1 L2 L3 L4 L5 L6 L7

0 0 0 0 0 1 0 1 1 1 1 1

0 0 0 1 1 0 0 0 0 0 1 1

0 0 1 0 2 1 1 1 0 1 1 0

0 0 1 1 3 1 1 1 0 0 1 1

0 1 0 0 4 0 1 0 1 0 1 1

0 1 0 1 5 1 1 1 1 0 0 1

0 1 1 0 6 1 1 1 1 1 0 1

0 1 1 1 7 1 0 0 0 0 1 1

1 0 0 0 8 1 1 1 1 1 1 1

1 0 0 1 9 1 1 0 1 0 1 1

i3 i2 i1 i0 dec L1 L2 L3 L4 L5 L6 L7

0 0 0 0 0 1 0 1 1 1 1 1

0 0 0 1 1 0 0 0 0 0 1 1

0 0 1 0 2 1 1 1 0 1 1 0

0 0 1 1 3 1 1 1 0 0 1 1

0 1 0 0 4 0 1 0 1 0 1 1

0 1 0 1 5 1 1 1 1 0 0 1

0 1 1 0 6 1 1 1 1 1 0 1

0 1 1 1 7 1 0 0 0 0 1 1

1 0 0 0 8 1 1 1 1 1 1 1

1 0 0 1 9 1 1 0 1 0 1 1

i3 i2 i1 i0 dec L1 L2 L3 L4 L5 L6 L7

0 0 0 0 0 1 0 1 1 1 1 1

0 0 0 1 1 0 0 0 0 0 1 1

0 0 1 0 2 1 1 1 0 1 1 0

0 0 1 1 3 1 1 1 0 0 1 1

0 1 0 0 4 0 1 0 1 0 1 1

0 1 0 1 5 1 1 1 1 0 0 1

0 1 1 0 6 1 1 1 1 1 0 1

0 1 1 1 7 1 0 0 0 0 1 1

1 0 0 0 8 1 1 1 1 1 1 1

1 0 0 1 9 1 1 0 1 0 1 1

i3 i2 i1 i0 dec L1 L2 L3 L4 L5 L6 L7

0 0 0 0 0 1 0 1 1 1 1 1

0 0 0 1 1 0 0 0 0 0 1 1

0 0 1 0 2 1 1 1 0 1 1 0

0 0 1 1 3 1 1 1 0 0 1 1

0 1 0 0 4 0 1 0 1 0 1 1

0 1 0 1 5 1 1 1 1 0 0 1

0 1 1 0 6 1 1 1 1 1 0 1

0 1 1 1 7 1 0 0 0 0 1 1

1 0 0 0 8 1 1 1 1 1 1 1

1 0 0 1 9 1 1 0 1 0 1 1

i3 i2 i1 i0 dec L1 L2 L3 L4 L5 L6 L7

0 0 0 0 0 1 0 1 1 1 1 1

0 0 0 1 1 0 0 0 0 0 1 1

0 0 1 0 2 1 1 1 0 1 1 0

0 0 1 1 3 1 1 1 0 0 1 1

0 1 0 0 4 0 1 0 1 0 1 1

0 1 0 1 5 1 1 1 1 0 0 1

0 1 1 0 6 1 1 1 1 1 0 1

0 1 1 1 7 1 0 0 0 0 1 1

1 0 0 0 8 1 1 1 1 1 1 1

1 0 0 1 9 1 1 0 1 0 1 1

i3 i2 i1 i0 dec L1 L2 L3 L4 L5 L6 L7

0 0 0 0 0 1 0 1 1 1 1 1

0 0 0 1 1 0 0 0 0 0 1 1

0 0 1 0 2 1 1 1 0 1 1 0

0 0 1 1 3 1 1 1 0 0 1 1

0 1 0 0 4 0 1 0 1 0 1 1

0 1 0 1 5 1 1 1 1 0 0 1

0 1 1 0 6 1 1 1 1 1 0 1

0 1 1 1 7 1 0 0 0 0 1 1

1 0 0 0 8 1 1 1 1 1 1 1

1 0 0 1 9 1 1 0 1 0 1 1

Implement L4

i3 i2 i1 i0 dec L4

0 0 0 0 0 1

0 0 0 1 1 0

0 0 1 0 2 0

0 0 1 1 3 0

0 1 0 0 4 1

0 1 0 1 5 1

0 1 1 0 6 1

0 1 1 1 7 0

1 0 0 0 8 1

1 0 0 1 9 1

L4 implementation

In a future lecture, I’ll explain how to do this sort of design.

L4 implementation

In a future lecture, I’ll explain how to do this sort of design.

Switch-based design representation

• A switch shorts or opens two points dependant on a control signal

• Used as models for digital transistors

• Why is using normally open and normally closed particularly

useful for CMOS?

– NMOS and PMOS transistors easy to model

Switch-based design representation

• A switch shorts or opens two points dependant on a control signal

• Used as models for digital transistors

• Why is using normally open and normally closed particularly

useful for CMOS?

– NMOS and PMOS transistors easy to model

Switch-based definitions

control

normally openswitch

closed switch

open switch

control

switch

open switch

closed switch

normally closed

Microwave control example

haltmicrowave

water vaporsensed

at least fiveminutes elapsed

cancel buttonpressed

• What happens if the cancel button is not pressed and five

minutes haven’t yet passed?

– The output value is undefined.

Microwave control example

haltmicrowave

water vaporsensed

at least fiveminutes elapsed

cancel buttonpressed

• What happens if the cancel button is not pressed and five

minutes haven’t yet passed?

– The output value is undefined.

Constraints on network output

Under all possible combinations of input values

• Each output must be connected to an input value

• No output may be connected to conflicting input values

Switch-based AND

output

Note that this requires

• Normally closed switches that transmit false signals well

• Normally open switches that transmit true signals well

Switch-based AND

output

Note that this requires

• Normally closed switches that transmit false signals well

• Normally open switches that transmit true signals well

Relationship with CMOS

• Metal Oxide Semiconductor

• Positive and negative carriers

• Complimentary MOS

• PMOS gates are like normally closed switches that are good at

transmitting only true (high) signals

• NMOS gates are like normally open switches that are good at

transmitting only false (low) signals

NAND gate

• Therefore, NAND and NOR gates are used in CMOS design

instead of AND and OR gates

output

NAND gate

• Therefore, NAND and NOR gates are used in CMOS design

instead of AND and OR gates

output

Transistors

• Basic device in NMOS and PMOS (CMOS) technologies

• Can be used to construct any logic gate

NMOS transistor

silicon bulk (P)

drain (N)source (N)

NMOS transistor

silicon bulk (P)

drain (N)source (N) channeloxide

NMOS transistor

• Metal–oxide semiconductor (MOS)

– Now, it’s actually polysilicon–oxide semiconductor

• P-type bulk silicon doped with positively charged ions

• N-type diffusion regions doped with negatively charged ions

• Gate can be used to pull a few electrons near the oxide

– Forms channel region, conduction from source to drain starts

• NMOS turns on when the gate is high

• PMOS just like NMOS, with N and P regions swapped

• PMOS turns on when the gate is low

• NMOS good at conducting low (0s)

• PMOS good at conducting high (1s)

• Use NMOS and PMOS transistors together to build circuits

– Complementary metal oxide silicon (CMOS)

CMOS NAND gate

pull−up network

pull−down network

CMOS NAND gate layout

CMOS inverter operation

A=0B=1

CMOS inverter operation

B=0A B

NAND operation

B=0A=0

NAND operation

Z=1A=0

blocked

NAND operation

blocked

NAND operation

NOR operation

B=1Z=0

blocked

NOR operation

A=1Z=0

blocked

NOR operation

A=1 B=1Z=0

Threshold effect on NMOS/PMOS transistors

• Recall that NMOS transmits low values easily. . .

• . . . transmits high values poorly

• PMOS transmits high values easily. . .

• . . . transmits low values poorly

• This is due to the effect of the transistors’ thresholds

• VT, or threshold voltage, is commonly 0.7 V

• NMOS conducts when VGS > VT

• PMOS conducts when VGS < −VT

• What happens if an NMOS transistor’s source is high?

• Or a PMOS transistor’s source is low?

• Alternatively, if one states that VTN = 0.7 V and VTP = −0.7 V

then NMOS conducts when VGS > VTN and PMOS conducts

when VGS < VTP

NMOS transistor

silicon bulk (P)

drain (N)source (N)

• If an NMOS transistor’s input were VDD (high), for VGS > VTN,

the gate would require a higher voltage than VDD

• If an PMOS transistor’s input were VSS (low), for VGS < VTP, the

gate would require a lower voltage than VSS

Implications of threshold

NAND/NOR easy to build in CMOS

Implications of threshold

AND/OR requires more area, power, time

CMOS transmission gates (switches)

• NMOS is good at transmitting 0s

– Bad at transmitting 1s

• PMOS is good at transmitting 1s

– Bad at transmitting 0s

• To build a switch, use both: CMOS

CMOS transmission gate (TG)

C = 1blocked

blocked

C = 1blocked

blockedB =High-Z

Other TG diagram

What can we build with TGs?

• Anything. . . try some examples.

Summary

• Administrative details

• Combinational logic design example

• Logic gates can be implemented with physical devices, e.g,

• Underlying technology influences higher-level representation

– NAND, NOR vs. AND, OR

Reading assignment

• Section 2.3

Computer geek culture reference

• http://slashdot.org

• http://www.python.org

Today’s topics

• Quiz (ungraded)

• Finish CMOS and basic gates

• Boolean algebra

Quiz (ungraded)

• What is the relationship between a truth table and a Boolean

formula?

• What is the relationship between a Boolean formula and a

combinational circuit?

• What quirks does the CMOS implementation technology have?

• What is voltage regeneration?

• What practices are unsafe in switch-based design? Why?

Boolean algebra

• Set of elements, B

• Binary operators, [ AND, ∧, *, · ], [ OR, ∨, + ]

– We’ll prefer · and +

– · frequently omitted

• Unary operator, [ NOT, ’, o ]

Axioms of Boolean algebra

∃x,y∈ B s.t. x 6= y

closure ∀x,y∈ B xy∈ B

x+y∈ B

commutative laws ∀x,y∈ B xy= yx

x+y = y+x

identities 0,1 ∈ B,∀x∈ B x1 = x

x+0 = x

Axioms of Boolean algebra

∃x,y∈ B s.t. x 6= y

distributive laws ∀x,y,z∈ B x+(yz) = (x+y)(x+z)

x(y+z) = xy+xz

complement x∈ B xx = 0

x+ x = 1

De Morgan’s laws

(a+b) = a b

ab = a + b

f (x1,x2, . . . ,xn, ·,+) = f (x1 , x2 , . . . , xn ,+, ·)

• Those xs could be functions

• Apply in stages

– Top-down

De Morgan’s laws example

a · (bc)

a · (b + c)

Representations of Boolean functions

• Truth table

• Expression using only ·, +, and ’

• Symbolic

• Karnaugh map

– More useful as visualization and optimization tool

Review: AND

a b a b

ba a b

a AND b = a b

Will show Karnaugh map later

Review: OR

a b a + b

ab a + b

a OR b = a + b

Review: NOT

NOT a = a

Different representations possible

Z = ((C+D) B) A

Z = (C+D) A B

Different representations possible

Z = ((C+D) B) A

Z = (C+D) A B

Simplifying logic functions

• Minimize literal count (related to gate count, delay)

• Minimize gate count

• Minimize levels (delay)

• Trade off delay for area

– Sometimes no real cost

Proving theorems = simplification

Prove XY+XY = X

XY+XY = X(Y+ Y ) distributive law

X(Y + Y ) = X(1) complementary law

X(1) = X identity law

Proving theorems = simplification

Prove X +XY = X

X +XY = X1+XY identity law

X1+XY = X(1+Y) distributive law

X(1+Y) = X1 identity law

X1 = X identity law

Literals

• Each appearance of a variable (complement) in expression

• Fewer literals usually implies simpler to implement

• E.g., Z = ABC+ A B+ A BC + BC

– Three variables, ten literals

NANDs and NORs

• Can be implemented in CMOS

– More on this later

• X NAND Y = XY

• X NOR Y = X +Y

• Do we need inverters?

Summary

• Finished CMOS and basic gates

• Boolean algebra

Reading assignment

• Sections 2.4 and 2.5

Next lectures

• Karnaugh maps

• Visual minimization

• We’ll also learn the optimal Quine-McCluskey method

– Optimal two-level minimization is fun!

Breadboard

74LS00

Logic probe

Light emitting diodes (LEDs)

Never drive an LED without a series current-limiting resistor

rounded

Resistors

• Color code sheet in your orange box

• Colored bands indicate numbers

• Black (0), brown (1), red (2), orange (3), yellow (4), etc.

• What is Orange, Orange, Black?

• What about Orange, Orange, Brown?

Transistor to transistor logic (TTL)

• Consumes more power than CMOS

• Generally more difficult to damage than CMOS (ESD)

• Inputs “float high”

• What does this imply?

• Why is it good for prototyping?

Guidelines

• Connect all inputs to some signal, best not to rely on floating

– Good practice for CMOS, where it’s essential

• Color-code wiring in complicated circuits

– Learn how to strip wire

• Don’t cross wire over chips

• Double-check VDD and VSSwiring

• Watch for hot chips

• Use current-limiting resistors on LEDs

Circuit diagram example

input circuit

output circuit

qx red

(A) 74LS00

Incomplete circuit diagram example

Summary

• Demo to put prototyping in context

• Breadboarding lecture and demo

Prototypeing trends

• Surface mount

• FPGAs

• Virtual prototypeing

• http://www.digikey.com

• http://www.mouser.com

• http://www.jameco.com

Summary

• Transmission gates review

• Two-level logic

• Karnaugh maps

C = 1blocked

blocked

C = 1blocked

blockedB =High-Z

Other TG diagram

TG examplea a b b

Impact of control on input

TG’s resistance

a’s internal resistanceTG’s resistance

TG’s resistance

Logic minimization motivation

• Want to reduce area, power consumption, delay of circuits

• Hard to exactly predict circuit area from equations

• Can approximate area with SOP cubes

• Minimize number of cubes and literals in each cube

• Algebraic simplification difficult

– Hard to guarantee optimality

Logic minimization motivation

• K-maps work well for small problems

– Too error-prone for large problems

– Don’t ensure optimal prime implicant selection

• Quine-McCluskey optimal and can be run by a computer

– Too slow on large problems

• Some advanced heuristics usually get good results fast on large

problems

• Want to learn how these work and how to use them?

• Take Advanced Digital Logic Design

Boolean function minimization

• Algebraic simplification

– Not systematic

– How do you know when optimal solution has been reached?

• Optimal algorithm, e.g., Quine-McCluskey

– Only fast enough for small problems

– Understanding these is foundation for understanding more

advanced methods

• Not necessarily optimal heuristics

– Fast enough to handle large problems

Karnaugh maps (K-maps)

• Fundamental attribute is adjacency

• Useful for logic synthesis

• Helps logic function visualization

Karnaugh maps

b10110100

Karnaugh maps

b10110100

1011010000

Sum of products (SOP)

bf(a,b)

+(a b)

bf(a,b)

+(a b)

bf(a,b)

+(a b)

bf(a,b)

+(a b)

Implicants

1 1 1 1

101 11 10

f(a,b,c)

Implicants

implicant

1 1 1 1

101 11 10

f(a,b,c)

Implicants

implicant

1 1 1 1

101 11 10

f(a,b,c)

Implicants

implicant

1 1 1 1

101 11 10

f(a,b,c)

Implicants

prime implicant

1 1 1 1

101 11 10

f(a,b,c)

Prime implicants are not covered by other implicants

Implicants

essential prime implicant

1 1 1 1

101 11 10

f(a,b,c)

Essential prime implicants uniquely cover minterms

Implicants

1 1 1 1

101 11 10

f(a,b,c)

Implicants

1 1 1 1

101 11 10

f(a,b,c)

K-map example

• Minimize f (a,b,c,d) = ∑(1,3,8,9,10,11,13)

• f(a, b, c, d) = a b + b d+a c d

K-map example

• Minimize f (a,b,c,d) = ∑(1,3,8,9,10,11,13)

• f(a, b, c, d) = a b + b d+a c d

K-map simplification technique

For all minterms

• Find maximal groupings of 1’s and X’s adjacent to that minterm.

• Remember to consider top/bottom row, left/right column, and

corner adjacencies.

• These are the prime implicants.

• Revisit the 1’s elements in the K-map.

• If covered by single prime implicant, the prime is essential, and

participates in final cover.

• The 1’s it covers do not need to be revisited.

• If there remain 1’s not covered by essential prime implicants,

• Then select the smallest number of prime implicants that cover

the remaining 1’s.

• This can be difficult for complicated functions.

• Will present an algorithm for this in a future lecture.

Product of sums (POS)

bf(a,b)

(a +b)·(

bf(a,b)

(a +b)·(

bf(a,b)

(a +b)·(

bf(a,b)

(a +b)·(

bf(a,b)

(a +b)·(

POS K-map techniques

• Direct reading by covering zeros and inverting variables

• Invert function

• Do SOP

• Invert again

• Apply De Morgan’s laws

POS K-map example

• Minimize f (a,b,c) = ∏(2,4,5,6)

• f (a,b,c) = (b +c)(a +b)

POS K-map example

• Minimize f (a,b,c) = ∏(2,4,5,6)

• f (a,b,c) = (b +c)(a +b)

SOP from Karnaugh map

00 11 1001

f(a,b,c,d)cd

00 11 1001

f(a,b,c,d)cd

00 11 1001

f(a,b,c,d)cd

00 11 1001

f(a,b,c,d)cd

00 11 1001

f(a,b,c,d)cd

00 11 1001

f(a,b,c,d)cd

00 11 1001

f(a,b,c,d)cd

00 11 1001

f(a,b,c,d)cd

00 11 1001

f(a,b,c,d)cd

00 11 1001

f(a,b,c,d)cd

00 11 1001

f(a,b,c,d)cd

00 11 1001

f(a,b,c,d)cd

00 11 1001

f(a,b,c,d)cd

00 11 1001

f(a,b,c,d)cd

00 11 1001

f(a,b,c,d)cd

00 11 1001

f(a,b,c,d)cd

Six-variable K-map example

z(a,b,c,d,e, f ) = ∑(2,8,10,18,24,26,34,37,42,45,50,53,58,61)

Six-variable K-map exampleCD

AB =00

AB =01

00 01 11 10 00

0 4 12 8

1 5 13 9

3 7 15 11

2 6 14 10

16 20 28 24

17 21 29 25

19 23 31 27

18 22 30 26

AB =11

00 01 11 10 00

48 52 60 56

49 53 61 57

51 55 63 59

50 54 62 58

AB =10

00 01 11 10 00

32 36 44 40

33 37 45 41

35 39 47 43

34 38 46 42

AB =00

AB =01

00 01 11 10

00 01 11 10 00

AB =11

00 01 11 10 00

AB =10

00 01 11 10

Six-variable K-map example

z(a,b,c,d,e, f ) = d e f +ad e f + a C d f

DON’T CARE logic

• All specified Boolean values are 0 or 1

• However, during design some values may be unspecified

– Don’t care values (×)

• ×s allow circuit optimization, i.e.,

– Incompletely specified functions allow optimization

DON’T CARE values

bf(a,b)

DON’T CARE values

bf(a,b)

Can let the undefined values be zero

• Correct. . .

• . . . however, complicated

+(a b)

DON’T CARE values

bf(a,b)

Can let the undefined values be zero

• Correct. . .

• . . . however, complicated

+(a b)

DON’T CARE values

bf(a,b)

Instead, leave these values undefined (×)

• Also called DON’T CARE values

• Allows any function implementing the specified values to be used

• E.g., could use(

+(a b)

DON’T CARE values

bf(a,b)

Instead, leave these values undefined (×)

• Also called DON’T CARE values

• Allows any function implementing the specified values to be used

• E.g., could use(

+(a b)

• However, best to use simpler 1

Don’t care K-map example

• Minimize f (a,b,c,d) = ∑(1,3,8,9,10,11,13)+d(5,7,15)

• f (a,b,c,d) = a b +d

Don’t care K-map example

• Minimize f (a,b,c,d) = ∑(1,3,8,9,10,11,13)+d(5,7,15)

• f (a,b,c,d) = a b +d

Two-level logic is necessary

bf(a,b)

Some Boolean functions can not be represented with one logic level

+(a b)

bf(a,b)

+(a b)

bf(a,b)

+(a b)

bf(a,b)

+(a b)

bf(a,b)

+(a b)

Two-level logic is sufficient

bf(a,b)

• All Boolean functions can be represented with two logic levels

• Given k variables, 2K minterm functions exist

• Select arbitrary union of minterms

Two-level well-understood

• As we will see later, optimal minimization techniques known for

two-level

• However, optimal two-level solution may not be optimal solution

– Sometimes a suboptimal solution to the right problem is better

than the optimal solution to the wrong problem

Two-level sometimes impractical

00 11 10010 1

f(a,b,c,d)cd

Consider a 4-term XOR (parity) gate: a⊕b⊕c⊕d(

a b c d)

+(a b c d)+(a b c d)+(

a b c d)

Two-level sometimes impractical

00 11 10010 1

f(a,b,c,d)cd

Consider a 4-term XOR (parity) gate: a⊕b⊕c⊕d(

a b c d)

+(a b c d)+(a b c d)+(

a b c d)

Two-level weakness

• Two-level representation is exponential

• However, it’s a simple concept

– Is ∑ni xi odd?

• Problem with representation, not function

Two-level weakness

Two-level representations also have other weaknesses

• Conversion from SOP to POS is difficult

– Inverting functions is difficult

– ·-ing two SOPs or +ing two POSs is difficult

• Neither general POS or SOP are canonical

– Equivalence checking difficult

• POS satisfiability ∈ NP-complete

– Basically, it can’t be solved quickly for large problem instances

Summary

• Transmission gate review

• Two-level logic

• Karnaugh maps

Reading assignment

• Section 2.6

• Also read TTL reference, D. Lancaster, TTL Cookbook. Howard

W. Sams & Co., Inc., 1974, as needed

Today’s topics

• Lab and lecture comments

• Review: Minimization overview

• Review: Karnaugh map SOP minimization

• POS using SOP K-map trick

• Quine-McCluskey optimal two-level minimization method

Lab and lecture comments

• Anybody falling behind?

• If something isn’t making sense, stop me and I’ll elaborate using

the chalkboard

– I’m glad to do it!

• Lab expectations (lab two and above)

– Complete schematics

– Easy to debug, color-coded wiring

– Terse but clear description

Review: Minimization techniques

Advantages and disadvantages?

• Algebraic manipulation

• Karnaugh maps

• Quine-McCluskey

• Advanced topic: Kernel extraction

• Advanced topic: Heuristic minimization, e.g., Espresso

Deriving POS

00 11 1001

f(a,b,c,d)ab

Find SOP form for zeros:

f = abz + cd+ a bd

Deriving POS

Apply De Morgan’s theorem

f = abd + c d+ a bd (1)

f = abd + c d+ a bd (2)

· (cd) ·(

a + b +d)(

c+ d)(

a+b+ d)

• Advanced topic: Read the POS expression directly from the

Karnaugh map

– More difficult

Quine-McCluskey two-level logic minimization

• Compute prime implicants with a well-defined algorithm

– Start from minterms

– Merge adjacent implicants until further merging impossible

• Select minimal cover from prime implicants

– Unate covering problem

• What is happening?

– ab+ab = a

Computing prime implicants

000100101000

10011010

11011110

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

000X0000

000100101000

10011010

11011110

0000 000X

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

000X0000

000100101000

10011010

11011110

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

00X0000X0000

000100101000

10011010

11011110

00010010

000000X0

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

00X0000X0000

000100101000

10011010

11011110

00010010

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

00X0X000

000X0000

000100101000

10011010

11011110

000100101000

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

00X0X000

000X0000

000100101000

10011010

11011110

000100101000

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

00X0X000X001

000X0000

000100101000

10011010

11011110

000100101000

X0010001

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

00X0X000X001

000X0000

000100101000

10011010

11011110

000100101000

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

00X0X000X001X010

000X0000

000100101000

10011010

11011110

000100101000

10011010

0010 X010

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

00X0X000X001X010

000X0000

000100101000

10011010

11011110

000100101000

10011010

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

00X0X000X001X010100X

000X0000

000100101000

10011010

11011110

000100101000

10011010

1000 100X

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

00X0X000X001X010100X

000X0000

000100101000

10011010

11011110

000100101000

10011010

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

00X0X000X001X010100X10X0

000X0000

000100101000

10011010

11011110

000100101000

10011010

100010X0

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

00X0X000X001X010100X10X0

000X0000

000100101000

10011010

11011110

000100101000

10011010

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

00X0X000X001X010100X10X01X01

000X0000

000100101000

10011010

11011110

000100101000

100110101101

1001 1X01

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

00X0X000X001X010100X10X01X01

000X0000

000100101000

10011010

11011110

000100101000

100110101101

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

00X0X000X001X010100X10X01X011X10

000X0000

000100101000

10011010

11011110

000100101000

1001101011011110

1010 1X10

1110∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

00X0X000X001X010100X10X01X011X10

000X0000

000100101000

10011010

11011110

000100101000

1001101011011110

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

00X0X000X001X010100X10X01X011X10111X

000X0000

000100101000

10011010

11011110

000100101000

10011010

110111101111

111X1110

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

00X0X000X001X010100X10X01X011X10111X

000X0000

000100101000

10011010

11011110

000100101000

10011010

11011110

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

00X0X000X001X010100X10X01X011X10111X11X1

000X0000

000100101000

10011010

11011110

000100101000

10011010

110111101111

11X11101

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

00X0X000X001X010100X10X01X011X10111X11X1

000X0000

000100101000

10011010

11011110

000100101000

10011010

11011110

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

X00X00X0X000X001X010100X10X01X011X10111X11X1

000X0000

000100101000

10011010

11011110

0000 000X

000100101000 100X

10011010

11011110

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

X00X00X0X000X001X010100X10X01X011X10111X11X1

000X0000

000100101000

10011010

11011110

0000 000X

000100101000 100X

10011010

11011110

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

X00XX0X000X0

X000X001X010100X10X01X011X10111X11X1

000X0000

000100101000

10011010

11011110

0000 000X00X0

000100101000 100X

10X010011010

11011110

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

X00XX0X000X0

X000X001X010100X10X01X011X10111X11X1

000X0000

000100101000

10011010

11011110

0000 000X00X0

000100101000 100X

10X010011010

11011110

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

X00XX0X000X0

X000X001X010100X10X01X011X10111X11X1

000X0000

000100101000

10011010

11011110

0000 000X00X0X000X0010001

00101000 100X

10X010011010

11011110

X000X001

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

X00XX0X000X0

X000X001X010100X10X01X011X10111X11X1

000X0000

000100101000

10011010

11011110

0000 000X00X0X000X0010001

00101000 100X

10X010011010

11011110

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

X00XX0X000X0

X000X001X010100X10X01X011X10111X11X1

000X0000

000100101000

10011010

11011110

0000 000X00X0X000X0010001

00101000

X010100X10X0

10011010

11011110

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

X00XX0X000X0

X000X001X010100X10X01X011X10111X11X1

000X0000

000100101000

10011010

11011110

0000 000X00X0X000X0010001

00101000

X010100X10X0

10011010

11011110

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

Summary

• Review: Minimization overview

• Review: Karnaugh map SOP minimization

• POS using SOP K-map trick

• Quine-McCluskey optimal two-level minimization method

Next lecture – More advanced building blocks

• Encoders and decoders

• MUXs

• Advanced TG techniques

Reading assignment

• Sections 2.7–2.10

• Section 4.6 (decoders and multiplexers only)

• M. M. Mano and C. R. Kime, Web supplements to Logic and

Computer Design Fundamentals. Prentice-Hall, Englewood

Cliffs, NJ, 2004. http://www.writphotec.com/mano/Supplements

handout on tabular method (Quine-McCluskey)

Additional references

• If QM doesn’t click, please also see the following references

• R. H. Katz, Contemporary Logic Design. The

Benjamin/Cummings Publishing Company, Inc., 1994: pp. 85–88

• J. P. Hayes, Introduction to Digital Logic Design. Addison-Wesley,

Reading, MA, 1993 pp. 320, 321

• You can get these from me or the library

• http://www.deepchip.com

Today’s topics

• Ungraded quiz

• ∑ for minterms, ∏ for maxterms

• Review: Quine-McCluskey

• Prime implicant selection in Quine-McCluskey

• Review: Transmission gates

• Multiplexers and demultiplexers

Review: Quine-McCluskey two-level logic

minimization

• Compute prime implicants with a well-defined algorithm

– Start from minterms

– Merge adjacent implicants until further merging impossible

• Select minimal cover from prime implicants

– Unate covering problem

• What is happening?

– ab+ab = a

Review: Computing prime implicants

000100101000

10011010

11011110

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

000X0000

000100101000

10011010

11011110

0000 000X

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

000X0000

000100101000

10011010

11011110

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

00X0000X0000

000100101000

10011010

11011110

00010010

000000X0

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

00X0000X0000

000100101000

10011010

11011110

00010010

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

00X0X000

000X0000

000100101000

10011010

11011110

000100101000

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

00X0X000

000X0000

000100101000

10011010

11011110

000100101000

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

00X0X000X001

000X0000

000100101000

10011010

11011110

000100101000

X0010001

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

00X0X000X001

000X0000

000100101000

10011010

11011110

000100101000

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

00X0X000X001X010

000X0000

000100101000

10011010

11011110

000100101000

10011010

0010 X010

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

00X0X000X001X010

000X0000

000100101000

10011010

11011110

000100101000

10011010

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

00X0X000X001X010100X

000X0000

000100101000

10011010

11011110

000100101000

10011010

1000 100X

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

00X0X000X001X010100X

000X0000

000100101000

10011010

11011110

000100101000

10011010

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

00X0X000X001X010100X10X0

000X0000

000100101000

10011010

11011110

000100101000

10011010

100010X0

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

00X0X000X001X010100X10X0

000X0000

000100101000

10011010

11011110

000100101000

10011010

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

00X0X000X001X010100X10X01X01

000X0000

000100101000

10011010

11011110

000100101000

100110101101

1001 1X01

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

00X0X000X001X010100X10X01X01

000X0000

000100101000

10011010

11011110

000100101000

100110101101

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

00X0X000X001X010100X10X01X011X10

000X0000

000100101000

10011010

11011110

000100101000

1001101011011110

1010 1X10

1110∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

00X0X000X001X010100X10X01X011X10

000X0000

000100101000

10011010

11011110

000100101000

1001101011011110

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

00X0X000X001X010100X10X01X011X10111X

000X0000

000100101000

10011010

11011110

000100101000

10011010

110111101111

111X1110

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

00X0X000X001X010100X10X01X011X10111X

000X0000

000100101000

10011010

11011110

000100101000

10011010

11011110

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

00X0X000X001X010100X10X01X011X10111X11X1

000X0000

000100101000

10011010

11011110

000100101000

10011010

110111101111

11X11101

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

00X0X000X001X010100X10X01X011X10111X11X1

000X0000

000100101000

10011010

11011110

000100101000

10011010

11011110

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

X00X00X0X000X001X010100X10X01X011X10111X11X1

000X0000

000100101000

10011010

11011110

0000 000X

000100101000 100X

10011010

11011110

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

X00X00X0X000X001X010100X10X01X011X10111X11X1

000X0000

000100101000

10011010

11011110

0000 000X

000100101000 100X

10011010

11011110

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

X00XX0X000X0

X000X001X010100X10X01X011X10111X11X1

000X0000

000100101000

10011010

11011110

0000 000X00X0

000100101000 100X

10X010011010

11011110

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

X00XX0X000X0

X000X001X010100X10X01X011X10111X11X1

000X0000

000100101000

10011010

11011110

0000 000X00X0

000100101000 100X

10X010011010

11011110

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

X00XX0X000X0

X000X001X010100X10X01X011X10111X11X1

000X0000

000100101000

10011010

11011110

0000 000X00X0X000X0010001

00101000 100X

10X010011010

11011110

X000X001

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

X00XX0X000X0

X000X001X010100X10X01X011X10111X11X1

000X0000

000100101000

10011010

11011110

0000 000X00X0X000X0010001

00101000 100X

10X010011010

11011110

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

X00XX0X000X0

X000X001X010100X10X01X011X10111X11X1

000X0000

000100101000

10011010

11011110

0000 000X00X0X000X0010001

00101000

X010100X10X0

10011010

11011110

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

X00XX0X000X0

X000X001X010100X10X01X011X10111X11X1

000X0000

000100101000

10011010

11011110

0000 000X00X0X000X0010001

00101000

X010100X10X0

10011010

11011110

∑ = 4

∑ = 0

∑ = 1

∑ = 2

∑ = 3

Definition: Unate covering

Given a matrix for which all entries are 0 or 1, find the minimum

cardinality subset of columns such that, for every row, at least one

column in the subset contains a 1.

I’ll give an example

Definition: Unate covering

Given a matrix for which all entries are 0 or 1, find the minimum

cardinality subset of columns such that, for every row, at least one

column in the subset contains a 1.

I’ll give an example

Prime implicant selection

0X001X X00 X11

000 1 1

On-setminterms

Prime implicants

0X001X X00 X11

000 1 1

On-setminterms

these... cover

Use these to...Prime implicants

0X001X X00 X11

000 1 1

On-setminterms

these... cover

0X001X X00 X11

000 1 1

On-setminterms

these... cover

0X001X X00 X11

000 1 1

On-setminterms

these... cover

Cyclic core

00 01 11 10

Cyclic core

00 01 11 10

Cyclic core

00 01 11 10

Cyclic core

00 01 11 10

Cyclic core

0X1 01X X01 X10 1X010X

00 01 11 10

Cyclic core

0X1 01X X01 X10 1X010X

00 01 11 10

Cyclic core

0X1 01X X01 X10 1X010X

00 01 11 10

Cyclic core

0X1 01X X01 X10 1X010X

00 01 11 10

Implicant selection reduction

• Eliminate rows covered by essential columns

• Eliminate rows dominated by other rows

• Eliminate columns dominated by other columns

Eliminate rows covered by essential columns

Eliminate rows dominated by other rows

Eliminate columns dominated by other columns

Backtracking

• Will proceed to complete solution unless cyclic

• If cyclic, backtrack

– Try all possible options to completion

• Advanced topic: Can use a number of tricks to simplify this

Use bound to constrain search space

• Eliminate rows covered by essential columns

• Eliminate rows dominated by other rows

• Eliminate columns dominated by other columns

• Speed improved, still ∈NP-complete

– Too slow to solve for large problem instances

Loose end – Don’t cares

• What should be done about Xs in QM?

• Should they be included in the initial minterms?

• Should they be required in the Unate Covering problem?

Another example

f (a,b,c) = ∑(1,2,6)+d(3)

Summary

• Review

• Prime implicant selection in Quine-McCluskey

• Multiplexers and demultiplexers

Reading assignment

• Rest of Section 4.6

• Complexity classes

• M. R. Garey and D. S. Johnson, Computers and Intractability: A

Guide to the Theory of NP-Completeness. W. H. Freeman &

Company, NY, 1979

Today’s topics

• Encoders

• Decoders

Encoders

• Assume you have n one-bit signals

• Only one signal can be 1 at a time

• How many states can you be in?

• How many signals are required to encode all those states?

Encoder example

Pressed (i2, i1, i0) Code (o1,o0)

000 00

001 01

010 10

011 XX

100 11

101 XX

110 XX

111 XX

Implementation?

Priority encoder

What if we want the highest-order high signal to dominate?

Pressed (i3, i2, i1) Code (o1,o0)

000 00

001 01

010 10

011 10

100 11

101 11

110 11

111 11

What impact on implementation efficiency?

Decoders

Need to map back from encoded signal to state

Pressed (i1, i0) Code (o3,o2,o1,o0)

00 0001

01 0010

10 0100

11 1000

o0 isn’t always used. Why?

Most straightforward implementation?

Straight-forward decoder implementation

n NOTs

n NOTs n inputs

2n ANDs

Decoder implementation efficiency

• n NOTs

• n2 n-input ANDS

• O(

• Can’t do this for large number of inputs!

• Instead, decompose into multi-level implementation

Multilevel decoder implementation

Starting point

o0 = i2 i1 i0

o1 = i2 i1 i0

o2 = i2 i1 i0

o3 = i2 i1i0

o4 = i2 i1 i0

o5 = i2 i1 i0

o6 = i2i1 i0

o7 = i2i1i0

o0 = i2 ( i1 i0 )

o1 = i2 ( i1 i0)

o2 = i2 (i1 i0 )

o3 = i2 (i1i0)

o4 = i2( i1 i0 )

o5 = i2( i1 i0)

o6 = i2(i1 i0 )

o7 = i2(i1i0)

Reuse terms! Schematic?

o0 = i2 ( i1 i0 )

o1 = i2 ( i1 i0)

o2 = i2 (i1 i0 )

o3 = i2 (i1i0)

o4 = i2( i1 i0 )

o5 = i2( i1 i0)

o6 = i2(i1 i0 )

o7 = i2(i1i0)

Reuse terms! Schematic?

Summary

• Encoders

• Decoders

Reading assignment

Homework assignment two

• Due 12 October

• Brief CMOS and TTL review

• Lab preparation questions

• Two-level logic

• Karnaugh maps

• Quine-McCluskey

• C. Stoll, The Cukoo’s Egg. Bantam Doubleday Dell Publishing

Group, 1989

Today’s topics

• Multiplexers

• Demultiplexers

Multiplexers or selectors

• Routes one of 2n inputs to one output

• n control lines

• Can implement with logic gates

Logic gate MUX

Decoder

However, there is another way. . .

MUX functional table

MUX truth table

I1 I0 C Z

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 0

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 1

Review: CMOS transmission gate (TG)

C = 1blocked

blocked

Review: CMOS transmission gate (TG)

C = 1blocked

blockedB =High-Z

Review: Other TG diagram

DC = 1

D = BC = 0

2:1 MUX

MUX using TGs

Hierarchical MUX implementation

4 :1mux

8 :1mux

2 :1mux

S 1 S 0

I 6I 7

Alternative hierarchical MUX implementation

33 S 0

MUX examples

2:1m ux

Z = A I0 +AI1

MUX examples

I 1I 2I 3

Z = A B I0 + A BI1 +ABI2 +ABI3

MUX examples

I 1I 2I 3

Z8:1m ux

I 4I 5I 6

Z = A B C I0 + A BCI1 + ABC I2 + ABCI3+

AB C I4 +ABCI5 +ABC I6 +ABCI7

MUX properties

• A 2n : 1 MUX can implement any function of n variables

• A 2n−1 : 1 can also be used

– Use remaining variable as an input to the MUX

MUX example

F(A,B,C) = ∑(0,2,6,7)

= A B C + A BC +ABC +ABC

Truth table

A B C F0 0 0 10 0 1 00 1 0 10 1 1 01 0 0 01 0 1 01 1 0 11 1 1 1

Lookup table implementation

8:1MUX

101000111

012345677 S2 S1 S0

AA BB CC

MUX example

F(A,B,C) = ∑(0,2,6,7)

= A B C + A BC +ABC +ABC

Therefore,

A B → F = C

A B→ F = C

AB → F = 0

AB→ F = 1

Truth table

A B C F0 0 0 10 0 1 00 1 0 10 1 1 01 0 0 01 0 1 01 1 0 11 1 1 1

Truth table

A B C F0 0 0 10 0 1 00 1 0 10 1 1 01 0 0 01 0 1 01 1 0 11 1 1 1

Lookup table implementation

4:1MUX

Demultiplexer (DMUX) definitions

• Closely related to decoders

• n control signals

• Single data input can be routed to one of 2n outputs

Recall decoders

n NOTs

DMUXs similar to decoders

oei0 i0

Use extra input to control output signal

Demultiplexer

However, this implementation is dangerous

Demultiplexer

E=High-Z

Demultiplexer

D=High-Z

Demultiplexer

Dangers when implementing with TGs

What if an output is not connected to any input?

Review: Consider undriven inverter inputs

A=0B=1

B=0A B

Set all outputs

Demultiplexers as building blocks

3 :8dec

ABCS2 S1 S 0

Generate minterm based on control signals

Example function

F1 = A BCD+ A BC D+ABCD

F2 = ABC D +ABC= ABC D +ABCD +ABCD

F3 = A + B + C + D = ABCD

Demultiplexers as building blocks

A B C D

S3 S 2 S1 S0

4:16dec

Status

• CMOS

• Switch-based and gate-based design

• Two-level minimization

• Encoders

• Decoder

• Multiplexers

• Demultiplexers

Is anything still unclear? Then let’s do some examples!

Lab three

• Requires error detection

• Read Section 1.4 in the book

• How to build an error injector, i.e., a conditional inverter?

• How to build a two-input parity gate?

• How to build a three-input parity gate from two-input parity gates?

• How to detect even number of ones?

Summary

• CMOS review

• Multiplexers

• Demultiplexers

Reading assignment

• Finish Sections 1.2–1.7

Today’s topics

• Practice midterm

• Questions on MUXs and DMUXs?

• Questions about lab three?

• Number systems

Arithmetic circuits

• Administration

• Number systems

• Adders

– Ripple carry

– Carry lookahead

– Carry select

Introduction to number systems

Consider a base-10 number: 1,293

1,293 = 1 ·103 +2 ·102 +9 ·101 +3 ·100

For base-10, given an n-digit number in which di is the ith digit, the

number is

∑i=0

10i−1 ·di

This works for any base. Convert 2,0123 from base-3 to base-10.

2 ·33 +0 ·32 +1 ·31 +2 ·30

2 ·27+0 ·9+1 ·3+2 ·1

54+0+3+2

Convert 5910 from base-10 to base-3. Repeatedly divide by the

greatest power of b (the base) that is less than the number.

Remainder Try dividing Digit Comment

59 34 = 81 0 Too big

59−0 ·81 = 59 33 = 27 2 O.K.

59−2 ·27 = 5 32 = 9 0 Too big

5−0 ·9 = 5 31 = 3 1 O.K.

5−1 ·3 = 2 30 2 O.K.

020123 = 20123

Conversion works for any base

Review: For base-10, given an n-digit number in which di is the ith

digit, the number isn

∑i=1

10i−1 ·di

For base-b, given an n-digit number in which di is the ith digit, the

number isn

∑i=1

·bi−1 ·di

Useful bases

• 2: Also called binary. Most fundamental base in digital logic.

Know this like the back of your hand.

• 8: Also called octal. Sometimes used by programmers. Prefer

base 16.

• 10: Also called decimal or Arabic.

• 16: Also called hexadecimal or simple hex. One of the most

compact and beautiful representations for digital computer

programmers.

Binary

1 2 4 8 16 32 64 128 256 512 1,024 (1K)

20 21 22 23 24 25 26 27 28 29 210

k 6= K

1 k = 103 = 1,000

1 K = 210 = 1,024

Decimal

• Most commonly used by human beings.

• Also called Arabic.

– Actually developed in India and brought to Europe via Arabian

empire.

• Largely replaced Roman numerals, which were more

cumbersome when writing the large and complicated numbers

used in astronomy and wide-spread trade.

Number systems

• Representation of positive numbers same in most systems

• A few special-purpose alternatives exist, e.g., Gray code

• Alternatives exist for signed numbers

Base-16: Hex

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 1 2 3 4 5 6 7 8 9 A B C D E F

Often prefixed with 0x.

What is 0xFF?

Reading assignment

• Spelling things in ASCII (hex or binary)

• This is one of the lower forms of geek culture, akin to bad puns

• However, at least one university has things written into its

buildings with subtle brick patterns in ASCII binary

4a6934207375616e34206a6931207368653420

6a69342068656e332068616f332077616e3221

Today’s topics

• Number systems

• Adders and subtracters

Other number/encoding systems

• Binary-coded decimal

– Wastes fractional bit for alignment

• ASCII: 7-bit characters

– Parity

– Best to see a chart

– 0x61 = 97 = ‘a’

– 0x47 = 71 = ‘G’

Other number/encoding systems

Unicode: 16-bit

• Similar to ASCII

• International

• Allows about 216 = 65,536 characters

• Enough for symbolic writing systems

Standard unsigned binary numbers

01111000

10 (a)

11 (b)

12 (c)

13 (d)

14 (e)

15 (f)

Given an n-bit number in which di is the ith digit, the number is

∑ni=1 2i−1di

Unsigned addition

Consider adding 9 (1001) and 3 (0011)

1 0 0 1

+ 0 0 1 1

1 1 0 0

Why an extra column?

Unsigned addition

1 0 0 1

+ 0 0 1 1

1 1 0 0

Unsigned addition

1 0 0 1

+ 0 0 1 1

1 1 0 0

Unsigned addition

1 0 0 1

+ 0 0 1 1

1 1 0 0

Unsigned addition

1 0 0 1

+ 0 0 1 1

1 1 0 0

Unsigned addition

1 0 0 1

+ 0 0 1 1

1 1 0 0

Overflow

• If the result of an operation can’t be represented in the available

number of bits, an overflow occurs

• E.g., 0110+1011 = 10001

• Need to detect overflow

Overflow

• If the result of an operation can’t be represented in the available

number of bits, an overflow occurs

• E.g., 0110+1011 = 10001

• Need to detect overflow

Gray code

01111000

515 (f)

14 (e)

12 (c)

13 (d)

11 (b)

10 (a)

Useful for shaft encoding

Sequence?

Gray code

• To convert from a standard binary number to a Gray code

number XOR the number by it’s half (right-shift it)

• To convert from a Gray code number to a standard binary

number, XOR each binary digit with the parity of the higher digits

Given that a number contains n digits and each digit, di , contributes

2i−1 to the number

Pkj = d j ⊕d j+1 · · ·⊕dk−1 ⊕dk

di = di ⊕Pni+1

Gray code

• Converting from Gray code to standard binary is difficult

– Take time approximately proportional to n

• Doing standard arithmetic operations using Gray coded numbers

is difficult

• Generally slower than using standard binary representation

• E.g., addition requires two carries

• Why use Gray coded numbers?

– Analog to digital conversion

– Reduced bus switching activity

Signed number systems

• Three major schemes

– Sign and magnitude

– One’s complement

– Two’s complement

Number system assumptions

• Four-bit machine word

• 16 values can be represented

• Approximately half are positive

• Approximately half are negative

Sign and magnitude

01111000

Sign and magnitude

• dn represents sign

– 0 is positive, 1 is negative

• Two representations for zero

• What is the range for such numbers?

– Range: [−2n−1 +1,2n−1 −1]

Sign and magnitude

• dn represents sign

– 0 is positive, 1 is negative

• Two representations for zero

• What is the range for such numbers?

– Range: [−2n−1 +1,2n−1 −1]

Sign and magnitude

• How is addition done?

• If both numbers have the same sign, add them like unsigned

numbers and preserve sign

• If numbers have differing signs, subtract smaller magnitude from

larger magnitude and use sign of large magnitude number

Sign and magnitude

• Consider 5+−6

• Note that signs differ

• Use magnitude comparison to determine large magnitude: 6−5

• Subtract smaller magnitude from larger magnitude: 1

• Use sign of large magnitude number: −1

Direct subtraction

Consider subtracting 5 (0101) from 6 (0110)

0 1 1 0

− 0 1 0 1

0 0 0 1

• Note that this operation is different from addition

• Sign and magnitude addition is complicated

Direct subtraction

0 1 1 0

− 0 1 0 1

0 0 0 1

Direct subtraction

0 1 1 0

− 0 1 0 1

0 0 0 1

Direct subtraction

0 1 1 0

− 0 1 0 1

0 0 0 1

Direct subtraction

0 1 1 0

− 0 1 0 1

0 0 0 1

One’s compliment

01111000

1111 1

−10 0

One’s compliment

• If negative, complement all bits

• Addition somewhat simplified

• Do standard addition except wrap around carry back to the 0th bit

• Potentially requires two additions of the whole width

– Slow

One’s complement addition

Consider adding -5 (1010) and 7 (0111)

1 0 1 0

+ 0 1 1 1

1 0 1 0

+ 0 1 1 1

1 0 1 0

+ 0 1 1 1

1 0 1 0

+ 0 1 1 1

1 0 1 0

+ 0 1 1 1

0 0 0 1

1 1 1 1

1 0 1 0

+ 0 1 1 1

0 0 0 0

1 1 1 1

1 0 1 0

+ 0 1 1 1

0 0 1 0

Two’s complement

• To negate a number, invert all its bits and add 1

• Like one’s complement, however, rotated by one bit

• Counter-intuitive

– However, has some excellent properties

Two’s complement

01111000

Two’s complement

• Only one zero

– Leads to more natural comparisons

• One more negative than positive number

– This difference is irrelevant as n increases

• Substantial advantage – Addition is easy!

Two’s complement addition

1 1 0 0

+ 0 1 1 0

0 0 1 0

1 1 0 0

+ 0 1 1 0

0 0 1 0

1 1 0 0

+ 0 1 1 0

0 0 1 0

1 1 0 0

+ 0 1 1 0

0 0 1 0

1 1 0 0

+ 0 1 1 0

0 0 1 0

Two’s complement

• No looped carry – Only one addition necessary

• If carry-in to most-significant bit 6= carry-out to most-significant

bit, overflow occurs

• What does this represent?

• Both operands positive and have carry-in to sign bit

• Both operands negative and don’t have carry-in to sign bit

Two’s complement overflow

a b cin cout

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 1

Two’s complement overflow

a b cin cout

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 1

Half adder

For two’s complement, don’t need subtracter

A B cout sum

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

cout= AB

sum= A⊕B

Half adder

Full adder

Need to deal with carry-inA B cin cout sum

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

Full adder

sum= A⊕B⊕cin

cout= AB+A ci+B ci

Cascaded full-adders

A B A Bcout cincincout

A Bcincout

A1A2A3 B1B2B3

sum1sum2sum3

Full adder standard implementation

Six logic gates

Full adder composed of half-adders

Ha lfAdder

HalfAdder

A + B + CISS SS

COCOCI (A + B)A B

AB+ci(A⊕B) = AB+B ci+A ci

Adder/subtracter

sum sum sumsum

A B A B A B

Add/Subtract

A3 B3 B3

A 2 B2 B2

A0 B0 B0

Sel Sel Sel Sel

S3 S2 S1

Overflow

cin cin cin cincout coutcoutcout

Consider input to cin

Ripple-carry delay analysis

• The critical path (to cout) is two gate delays per stage

• Consider adding two 32-bit numbers

• 64 gate delays

– Too slow!

• Consider faster alternatives

Carry lookahead adder

• Lecture notes give detail for completeness

• However, primarily important to understand that carry lookahead

compresses many levels of a carry chain into fewer levels for

• Will need to understand carry select adders in detail

• Carry generate: G = AB

• Carry propagate: P = A⊕B

• Represent sumand cout in terms of G and P

Overview: Carry lookahead adder

sum= A⊕B⊕cin

= P⊕cin

cout= AB+A cin+B cin

= AB+cin(A+B)

= AB+cin(A⊕B)

= G+cin P

Overview: Carry lookahead adder

Flatten carry equations

cin1 = G0 +P0 cout0

cin2 = G1 +P1 cout1 = G1 +P1G0 +P1P0 cout0

cin3 = G2 +P2 cout2 = G2 +P2G1 +P2P1G0 +P2P1P0 cout0

cin4 = G3 +P3C3 = G3 +P3G2 +P3P2G1+

P3P2P1G0 +P3P2P1P0 cout0

Each cin can be implemented in three-level logic

Carry lookahead building block

Pi 1 gate delay

Ci Si 2 gate delays

G i 1 gate delay

Carry lookahead adder

C0P0P0

Carry lookahead delay analysis

• Assume a 4-stage adder with CLA

• Propagate and generate signals available after 1 gate delays

• Carry signals for slices 1 to 4 available after 3 gate delays

• Sum signal for slices 1 to 4 after 4 gate delays

Carry lookahead

• No carry chain slowing down computation of most-significant bit

– Computation in parallel

• More area required

• Each bit has more complicated logic than the last

• Therefore, limited bit width for this type of adder

• Can chain multiple carry lookahead adders to do wide additions

• Note that even this chain can be accelerated with lookahead

– Use internal and external carry lookahead units

Cascaded carry lookahead adder

4−bit Adder

A [15−12] B[15−12] C12C16

S[15−12]

P G4−bit Adder

A [11−8] B[11−8] C8

S[11−8]

P G4−bit Adder

A [7−4] B[7−4] C4

S[7−4]

P G4−bit Adder

A [3−0] B[3−0] C0

S[3−0]

Lookahead Carry UnitC0

P0 G0P1 G1P2 G2P3 G3 C3 C2 C1

P3−0 G3−0

@4@3@2@5

@3@2@5

Delay analysis for cascaded carry lookahead

• Four-stage 16-bit adder

• cin for MSB available after five gate delays

• sumfor MSB available after eight gate delays

• 16-bit ripple-carry adder takes 32 gate delays

• Note that not all gate delays are equivalent

• Depends on wiring, driven load

• However, carry lookahead is usually much faster than ripple-carry

Carry select adders

• Trade even more hardware for faster carry propagation

• Break a ripple carry adder into two chunks, low and high

• Implement two high versions

– high0 computes the result if the carry-out from low is 0

– high1 computes the result if the carry-out from low is 1

• Use a MUX to select a result once the carry-out of low is known

– high0’s cout is never greater than high1’s cout so special-case

MUX can be used

Carry select adder

4−Bit Adder[3:0]

4−Bit Adder[7:4]

2:1 Mspecial−case

010101

4−Bit Adder[7:4]

C8 S7 S6 S5 S4 S3 S2 S1 S0

AdderH

MUX MUX MUX MUX

AdderLow

Delay analysis of carry select adder

• Consider 8-bit adder divided into 4-bit stages

• Each 4-bit stage uses carry lookahead

• The 2:1 MUX adds two gate delays

• 8-bit sum computed after 6 gate delays

• 7 gate delays for carry lookahead

• 16 gate delays for ripple carry

Summary

• Number systems

• Adders and subtracters

Homework three

• Review of a few concepts (should be quick for most of you)

• QM problems

• Encoders, decoders, MUXs, and DMUXs

• Number systems

Reading assignment

• Finish Sections 5.1–5.6

Today’s topics

• Memory

• Latches

• Flip-flops

Memory

• Combinational logic outputs a function of inputs, only

• Sequential logic outputs a function of inputs and state

• State is remembered

• Consider a sequential vending machine

Flip-flop introduction

• Stores, and outputs, a value

• Puts a special clock signal in charge of timing

• Allows output to change in response to clock transition

• More on this later

– Timing and sequential circuits

Feedback and memory

• Feedback is the root of memory

• Can compose a simple loop from NOT gates

• However, there is no way to switch the value

Feedback and memory

• Feedback is the root of memory

• Can compose a simple loop from NOT gates

• However, there is no way to switch the value

TG and NOT-based memory

• Can break feedback path to load new value

• However, potential for timing problems

Ring oscillators

B C D E

1 0 0 0 1

Like pulse shaping circuits with memory

Ring oscillators

A (=X) B C D EE

Period of Repeating Waveform (tp ))Gate Delay (td ))

Reset/set latch

Reset/set timing

Reset Hold Set Reset Set Race

Unstable state Unstable state

RS latch state diagram

output=Q Qinput=R S

Clocking terms

T su T h

• Clock – Rising edge, falling edge, high level, low level, period

• Setup time: Minimum time before clocking event by which input

must be stable (TSU)

• Hold time: Minimum time after clocking event for which input

must remain stable (TH)

• Window: From setup time to hold time

Gated RS latch

Memory element properties

Type Inputs sampled Outputs valid

Unclocked latch Always LFT

Level-sensitive latch Clock high LFT

(TSU to TH ) around falling clock edge

Edge-triggered flip-flop Clock low-to-high transition Delay from rising edge

(TSU to TH ) around rising clock edge

Clocking conventions

Active-high transparent Active-low transparent

Positive (rising) edge Negative (falling) edge

CLK CLK

Timing for edge and level-sensitive latches

Q edge

Q level

Summary

• Memory

• Latches

• Flip-flops (more on these later)

Reading assignment

Computer security

• PGP

• (Open)SSH

• (Type II) remailers

• Ethereal

• Crack

Today’s topics

• Administrative

• Review: Build a multiplier

• Finite state machines

• Back to latches

• Debouncing

Multiplication

• Already went through this on the blackboard

• Wanted the class to do it together, also want you to have clear

lecture notes on it

• To understand why these trade-offs exist, we need to understand

the fundamentals of arithmetic circuits

• We have already discussed the selection of number systems and

the design of adders/subtracters

• Similar alternatives exist for multipliers

Multiplication

• Multiplication is the repeated application addition of ANDed bits

and shifting (multiplying by two)

• Multiplication is the sum of the products of each bit of one

operand with the other operand

• Consequence: A product has double the width of its operands

Multiplication

Recall that multiplying a number by two shifts it to the left one bit

6 ·3 = 6 · (22 ·0+21 ·1+20 ·1)

= 6 ·22 ·0+6 ·21 ·1+6 ·20 ·1

110 ·011 = 11000 ·0+1100 ·1+110 ·1

= 110+1100

= 10010

Multiplication

A2 A1 A0

× B2 B1 B0

A2B0 A1B0 A0B0

A2B1 A1B1 A0B1

+ A2B2 A1B2 A0B2

sum5 sum4 sum3 sum2 sum1 sum0

Multiplication

Consider multiplying 6 (110) by 3 (011)

× 0 1 1

+ 0 0 0

0 1 0 0 1 0

Multiplier implementation

• Direct implementation of this scheme possible

• Partial products formed with ANDs

• For four bits, 12 adders and 16 gates to form the partial products

– 88 gates

• Note that the maximum height (number of added bits) is equal to

the operand width

Combinational multiplier

A 0 B 0 A 1 B 0 A 0 B 1 A 0 B 2 A 1 B 1 A 2 B 0 A 0 B 3 A 1 B 2 A 2 B 1 A 3 B 0 A 1 B 3 A 2 B 2 A 3 B 1 A 2 B 3 A 3 B 2 A 3 B 3

S 0 S 1

Multiplier building block

S CI CO

Cin Sum In

Sum Out Cout

Combinational multiplier

P2P3P4P5

A2 B0 A1 B0 A0 B0

A0 B1A1 B1A2 B1

A1 B2 A0 B2A2 B2

Sequential multiplier

• Can iteratively one row of adders to carry out multiplications

• Advantage: Area reduced to approximately its square root

• Disadvantage: Takes n clock cycles, where n is the operand bit

2X2 sequential multiplier

co co coco ci ci cicisum sum sumsum

b b bb a a aa

Q QD D

clkclk

clkclkclk

Operands already in registersAdder flip-flops cleared

b b bb a a aa

Q QD DOperands

clkclk

clkclkclk

b b bb a a aa

Q QD DOperands

Could be HA

clkclk

clkclkclk

Arithmetic/logic units

• Possible to implement functional units that can carry out many

arithmetic and logic operations with little additional area or delay

overhead

• Already saw example: Combined adder/subtracter

• Other operations possible

• Could you generalize the approach used for two’s complement

addition and subtraction to another pair of operations?

Arithmetic/logic operations

• Increment

• Addition

• Negation

• Subtraction

• Multiplication

– Slow or large

• Division

– Slow or large

Arithmetic/logic operations

• Shift left

– Fast, multiplication by two

• Shift right

– Fast, division by two

• Bit-wise operations

– AND, OR, NOT, NAND, NOR, XOR, and XNOR

Word description to state diagram

• Design a vending machine controller that will release (output

signal r) an apple as soon as 30¢ have been inserted

• The machine’s sensors will clock your controller when an event

occurs. The machine accepts only dimes (input signal d) and

quarters (input signal q) and does not give change

• When an apple is removed from the open machine, it indicates

this by clocking the controller with an input of d

• The sensors use only a single bit to communicate with the

controller

• We can enumerate the inputs on which an apple should be

released

ddd+ddq+dq+qd+qq

d(dd+dq+q)+q(d+q)

d(d(d+q)+q)+q(d+q)

For d, i = 0, for q, i = 1

0(0(0+1)+1)+1(0+1)

0(0(0 + 1) + 1) + 1(0 + 1)

State diagram to state table

nextcurrent state output (r)state i=0 i=1

A B E 0

B C D 0

C D D 0

D A A 1

E D D 0

Moore block diagram

combinational logic

sequential elements

combinational logic

feedback

inputs

outputs

Mealy block diagram

combinational logic

sequential elements

outputs

inputs

feedback

Moore FSMs

A/0 B/0

Mealy FSMs

0/00/0

1/10/1

Mealy tabular form

A D/0 B/X

B C/1 B/0

C A/0 B/1

D C/1 C/0

FSM design summary

• Specify requirements in natural form

• Manually derive state diagram

– Automatic way to go from English to FSM, however more

theory required

– Can minimize state count, however, more theory also required

– See me if you want more information on this, or take a

compilers course and a graduate-level switching theory

course, or take my ECE 303

• Assign values to states to minimize logic complexity

• Optimize implementation of state and output functions

Back to latches

• Latches: Level sensitive

• Flip-flops: Edge-triggered

Review: Clocking conventions

Active-high transparent Active-low transparent

Positive (rising) edge Negative (falling) edge

CLK CLK

Latch and flip-flop equations

Q+ = S+ R Q

Q+ = D

Latch and flip-flop equations

Q+ = J Q + K Q

Q+ = T ⊕Q

JK latch

R−S latch

replacements

Use output feedback to ensure that RS6= 11

Q+ = Q K + Q J

JK latch

J K Q Q+

0 0 0 0

0 0 1 1 hold

0 1 0 0

0 1 1 0 reset

1 0 0 1

1 0 1 1 set

1 1 0 1

1 1 1 0 toggle

JK race

100 Set Reset Toggle

Race Cond i t ion

Falling edge-triggered D flip-flop

• Use two stages of latches

• When clock is high

– First stage samples input w.o. changing second stage

– Second stage holds value

• When clock goes low

– First stage holds value and sets or resets second stage

– Second stage transmits first stage

• Q+ = D

• One of the most commonly used flip-flops

Clock high

Holds D whenclock goes low

Clock switching

Inputs sampled on falling edge, outputs change after falling edge

Clock low

Another view of an edge-triggered DFF

Edge triggered timing

Positive edge− t riggered FF

Negative edge− t riggered FF

RS clocked latch

• Storage element in narrow width clocked systems

• Dangerous

• Fundamental building block of many flip-flop types

JK flip-flop

• Versatile building block

• Building block for D and T flip-flops

• Has two inputs resulting in increased wiring complexity

• Edge-triggered varieties exist

D flip-flop

• Minimizes input wiring

• Simple to use

• Common choice for basic memory elements in sequential circuits

Debouncing

• Mechanical switches bounce!

• What happens if multiple pulses?

– Mutliple state transitions

• Need to clean up signal

Schmitt triggers

transition

Schmitt triggers

transitionB

Debouncing

-1.0e-03 -5.0e-04 0.0e+00 5.0e-04 1.0e-03 1.5e-03

Schmidt trig.RC

0.751.65

Assigned reading

• Review Sections 6.4 and 6.5

– If FSMs don’t make sense now, please ask questions, or see

– FSMs are tricky at first – Almost everybody has this moment

of epiphany at which they suddenly make sense

• Section 6.6

• Parsers and lexical analyzers

• Writing problem-specific languages

• A. Aho, R. Sethi, and J. Ullman, Compilers principles, techniques,

and tools. Addison-Wesley, Reading, MA, 1986

• Lex and yacc

• Flex and bison

Today’s topics

• Introduction to instruction processors

• RSE processor

• Architecture

• Assembly

• Compilation

• PIC16C74A

Change in style

• Micro-controller based design

• In this lecture, I want a lot of help and participation

• You now have the fundamental knowledge to design a processor

• Let’s build a simple one on paper

• You’ll be programming a slightly more complex processor in next

week’s lab assignment

RSE processor

• Already understand building FSMs

• Can use array of latches to store multiple bits: register

• Consider simple processor, called RSE (Rob’s simplified

example)

RSE registers

• All registers are 8-bit

• Four general-purpose registers, A,B,C, and D

– Used to do computation

• Program counter PC

• Stack pointer SP(sometimes called TOSfor top of stack), which

may also be used as a general-purpose register

• ALU capable of adding (0) and subtracting (1)

RSE arithmetic instructions

• add RD, RS1, RS2

• sub RD, RS1, RS2

Do computation on source registers and put result in destination

register

RSE data motion

• ldm RD, [RS]

– Load from memory location indicated by the source register

into destination register

• stm [RD], RS

– Store to memory location indicated by the destination register

from source register

• ldi RD, I

– Load immediate into destination register

• ldpc RS

– Load from program counter to destination register

Branch instructions

• blz RT , RC

– Set PC to RT if RC < 0

• bz RT , RC

– Set PC to RT if RC = 0

Architecture

Instructionfetch

<0 0MUX

Instruction decode &register fetch

Writeback

Memory

... ALU

Execute

I Decoder

What about memory writes? Immediates?

Instruction encoding

• How many instructions?

• Worst-case operands?

– 3 registers (each how many bits?)

– 1 register and 1 immediate

– To pack or not to pack?

Initialization

• Chip has reset line

• Set PC to byte 2

• Start running. . .

Memory

• Acts like a collection of byte-wide registers

• Address using a decoder

• Can put other devices at some memory locations

– Memory-mapped input-output

• Can also use special-purpose output instructions or registers

• Let’s build some from D flip-flops

• Multiplexing address and data lines?

Program counter

Every clock tick the processor

• Fetches an instruction from the memory location pointed to by PC

• Decodes the instruction

• Fetches the operands

• Executes the instruction

• Stores the results

• Increments the program counter

• Can jump to another code location by moving a value into the PC

Example high-level code

Sum up the contents of memory locations 2-6

1. A = 0

2. For B from 2 to 6

3. A = A+[B]

Example low-level code

Sum up the contents of memory locations 2–6

2. A = 0 ldi A, 0 or sub A, A, A

4. B = 2 ldi B, 2

6. C = [B] (loop start point) ldm C, [B]

8. A = A+C add A, A, C

10. B = B+1 ldi C, 1 — add B, B, C

14. C = 6 (loop start) ldi C, 6

16. If B≤ 6 (B < 7) branch to C ldi D, 7 — sub D, B, D — blz C, D

(Done)

4. B = 2 ldi B, 2

10. B = B+1 ldi C, 1 — add B, B, C

(Done)

4. B = 2 ldi B, 2

10. B = B+1 ldi C, 1 — add B, B, C

(Done)

4. B = 2 ldi B, 2

10. B = B+1 ldi C, 1 — add B, B, C

(Done)

4. B = 2 ldi B, 2

10. B = B+1 ldi C, 1 — add B, B, C

(Done)

4. B = 2 ldi B, 2

10. B = B+1 ldi C, 1 — add B, B, C

(Done)

4. B = 2 ldi B, 2

10. B = B+1 ldi C, 1 — add B, B, C

(Done)

4. B = 2 ldi B, 2

10. B = B+1 ldi C, 1 — add B, B, C

(Done)

Error conditions

• What happens on overflow or underflow?

• Special register?

• Special value associated with each register?

• Single-instruction compare and branch?

• Advantages and disadvantages of each?

Assemble to our encodings

• After assembling, can put program contents into memory, starting

at byte 2

• Compiling from higher-level languages also possible

Example high-level code

Sum up the contents of memory locations 2-6

1. i = 0

2. For j from 2 to 6

3. i = i +[ j]

Lesson

• With only a few registers and instructions, powerful actions are

possible

• Less time and power efficient than special-purpose hardware

design

• Instruction processors are flexible

• Allows massive use of a single type of IC

• Assembly is painful

• However, much better than doing hardware design

• Compilation also possible

Today’s topics

• Architecture

• Assembly

• Compilation

• PIC16C74A

Assigned reading

• Sections 7.1-7.9

• Read this and treat it as a reference for Chapter 10

• Note that, although they treat counters as special devices, they

are really just FSMs without (or with few) inputs

• You can understand almost everything in the context of

combinational networks and FSMs

• Chapter 7 is a catalog and cookbook

Assigned reading

• Section 8.7

• Chapter 10

• Building multicontroller-based devices for the fun of it

• http://www.bdmicro.com

• http://www.commlinx.com.au/microcontroller.htm

• http://members.home.nl/bzijlstra/

• http://www.robotcafe.com/dir/Companies/Hobby/more3.shtml

• Etc.

• Use two stages of latches

• When clock is high

– First stage samples input w.o. changing second stage

– Second stage holds value

• When clock goes low

– First stage holds value and sets or resets second stage

– Second stage transmits first stage

• Q+ = D

• One of the most commonly used flip-flops

Clock high

Holds D whenclock goes low

Clock switching

Inputs sampled on falling edge, outputs change after falling edge

Clock low

Today’s topics

• Goals

• Future closely related courses

• Resources

• Quick summary of topics

• Review

• Did you learn how to design, implement, and debug reasonably

efficient digital hardware and assembly language programs that

do useful things?

• Do you understand how hardware and software relate to each

other?

• Do you feel like you accomplished something worthwhile?

– I hope so – You did!

• Could you teach yourself (using books and experimentation) new

things related to the topics that were introduced in the class?

– I hope so, but there are also other classes that will accelerate

things

Future closely related courses

ECE 303: Advanced Digital Logic Design

• Robert Dick or Seda Ogrenci Memik

• Hardware design

• Manual and automatic

• Deeper theory

• Labs go beyond ECE 203, but so does the power of the theory

and software tools

• ECE 225: Fundamentals of Electronics

– More on details on circuit implementation, analog circuits

• ECE 361/362: Computer Architecture

– Efficient ways to combine the building blocks you learned

about in ECE 203 into working computers

• ECE 391/392: VLSI Systems Design

– Low-level analysis and design of complex digital systems

• ECE 360: Introduction to Feedback Systems

– Control, e.g., the car lab

• ECE 230/231, CS 211: Programming for Computer Engineers

– High-level languages

• ECE 205: Fundamentals of Computer System Software

– Assembly language

• CS 346: Design and Analysis of Algorithms

– Foundation for programming, automation

• ECE 357: Introduction to VLSI CAD

– Algorithms for physical design automation of digital circuits

• CS 322: Compiler Construction

– Closely related to FSMs, allows automation of FSM

implementation

• CS 343: Operating Systems

– Managing complexity in software systems, even on

µ-controllers

• Finding the right books can be difficult

• Stop by my office to see if these have what you’re searching for

• A. Aho, R. Sethi, and J. Ullman, Compilers principles, techniques,

and tools. Addison-Wesley, Reading, MA, 1986

• T. H. Cormen, C. E. Leiserson, and R. L. Rivest, Introduction to

Algorithms. McGraw-Hill Book Company, NY, 1990

• M. R. Garey and D. S. Johnson, Computers and Intractability: A

Guide to the Theory of NP-Completeness. W. H. Freeman &

Company, NY, 1979

• J. Hennessy and D. Patterson, Computer Architecture: A

Quantitative Approach. Morgan Kaufmann Publishers, CA, 1995

• P. Horowitz and W. Hill, The Art of Electronics. Cambridge

University Press, 1989

• Z. Kohavi, Switching and Finite Automata Theory. McGraw-Hill

Book Company, NY, 1978

• D. Lancaster, TTL Cookbook. Howard W. Sams & Co., Inc., 1974

• D. Lancaster, CMOS Cookbook. Howard W. Sams & Co., Inc.,

• B. G. Streetman, Solid State Electronic Devices. Prentice-Hall,

Englewood Cliffs, NJ, 1990

Quick summary of topics

• Switches

• PMOS and NMOS transistors

• Using TTL

• Logic gates

• Transmission gates

• Two-level minimization

• Multiplexers, demultiplexers, encoders, decoders

Quick summary of topics

• Computer arithmetic

• Latches and flip-flops

• Mealy and Moore finite state machine synthesis

• Number systems

• Base conversion

• Microcontroller assembly language

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