Interconnect and Packaging

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Interconnect and Packaging

Lecture 8: Clock Meshes and Shunts

Chung-Kuan ChengUC San Diego

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I. Clock Meshes

• In Engineering practice, very deep balanced buffer tree + mesh is widely adopted for global clock distribution• IBM Power 4: 64 by 64 grid at the bottom of an H-

tree• Intel IA: clock stripe at the bottom of a buffer tree.

• “Skew Averaging”: shunt at different levels

• “Skew Averaging Factor” determined by simulation. No guideline for routing resource planning known yet

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I. Clock Mesh Example (1)

• DEC Alpha 21264

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I. Clock Mesh Example (2)

• IBM Power4• H-tree drives one domain clock mesh• 8x8 area buffers

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I. Clock Mesh Example (3)

• Intel Pentium 4• Tree drives three spines

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II. Multi-level mesh structure

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II. Linear Variations Model

• Process variation model• Transistor length• Wire width• Linear variation model

• Power variation model• Supply voltage varies randomly (10%)

ykxkdd yx 0

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II. Simplified Circuit Model

Vs1Rs

C

Vs2Rs

C

R

1

2

u(t)

u(t-T)

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II. Transient Response when t<T

VS1=u(t)

Vs2=0

Let

))1

exp(1(2

1t

CRA

s

))21

exp(1()21(2

1t

CRR

R

R

RB

s

s

s

Then

V1 = A + B

V2 = A - B

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II. Transient Response when t>T

Let:

)1(exp)21(2

1

)1(exp2

1

21

2

1

1

TCRR

R

s

TCR

s

s

s

RR

K

K

tCRR

R

tCR

s

s

s

KB

KA21

2

1

1

exp

exp1

then

BAV

BAV

2

1

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II. Skew Expression

110 2ln CRt

)(2

1.

2

21.

1

21

V

VV

V

VVT

Assumptions:

1. T<<RsC

2. Rs /R <<RsC/T

Using first order

Taylor expansion ex=1+x,

)2ln2exp(

:function Skew

R

RTT s

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II. Spice Validation of Skew Function

)2ln2exp(R

RTT s

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II. Skew on mesh

• Conjectured skew expression

• Using regression to get k

)/exp( RkRTT s

Vs11

R1

R

VSNN

VS1N

VSN1

C1

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II. K values for n by n meshes

mesh size 2 by 2 4 by 4 8 by 8 16 by 16k 1.167 0.363 0.107 0.030

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II. Optimization

• Skew function

• Multi level skew function

)/exp( RkRTT s

)'exp()'exp( wkTwRkTT s

Awl

eTTeTeTTn

iii

wkn

wkwk nn

1

321

:s.t.

))...))((( :Min 2211

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• Die size 1cm by 1cm• 100nm copper technology• Ground Shielded Differential Signal

Wires for Global Clock Distribution

• Routing area is normalized to the area of a 16 by 16 mesh with minimal wire width

III. Experimental Settings

+ -

GND

GND

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III. Experimental Results

• Optimized wire width

1st 2nd 3rd 4th0.25 1.23 0.98 0.00 0.000.40 1.23 1.85 0.00 0.001.00 1.23 1.88 1.27 0.003.00 1.23 1.88 2.56 1.405.00 1.23 1.89 2.56 3.40

optimized wire width of each level meshtotal area

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III. Optimal Routing Resources Allocation

level-1

level-2

level-3

level-4

total area

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III. Skew reduction V.S. Mesh Area

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III. Experiments—Optimized Skew

s-mesh(s) m-mesh(s) ratio0.00 2.92E-11 2.92E-11 100.0%0.25 2.79E-11 2.60E-11 93.2%0.40 2.71E-11 2.45E-11 90.4%1.00 2.42E-11 1.98E-11 81.8%3.00 1.70E-11 1.24E-11 73.2%5.00 1.24E-11 8.72E-12 70.5%

skewtotal area

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III. Delay Surfaces

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III. Robustness Against Supply Voltage Variations

ave worst ave worst0.00 2.10E-11 2.91E-11 2.10E-11 2.91E-111.00 8.38E-12 1.14E-11 8.26E-12 1.43E-112.00 2.71E-12 4.42E-12 6.18E-12 1.11E-113.00 1.89E-12 3.33E-12 4.83E-12 8.73E-124.00 1.45E-12 2.48E-12 3.88E-12 6.96E-125.00 1.16E-12 2.02E-12 3.18E-12 5.64E-12

total areamutli-level mesh single-level mesh

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III. Inductance Considerations

• Delay error between RC and RLC will not exceed 15 % under following conditions:• CL >> C

• R/Z0 > 2

• R1 > nZ0(n is between 0.5 and 1.0)

(In our network, working at 4G, Z0=339ohm

R1=367ohm, R=5130ohm, Cl=149.4fF, and C=14.3fF)

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IV. Simulation Results with inductance

total area w/o L w/ L error1.00 1.98E-11 2.00E-11 0.7%3.00 1.24E-11 1.27E-11 2.2%

Without L With L

Spice simulation results at 4GHz

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IV. Inductance Diminishes Shunt Effects

Vs1 Rs

C

Vs2 Rs

C

R

1

2

u(t)

u(t-T)

L

f(GHz) 0.5 1 1.5 2 3 3.5 4 5

skew(ps) 3.9 4.2 5.8 7.5 9.9 13 17 26

• 0.5um wide 1.2 cm long copper wire

• Input skew 20ps