Housekeeping 1.teams—end of class 2.Example verilog code (alter) 3.Example altera report 4.Lab...

Housekeeping

1. teams—end of class

2. Example verilog code (alter)

3. Example altera report

4. Lab Monday: you will be asked to show:-- one or more reports

--one or more verilog modules

--one or more simulation

Processors (ISA, RTL levels); Instruction cycle;

interruptsComputer Processor Basics

ISA (Instruction Set Architecture)

RTL (Register Transfer Language)

Main references:

Peckol, Chapters 1-3

Patt and Patel, Introduction to Computing Systems (slides from NC State)

Fig. 01-00

“Machine” categories• FSM

• Stack machine

• Turing machine– von Neumann architecture– Harvard architecture

program and data share one memory

Von Neumann memoryHarvard memory: separation of program, data

program data

1. fsm--"finite state machine"--states, input, output; transition from one state to the next is a function of current state or current state + input. Machine does not "remember" where it has been previously--you cannot look back at where you have been. 2 basic types:

Moore machine: output from state machine is in Mealey machine: output based on state you are in and input Examples: vending machine, control unit, counter, traffic light.

0 0,1 1 1 START 0 Can be realized by flip-flops and combinational logic (and I/O). Theory: FSM regular languages

A B

C

2. stack machine--states, input, output, stack(LIFO). We can use the stack to "remember"some past actions.

Examples: parse expressions for grammar;evaluate arithmetic expressions.

Example: to evaluate AB+C* (= (A+B)*C)weperform the operations:Push A; push B; pop, pop, add and push; pushC; pop,pop, multiply and push; output result(end of input string). A simple fsm cannot dogeneral examples of this type of calculation.We need flip-flops, combinational logic, and thestack.

Theory: stack machine context-free languages stack machines are "more powerful" than

fsm's (e.g., using a stack we can write aprogram to recognize palindromes of the formAnBn,n>0. A fsm would need an infinite number of states to do this task.)

Control (fsm)

“Top”

Stack

Popped Item

(from “Top”)

Combinational Logic

I/O

3. Turing machine or "random access machine" or sequential computer--this in turn is more general than the stack machine. It can be realized by flip-flops, combinational logic, and a "random access memory" in which each memory location can be accessed through its unique address: (solid arrows represent control flow; dotted arrows represent data flow).(Sometimes called a Single Instruction Single Data or SISD machine). Theory: "UTM": Universal Turing Machine--can execute any algorithm, model any classical computer Turing machine recursively enumerable languages Two basic configurations: Von Neumann: store data + program together Harvard: store data, program in separate memories

CONTROL

(FSM)

I/O RAM ALU (comb)

(Actual “RAM” Hierarchy)

Registers

Cache

Main Memory (RAM)

(Virtual Storage)

{Hard Disk, Secondary Devices}

fig_01_05

Some processor options(note firmware)

DSP (A/D, D/A; high speed—video, audio, images

2. Microcontroller-based system Fig. 1-05 components integrated into one unit)

1. Microprocessor-based system

fig_01_06

fig_01_07

Instruction Set Architecture•ISA = All of the programmer-visible components and operations of the computer

– memory organization• address space -- how may locations can be addressed?• addressibility -- how many bits per location?

– register set• how many? what size? how are they used?

– instruction set• opcodes• data types• addressing modes

•ISA provides all information needed for someone that wants towrite a program in machine language (or translate from a high-level language to machine language).

Example 1:LC-3 (Patt) Overview: Memory and Registers

•Memory– address space: 216 locations (16-bit addresses)– addressability: 16 bits

•Registers

– temporary storage, accessed in a single machine cycle

• accessing memory generally takes longer than a single cycle

– eight general-purpose registers: R0 - R7

• each 16 bits wide

• how many bits to uniquely identify a register?

– other registers

• not directly addressable, but used by (and affected by) instructions

• PC (program counter), condition codes

LC-3 Overview: Instruction Set

•Opcodes– 15 opcodes– Operate instructions: ADD, AND, NOT– Data movement instructions: LD, LDI, LDR, LEA, ST, STR, STI– Control instructions: BR, JSR/JSRR, JMP, RTI, TRAP– some opcodes set/clear condition codes, based on result:

• N = negative, Z = zero, P = positive (> 0)•Data Types

– 16-bit 2’s complement integer: (q: how does 2’s c arithmetic work?)•Addressing Modes

– How is the location of an operand specified?– non-memory addresses: immediate, register– memory addresses: PC-relative, indirect, base+offset

Example: NOT (Register)

Note: Src and Dstcould be the same register.

Example: ADD/AND (Register)this zero means “register mode”

fig_01_08

DATA: DATA TYPES

NUMERIC--Unsigned integer

--Signed integer (2’s complement, sign-magnitude, fixed point, etc.)

--Floating point:3 components:

signexponentmantissa

NONNUMERIC--address

--character

Q: what common data type is not named? Is it “missing”?

Instructions—ISA level

Instruction coding:

HLL (high level language, C, C++ , e.g.)

assembly language (ISA)

machine language

(can work at any level; high level allows faster but less efficient coding)

IEEE Standard 694-1985—IEEE standard for microprocessor assembly language—used for examples in text

Instruction coding:

Fields: operator, operands (type of addressing)

Example: 32 bits

3 bits: opcode

2 bits: address mode (e.g. direct, indirect, indexed, immediate)

27 bits: for addressing operand (s)

Expanding opcode (example):

000-110xxxx…xxx: 2 operands

1110xxx…xxx: 1 operand

1111xxx…xxx: no operand (e.g., HALT)

operator addr mode operand(s)

fig_01_13fig_01_14

fig_01_15

Example instruction formats

fig_01_42

Typical ALU and

registers

fig_01_16

Data movement instructions: source / destination

fig_01_12

Addressing modes:

Immediate: MOVE A, #BH;

Direct: MOVE OPR1, OPR2;

Indirect: MOVE OPR1, *myVarPtr;

MOVE *OPR1, *OPR1;

MOVE *OPR1, **yPtr;

Register direct: MOVE Reg1, Reg2;

Register indirect: MOVE Reg1, *Reg2;

Indexed (loops): MOVE Reg1, OPR2[REG2];

PC relative (loops,e.g.; offset can be negative):

ADD PC, [Reg1];

Example: what is the difference between Y, *Y, **Y

Indirect addressing—myVarPtr holds address or myVar

fig_01_21

Addressing examples:

fig_01_22

fig_01_23

fig_01_24

Control instructions

Control can be:

sequential (default)

loop (pre or posttest)

branch:

go to

conditional (if, if-else,, case, branch on condition)

procedure or function call

[interrupt or exception]

change in control flow, e.g., I/O device ready

Unusual event, e.g., overflow or undefined instruction

fig_01_31

Example of conditional statements: C / assembly language:

fig_01_32

fig_01_34

Looping: example

fig_01_35

fig_01_36

fig_01_37

Function or procedure call:

Must store return address, pass information back and forth

What are standard parameter passing methods?

fig_01_39

Stack: common way to handle procedure / function calls

Q: what are two alternative methods for handling function / procedure calls? Which methods facilitate recursion?

fig_01_40

Function call: example:

fig_01_41

LC-3 Data Path

Filled arrow = info to be processed.

Unfilled arrow= control signal.

Instruction Processing Cycle

Decode instructionDecode instruction

Evaluate addressEvaluate address

Fetch operands from memoryFetch operands from memory

Execute operationExecute operation

Store resultStore result

Fetch instruction from memoryFetch instruction from memory Q: what about interrupts?

fig_01_46

Different viewpoint:

RTL: register-transfer language level

fig_01_52

RTL VIEW

fig_01_53

fig_01_57

Multiple levels--examples

fig_01_58

table_01_03

ALU

MMA

IR AC CF MD IA IB PC

ABUS

OBUS

BBUS

ALU OUTPUT

M: memoryMA: memory address registerMD: memory data registerIR: instruction registerAC: accumulatorCF: carry flagIA, IB: index registers (13 bit)PC: program counter

Instruction format:

Op code (3)

Addr Mode (2)

Address (13)

Functionality: 2's complement add, subtract, multiply, and divide, and, or, not jumps (conditional and unconditional), simple subroutine call and returnInterruptsI/O

Ex 2: Minimal hardware resources high degree of functionality

What should instructions be?