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High-speed Serial Interface
Lect. 4 – Channel Equalizer: Linear Equalizer
2013-1High-Speed Circuits and Systems Lab., Yonsei University1
Block diagram
2013-1High-Speed Circuits and Systems Lab., Yonsei University2
Serializer TxDriver Sampler
ClockRecovery
Deserializer
PLL
Channel
Tx Rx
• Where are we today?
RxEqualizer
Why equalize channel?• Channel causes ISI on received signal.
– Frequency-dependent High-loss in channel eye closure
2013-1High-Speed Circuits and Systems Lab., Yonsei University3
TxDriver Channel Rx
SamplerRx
Equalizer
Linear Equalizer• The purpose of linear equalizer
– To extend bandwidth by cancelling 1st pole in the channel
2013-1High-Speed Circuits and Systems Lab., Yonsei University4
Gain [dB]
Frequency (log)
0
ADC,EQ
fBW
-3
fBW,EQ
ADC,EQ-3
Transfer function• Desired frequency response
– 1 zero and 2 poles
2013-1High-Speed Circuits and Systems Lab., Yonsei University5
Gain [dB]
Frequency (log)
ADC,EQ
fz fp1
AAC,EQ
fp2
High frequency boosting
Controllability• Linear equalizer should have controllability
– Channel variation• Variations in channel fabrication • Uncertainty in channel modeling• Channel degradation/defect after usage
– PVT variation for equalizer
Automatic adaptation desired
2013-1High-Speed Circuits and Systems Lab., Yonsei University6
Controllability• Tuning location of pole/zero
2013-1High-Speed Circuits and Systems Lab., Yonsei University7
Gain [dB]
Frequency (log)
TuningZero location
FixedADC,EQ
ControllingAAC,EQ
Controllability• Tuning DC gain
2013-1High-Speed Circuits and Systems Lab., Yonsei University8
Gain [dB]
Frequency (log)
TuningDC gain
ControllingADC,EQ
FixedAAC,EQ
Implementation #1• Passive equalization
– Linear equalizer is basically high-pass filter.– Various forms of passive filters are available.
2013-1High-Speed Circuits and Systems Lab., Yonsei University9
R1
C1
OUTIN
R2 C2
COUTIN
R
Implementation #1• Passive equalization
☺ Pros: No power consumption☻ Cons: - Lossy- PVT dependent- Difficult to achieve 50-ohm matching- Difficult to tune- Often large size
2013-1High-Speed Circuits and Systems Lab., Yonsei University10
R1
C1
OUTIN
R2 C2
COUTIN
R
Implementation #2• Differential amplifier
– Basic differential amp. has 1 pole from load capacitance.
2013-1High-Speed Circuits and Systems Lab., Yonsei University11
VDD
VSS
OUT-
IN+
OUT+
IN-
Ibias
Zload Zload
gm gm~ // 1
Cload Cload
= + 1
Implementation #2• Inductive load
– Shunt peaking of inductoroffers additional pole zero pair
2013-1High-Speed Circuits and Systems Lab., Yonsei University12
VSS
OUT-
IN+
OUT+
IN-
Ibias
Rload Rload
gm gm
Cload Cload
Lload Lload
~ // 1VDD
= ( + )+ + 1= + 1+
Implementation #2• Inductive load☺ Pros- Gain of amp can be fully utilized.- Input matching is easily doneby 50-ohm resistor
☻ Cons- On-chip inductor is difficult to realize and very large
2013-1High-Speed Circuits and Systems Lab., Yonsei University13
VSS
OUT-
IN+
OUT+
IN-
Ibias
Rload Rload
gm gm
Cload Cload
Lload Lload
VDD
Implementation #3• Source degeneration
– Source degeneration is commonly used to enhance linearity at the cost of DC gain
2013-1High-Speed Circuits and Systems Lab., Yonsei University14
VDD
VSS
OUT-
IN+
OUT+
IN-
Ibias/2
Zload Zload
gm gm
Cload CloadIbias/2
Zdeg
= ′ // 1= 1 + 2 // 1
Implementation #3• Source degeneration
– Capacitive generation provides high-frequency boosting since capacitor is short at high frequency.
2013-1High-Speed Circuits and Systems Lab., Yonsei University15
VDD
VSS
OUT-
IN+
OUT+
IN-
Ibias/2
Zload Zload
gm gm
Cload CloadIbias/2
Rdeg
Cdeg
= 1 + 2 // 1= + 1
+ 1 + 2 + 1
Implementation #3• Source degeneration☺ Pros- Capacitor is not very large- Input matching is easily doneby 50-ohm resistor
☻ Cons- DC gain of amp is degraded byresistive degeneration
2013-1High-Speed Circuits and Systems Lab., Yonsei University16
VDD
VSS
OUT-
IN+
OUT+
IN-
Ibias/2
Zload Zload
gm gm
Cload CloadIbias/2
Rdeg
Cdeg
Implementation #4• Combining filter☺ Pros- Input matching is easily done by 50-ohm resistor- Easy to control amount of boosting and pole-zero location
☻ Cons- Delay mismatch between high- and low frequency path causes non-linear Distortion.
2013-1High-Speed Circuits and Systems Lab., Yonsei University17
OUT
IN
HighPassFilter
Implementation #4• Combining filter
– High-frequency component has additional gain stage– Each block in the diagram can be implemented in various forms.
• Ex) summing block: current addergain stages: differential pairhigh-pass filter: source degeneration
2013-1High-Speed Circuits and Systems Lab., Yonsei University18
OUT
IN
HighPassFilter
Limit of LE• Complex poles and zeros in channel
– Only simple pole/zero configuration is perfectly compensated.
2013-1High-Speed Circuits and Systems Lab., Yonsei University19
Gain [dB]
Frequency (log)
Additional zero
Additional pole
Limit of LE• LE cannot compensate non-linear distortions
– Linear equalization is just frequency domain filtering
– Applicable to only ISI from linear frequency-dependent loss• This is the main ISI component in HSI applications
– Other causes for ISI are;• Impedance mismatching• Differential offset• Cross-talk• Parasitic poles and zeros (ex: package parasitic)
2013-1High-Speed Circuits and Systems Lab., Yonsei University20
Limit of LE• Noise boosting
– LE is basically high-pass filter, so high-frequency noise are also boosted.
2013-1High-Speed Circuits and Systems Lab., Yonsei University21
Gain [dB]
White noise
Design example
2013-1High-Speed Circuits and Systems Lab., Yonsei University22
EqualizerOutputBuffer
300㎛
450㎛
“A 2-Gbps CMOS Adaptive Line Equalizer”Jae-Wook Lee, Bhum-Cheol Lee*, and Woo-Young Choi
AP-ASIC 2004
Combining filter and zero-forcing adaptation0.25㎛ CMOS technology
TQFP 80 pin package45mW dissipation @2.5V power supply
Test board
Design example
2013-1High-Speed Circuits and Systems Lab., Yonsei University23
0 1 2 3 4
-20
-15
-10
-5
0
(width = 5mil, height = 1.4mil)PCB trace
length = 2m
length = 1.5m
length = 1m
length = 0.5m
Gai
n(dB
)Frequency(GHz)
PCB trace : about 10dB loss @2Gbps / 2m length
HSPICE W-model simulation (strip line)
Er = 4.5, Loss tangent = 0.02 (FR4)
1.4
5
168
unit : mil
Design example• Block diagram
– Linear equalizer employing combined filter– Adaptation block: Limiting amp., square difference, V-I converter– Limiting amplifier removes analog information, therefore, only
timing information can be externally observed.
2013-1High-Speed Circuits and Systems Lab., Yonsei University24
CombiningLinearEqualizer
LimitingAmplifier
OutputDriver
SquareDifference
V-IConverter
OUTIN
Design example
2013-1High-Speed Circuits and Systems Lab., Yonsei University25
InputSignal
Input buffer
VGA
HPF
Equalizer input stage
Control Voltage
from bias circuit
output data
input data 1
Variable Gaincontrol
Load
VGAinput buffer
input data 2
Gain control
Design example
2013-1High-Speed Circuits and Systems Lab., Yonsei University26
Pattern Generator
PCB length = 60cm
Equalizer
X scale : 100ps / divY scale : 100mV / div
PCB length = 60cm
Design example
2013-1High-Speed Circuits and Systems Lab., Yonsei University27
Pattern Generator
PCB length = 150cm
Equalizer
X scale : 100ps / divY scale : 100mV / div
PCB length = 150cm
Design example
2013-1High-Speed Circuits and Systems Lab., Yonsei University28
Pattern Generator
PCB length = 200cm
Equalizer
X scale : 100ps / divY scale : 100mV / div
PCB length = 200cm
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