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Glitch Works 8085 SBC rev 3GW-8085SBC-3
User’s Manual and Assembly Guide
Revision 1, 2018-06-30
c©2018 The Glitch Workshttp://www.glitchwrks.com/
This manual is licensed under aCreative Commons “Attribution-NonCommercial-ShareAlike 4.0” license.
Contents
1 Introduction 2
2 Configuration 22.1 Configuring I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32.2 ROM Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32.3 Interrupt Jumpering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32.4 Glitchbus Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3 Assembly 43.1 Assembling the 8085 SBC rev 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43.2 Assembly Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53.3 Insert Socketed ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63.4 Solder Console Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 Initial Checkout and Testing 74.1 Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74.2 Repair and Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5 Technical Notes 85.1 Board Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85.2 Board Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85.3 Default Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95.4 Default I/O Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6 Errata and Clarifications 106.1 Resistor Pack Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106.2 ROM Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
7 Parts List 11
Assembly Drawing 13
Schematics 14
1
1 Introduction
The Glitch Works 8085 SBC rev 3 (GW-8085SBC-3) is a single-board computer based on the Intel8085 CPU. It includes the following features:
• Intel 8085 CPU at 2 MHz (guaranteed operation, overclocking possible)• 64 KB static RAM, FeRAM compatible• 32 KB ROM, EEPROM, or FeRAM in 4K pages, in-board programmable• Serial console via Intel 8251A USART• USART clock independent of system clock• Software controlled power-on jump• ROM paging and switch-out• Debounced reset and power supply supervisory circuit• Glitchbus expansion header
The 8085 SBC rev 3, when paired with GWMON, is a self-contained system needing only a serialterminal (or teminal emulation software on a PC) for full operation. GWMON for the 8085 SBCrev 3 includes Glitch Works ROM-FS, which allows for the storage of file records in ROM. Theserecords can be loaded from the monitor, or automatically selected by option switches on reset/power-up. This also allows for in-board updates to GWMON without overwriting the current, known-goodcopy.
2 Configuration
The 8085 SBC rev 3 includes a number of jumpers and switch packs for configuring system op-tions:
Name Function
J1 ROM Boot, 1-2 disables ROM boot, 2-3 enables ROM bootJ2 ROM Enabled, 1-2 disables ROM on reset, 2-3 enables ROM on resetJ5 Console USART Bitrate, jumper one position only for printed speed
SW2 I/O Port Block Base AddressSW3 ROM Base Address, Write Protect, and Boot Page Address
For normal operation with standard GWMON ROM images, J1 and J2 should both be set 2-3, SW2should be all open, SW3 1-4 should be closed, and SW3 5-8 should be open. This places the I/O blockat 0x00 - 0x03, ROM at 0xF000 - 0xFFFF, and enables jump to ROM on reset and power-up.
Console bitrate is selected with J5. The board’s silkscreen shows each position’s speed. Only onespeed may be selected. Note that the silkscreen legend will be incorrect if anything other than a2.4576 MHz crystal is used at Y2.
2
2.1 Configuring I/O
The addresses of the USART registers, the board status register, and the board control register arecontrolled by switch pack SW2. In a default configuration, SW2 is set to all open and places theI/O base at 0x00 - 0x03. The base I/O block may be re-addressed on any four-byte boundary inaddress space for use with other software.
2.2 ROM Options
ROM configuration on the 8085 SBC rev 3 is flexible. ROM is addressed in 4K pages, using theROM base set on SW3 and three bits from the board control register. The board control register issoftware programmable, and is reset to 0x00 at reset and power-on.
A pair of D-type flip-flops allows switching the ROM on or off under software control, as well asmapping ROM to 0x0000 for booting. The default states for these flip-flops are controlled by jumpersJ1 and J2. J1 controls remapping to 0x0000 for booting: place its shunt from 1-2 to disable ROMboot, or from 2-3 to enable ROM boot. J2 controls whether the ROM is enabled or disabled at reset.Place its shunt from 1-2 to disable ROM at reset, or from 2-3 to enable ROM at reset. Note thatROM must be enabled at reset for ROM boot to work (both J1 and J2 must be strapped for 2-3).
2.3 Interrupt Jumpering
The five hardware interrupt lines of the Intel 8085 are pulled down to an inactive state with 4.7 kΩresistors. While they are not used by the default Glitch Works software package, they are availablefor use. Additionally, the *BINT line from the Glitchbus expansion header is inverted and brought toTP1, INTERRUPT. It may be jumpered to any of the five available hardware interrupts. Consult theschematic for further details.
2.4 Glitchbus Expansion
The 8085 SBC rev 3 is expandable through a Glitchbus expansion header. The Glitchbus is a generic8-bit bus intended to be processor-agnostic. We plan on offering many expansion boards that utilizethis bus design. As implemented on the 8085 SBC rev 3, the Glitchbus is designed to stack abovethe SBC using PC/104 style stacking headers.
Do note that some of the status and control lines are not fully buffered on the 8085 SBC rev 3 andare subject to loading limitations.
The 8085 SBC’s Glitchbus expansion header is not compatible with previous expansion boards designedfor past revisions of the Glitch Works 8085 SBC. Previous boards will not work with the 8085 SBCrev 3 – use only Glitchbus compatible expansion boards! Previous boards are of a different physicalsize and should be fairly hard to get mixed up with Glitchbus boards.
3
3 Assembly
The 8085 SBC rev 3 is designed to be easy to assemble for anyone with moderate soldering ability.It is a moderately complex board and will typically require between one and three hours of assemblytime, depending on the skill of the assembler. The following tools will be required:
• Soldering iron, 20-40 W recommended, grounded tip• Solder, 63/37 leaded solder recommended, Kester “44 Core” or similar• Diagonal cutters or flush cutters• Solder braid, solder sucker, or desoldering station, in the event errors are made• Needle-nose pilers for bending component leads• 1/4 and 1/8 W resistor lead forms (optional)
This manual does not cover basic soldering technique. If you are new to soldering, we recommend theAdafruit soldering guide and plenty of practice on a piece of protoboard, before beginning assemblyof the 8085 SBC rev 3. The Adafruit guide can be found at:
https://learn.adafruit.com/adafruit-guide-excellent-soldering
3.1 Assembling the 8085 SBC rev 3
If you purchased a full Glitch Works parts kit, we recommend completing all assembly sections, sinceextra features can be disabled as needed. If supplying your own parts, you may choose which sectionsto complete based on the functionality required.
Note that pin 1 is designated with a square pad for all ICs, resistor packs, switches, and mostconnectors. Pin 1 is toward the top of the board, as seen from the front, for all ICs, diodes, resistorpacks, and switches. The component (front) side of the board is the side which contains the whitesilkscreen legend. It is recommended to install components from shortest to tallest, which makesassembly without an assembly vise or jig easier, assuming the board is flipped over and soldered withthe component side resting on a table top.
All jumper headers and connector headers are press-fit and may require a bit of force or gentlewiggling to install. This is normal and helps keep the headers in place when the board is flipped overfor soldering.
4
3.2 Assembly Checklist
Verify parts list against kit contents or builder-provided parts
Consult the assembly drawing for component locations and values
Bend all 0.01 µF bypass capacitors (yellow axial bead) – position 2 on a 1/8 W lead form
Install all 0.01 µF capacitors in positions marked C in assembly diagram
Hairpin bend three 4.7 kΩ resistors and set aside
Bend remaining 4.7 kΩ resistors and install in their marked locations – position 1 on a 1/4 Wlead form
Bend all 330 Ω resistors and install in their marked locations – position 1 on a 1/4 W lead form
Install non-socketed DIP ICs at their marked locations. Do not install U9, U15, U16, U17,U19, or U21
Install a 16-pin socket at U21
Install 28-pin sockets at U15, U16, U17, and U19
Install a 40-pin socket at U9
Install 22 µF 10V capacitors at C8 and C17, bend leads with needle-node pliers
Install micro tact pushbutton at SW1
Install 20 pF radial ceramic capacitor at C9
Install 10 nF radial ceramic capacitors at C1, C16
Install resistor packs at RP1, RP2
Install DIP switches at SW2, SW3
Install five 22 µF 16 V radial electrolytic capacitors at C25 - C29
Install TO-92 DS1233 at U1
Hairpin bend all 1 kΩ resistors and install at R21, R22
Install three previously hairpinned 4.7 kΩ resistors at R3, R4, R20
Install three LEDs at D1, D2, D3
Break the 22-pin pin header strip into two 8-pin sections and two 3-pin sections
Install two 3-pin header sections at J1, J2
Install two 8-pin header sections next to one another at J5
Install 4 MHz CPU clock crystal at Y1
Install 2.4576 MHz serial clock crystal at Y2
5
3.3 Insert Socketed ICs
Insert SRAM into sockets at U15, U16
Insert 8085 CPU into socket at U9
Insert 28C256 EEPROM into socket at U17
Insert 8251A USART into socket at U19
Insert MAX232 level shifter into socket at U21
3.4 Solder Console Cable
Glitch Works parts kits include a DB25F connector for the 8085 SBC rev 3 console cable, as well as aone-foot pigtail terminated in a 5-pin Molex KK-100 connector. This pigtail connects to J6, RS-232CONSOLE. Use the following table to build a console cable appropriate to your intended terminal:
J6 Pin DB25F DCE Pin DB25F DTE Pin Function
1 5 4 Request to Send2 3 2 Transmit Data3 2 3 Receive Data4 4 5 Clear to Send5 7 7 Signal Ground
J6 pin 4, CTS must be asserted for the console USART to transmit data. RTS may be left unconnectedif hardware handshaking is not desired. Console pigtails provided with Glitch Works parts kits omitpin 1, RTS.
A serial light box will help debug potential serial wiring problems, we highly recommend the additionof a light box to your toolkit if you regularly interface RS-232 equipment. Our personal favorite isthe IQ Technologies SmartCable SC821 Plus.
6
4 Initial Checkout and Testing
Once the 8085 SBC rev 3 is assembled, configure it as described in the “Configuration” section,starting on Page 2. Make sure that RPA2 - RPA0 (SW2, positions 6-8) are all open.
Double-check all ICs for proper orientation, check all solder joints for cold joints or solder bridges.Connect the power pigtail provided to a suitable regulated 5 V power supply capable of providingat least 500 mA. Connect your serial terminal or computer to the console port. Apply power toyour system and press RESET. The GWMON sign-on message should be printed to the console, andGWMON should respond to appropriate user input. POWER ON and ROM ON LEDs D1 and D2 shouldbe lit.
4.1 Troubleshooting
If your 8085 SBC rev 3 fails to come up, recheck all solder joints for cold joints, bridges, or missedpins – this is by far the most common problem we’ve observed during assembly workshops. Recheckconfiguration options. Ensure your serial terminal or terminal emulator software is properly config-ured and that your cable is wired correctly (a RS-232 light box is very helpful here). The Intel 8251Amust have CTS asserted or it will disable its transmitter and refuse to send characters.
Verify that *BRESET is properly strobing during power-up and when pressing the RESET button (SW1).If the ROM ON (D2) LED does not light after reset, either the power-on options for ROM (J1 and J2)are incorrect, or the flip-flop circuit is faulty.
4.2 Repair and Service
If you purchased an assembled 8085 SBC rev 3 from The Glitch Works, your board is warranted towork on arrival. If you have assembled a kit that fails to work, you may return it to The GlitchWorks for evaluation, repair, and testing. For questions concerning returns or configuration, pleasevisit http://www.glitchwrks.com/ and click the “Contact” link.
Do note that while we will attempt to help those who have purchased used boards, there is nowarranty extended.
7
5 Technical Notes
5.1 Board Control Register
The 8085 SBC rev 3 includes a board control register, which is a series of writable latches that affecthow various parts of the built-in circuitry function. This register is addressed at I/O BASE + 0x02;in the default configuration, this places the board control register at 0x02. Electrically, it is composedof three different latches: a 4-bit D-type latch at U2, and two elements of a dual D-type latch at U3.The bits of the board control register are mapped as follows:
Register Bit Function Notes
0 ROM Page Address, bit 0 Cleared on reset1 ROM Page Address, bit 1 Cleared on reset2 ROM Page Address, bit 2 Cleared on reset3 ROM Boot flip-flop Reset state determined by J14 ROM Enabled flip-flop Reset state determined by J25 Unused6 Unused7 USER LED output Cleared (LED off) on reset
Bits 0-2 control the selected 4K page of ROM available at ROM BASE. These bits are cleared on resetso that the first page of ROM is available for booting. Writing to these bits immediately changes theROM page. The state of these bits is available through the Board Status Register.
Bit 3 controls the ROM Boot flip-flop. When set, ROM is addressed at all memory locations,repeating throughout memory. This allows the 8085 to read ROM code at 0x0000 on reset. Writinga 0 to this bit clears it and immediately switches off the ROM Boot functionality. Typically, ROMboot code should contain a jump to a startup routine in ROM, which should immediately clear theROM Boot bit. The reset state of bit 3 is controlled by J1, see the “Configuration” section for moreinformation. The state of these bits is available through the Board Status Register.
Bit 4 enables ROM when set, and disables ROM when cleared. This allows unmapping ROM for useof the full 64 KB of system memory. Writing a 0 to this bit clears it and immediately switches offROM, writing a 1 to this bit switches ROM in. The selected ROM page is not affected. The resetstate of bit 3 is controlled by J2, see the “Configuration” section for more information. The state ofthese bits is available through the Board Status Register.
Bits 5 and 6 are not implemented; that is, nothing responds to their state when writing to the BoardControl Register.
Bit 7 is connected to the USER LED (D3). Writing a 1 to this bit lights the LED, writing a 0 turnsthe LED off. This bit is cleared on reset.
5.2 Board Status Register
The 8085 SBC rev 3 includes a board status register which provides the state of several bits of theBoard Control Register, as well as ROM OPT (SW3) DIP switch settings. This register is addressedat I/O BASE + 0x02; in the default configuration, this places the board control register at 0x02.
8
Electrically, it is composed of an octal tristate bus transceiver. The bits of the board status registerare mapped as follows:
Register Bit Function Notes
0 RPA0 switch, SW3-8 Closed reads 11 RPA1 switch, SW3-7 Closed reads 12 RPA2 switch, SW3-6 Closed reads 13 ROM Boot status Boot Enabled reads 14 ROM Enabled status ROM Enabled reads 15 ROM Page Address latch, bit 06 ROM Page Address latch, bit 17 ROM Page Address latch, bit 2
Bits 0-2 reflect the state of SW3 positions 8 through 6. These positions are labeled RPA0 - RPA2 inthe silkscreen. With the standard version of GWMON, these switches select the ROM-FS record toload into memory at reset. A 1 in a given bit position corresponds to a closed switch.
Bit 3 reflects the status of the ROM Boot flip-flop. ROM Boot is enabled when this bit reads 1.
Bit 4 reflects the status of the ROM Enabled flip-flop. ROM is enabled when this bit reads 1.
Bits 5-7 reflect the state of the ROM Page Address latch, which selects the currently addressed 4Kpage from ROM at U17.
5.3 Default Memory Map
Address Range Contents
0x0000 - 0x7FFF Static RAM, IC socket U150x8000 - 0xEFFF Static RAM, IC socket U160xF000 - 0xFFFF Static RAM, IC socket U16, when ROM is disabled0xF000 - 0xFFFF 4K page of ROM, IC socket U19, when ROM is enabled
Onboard memory devices may be overlaid by external devices on the Glitchbus using the *BMASK
signal.
5.4 Default I/O Map
I/O Address R/W Function
0x00 R/W USART Data Register0x01 R USART Status Register0x01 W USART Control Register0x02 R Board Status Register0x02 W Board Control Register0x03 R Board Status Register0x03 W Board Control Register
Note that the Board Control Register and Board Status register appear at both 0x02 and 0x03.
9
6 Errata and Clarifications
6.1 Resistor Pack Values
Kits provided at VCF East XIII (May 2018) included 18 kΩ resistor packs for both RP1 and RP2.18 kΩ was discovered to be insufficient for 74LS85 address comparators, resulting in SW3 1-4 beingignored (ROM BASE always at 0xF000). All later parts kits include 10 kΩ or smaller resistor packs forboth positions. Thanks to Josh Bensadon for reporting this error!
6.2 ROM Compatibility
The ROM socket at U17 is compatible with JEDEC standard 32K x 8 static RAM, FerroelectricRAM (FeRAM), and 28C256 EEPROMs. It may not be compatible with some manufacturers’ UVEPROMs, such as the common 27256 EPROM.
10
7 Parts List
The following substitutions may be made if you have purchased a bare board and are supplying yourown parts, or in a full Glitch Works parts kit:
• Any compatible 7400 series family logic ICs may be used (for example, a 74LS04 in the partslist may be shipped as a 7404, 74S04, 74F04, 74LS04, 74ALS04, or 74HCT04)
• All 4.7 kΩ resistors and resistor packs on the GW-OSI-RAM1 are pull-up or pull-down resistors,and may be any value from 2.2 kΩ to 10 kΩ, even though they are indicated as 4.7 kΩ on theassembly drawing
• Resistors may be of varying precision and body type
If you purchased a full Glitch Works parts kit, be sure it includes the following:
1x 20 pF radial ceramic capacitor
19x 0.01 µF axial ceramic capacitor (yellow bead)
2x 10 nF 16 V radial ceramic capacitor
2x 22 µF 10 V axial tantalum capacitor
5x 22 µF 16 V radial electrolytic capacitor
3x 330 Ω 1/4 W resistor
2x 1 kΩ 1/4 W resistor
17x 4.7 kΩ 1/4 W resistor (see above note)
2x 10 kΩ x 9 SIP resistor packs (see note above)
1x 4 MHz crystal
1x 2.4576 MHz crystal
1x 8085 CPU
1x 8251A USART
1x 28C256 EEPROM, preloaded with GWMON
2x JEDEC 62256-type 32K x 8 static RAM
1x 74LS00 quad 2-input NAND gate
1x 74LS04 hex inverter
1x 74LS20 dual 4-input NAND gate
1x 74LS32 quad OR gate
1x 74LS74 dual D-type flip flop
1x 74LS85 4-bit comparator
1x 74LS138 1-of-8 decoder
1x 74LS175 quad D-type latch
11
3x 74LS245 tranceiver
1x 74LS373 octal D-type latch
1x 74LS688 magnitude comparator
1x 74HCT4040 12-stage binary counter
1x MAX232 RS-232 level shifter
1x DS1233 EconoReset
2x 8-position DIP switch
3x red T-5 LED
1x mini tact pushbutton switch
1x 22-pin breakaway header strip
2x jumper shunt
1x 2-position Molex KK-100 header
1x 5-position Molex KK-100 header
4x 28-pin IC socket
1x 16-pin IC socket
1x Power pigtail
1x RS-232 console pigtail
1x DB25F connector
12
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
A
B
C
D
E
A
B
C
D
E
Date: 2018-07-01KiCad E.D.A. kicad 4.0.4-stable
Rev: 1Size: USLedgerId: 1/3
Title: 8085 SBC rev 3File: 8085_sbc_rev3.schSheet: /The Glitch WorksJ. Chapman
Y1
4 MHz
C9
20 p
F
OE1
O0 2D03
D14 O1 5
O2 6D27
D38 O3 9
LE11
O4 12D413
D514 O5 15
O6 16D617
D718 O7 19
U8
74LS373
A->B1
A02
A13
A24
A35
A46
A57
A68
A79 B7 11B6 12B5 13B4 14B3 15B2 16B1 17B0 18
CE19
U10
74LS245
A15A14A13A12A11A10A9A8
AD7AD6AD5AD4AD3AD2AD1AD0
BA7BA6BA5
BA4BA3
BA2BA1
BA0
BA15BA14BA13BA12BA11BA10BA9BA8
A15A14A13A12A11A10
A9A8
AD7AD6AD5
AD4AD3
AD2AD1
AD0
ALE
ALE
GND
GND
VCC
A->B1
A02
A13
A24
A35
A46
A57
A68
A79 B7 11B6 12B5 13B4 14B3 15B2 16B1 17B0 18
CE19
U14
74LS245
AD7AD6
AD5
AD4
AD3AD2
AD1
AD0 BD0
BD1
BD2BD3
BD4
BD5
BD6BD7
BR**W*RD
BIO**M
*RD
RESET_OUT
1
23U4A
74LS00
1 2U13A
74LS04
*RD
BR**W*BSTART
*BRESET
UART and I/O
uart_io.sch
Memory Devices
memory.sch
GNDBCLOCK
Address Latch and Buffering
Data Bus Buffer and Control Logic
X11
X22
RESET_OUT3
SOD4
SID5
TRAP6
RST_7.57
RST_6.58
RST_5.59
INTR10
ALE 30INTA11
A8 21
*WR 31
AD0 12
A9 22
*RD 32
AD1 13
A10 23
S1 33
AD2 14
A11 24
IO**M 34
AD3 15
A12 25
READY35
AD4 16
A13 26
RESET_IN36
AD5 17
A14 27
CLK_OUT37
AD6 18
A15 28
HLDA38
AD7 19
S0 29
HOLD39
U9
8085
GND
GND
VCC VDD
VSS
C19
C
C20
C
C21
C
C22
C
C23
C
C24
C
C12
C
W1MTG
W2MTG
W3MTG
W4MTG
GND
Mounting Holes
1 23 45 67 89 10
20
30
40
11
21
31
12
22
32
13
23
33
14
24
34
15
25
35
16
26
36
17
27
37
18
28
38
19
29
39
J4
GLI
TC
HB
US
R64.7K
R74.7K
R84.7K
R94.7K
R104.7K
R54.7K
R14.7KR
24.
7K
VCC
GND1*RESET 2
VCC3U1
DS1233*BRESET
VCC
GNDC1
10n
SW
1RE
SE
T
GND
C10
C
C11
C
C2
C
C3
C
C4
C
C5
C
C6
C
C13
C
C14
C
C15
C
C7
C
C18
C
VCC
GND
BD0 BD1BD2 BD3BD4 BD5BD6 BD7
BA7BA6BA5BA4BA3BA2BA1BA0
BA15BA14BA13BA12BA11BA10BA9BA8
1245
6U6A
74LS20
8
9101213
U6B
74LS20
*ROM_CS*RAM_LO_CS*RAM_HI_CS
*IO_BASE_SEL
*EXTERNAL_BUS
*EXTERNAL_BUS
*BRESET
*BMASK*BSTART
BCLOCK
BIO**MBR**W *BINT
*BSTART Signal Generator -- Signals Start of Bus Transaction
*BINT
R15
4.7K
VCC
INTERRUPT
TP1
INTC8
22uF
R11
4.7K
R12
4.7K
VCC
12
D1
PO
WE
R
GND
VCC
R17
330R
Power Indicator
W5MTG
W6MTG
Bypass and Decoupling CapsBypass caps are 0.01 - 0.1 uF
Reset circuit
Open collector with internal pull-upCan connect an external switch from Glitchbus
Glitchbus Expansion Connector
Interrupt Inverter
If desired, jumper output to one of the 8085 interrupt inputsRecommended to use a half-interrupt, not INTR
Processor, Oscillator, and Pull-Ups/Pull-Downs
External data bus is only active when no onboard device is selected
BREADY
BREADY
12
J3
PO
WE
RC17
22uF
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
A
B
C
D
E
A
B
C
D
E
Date: 2018-07-01KiCad E.D.A. kicad 4.0.4-stable
Rev: 1Size: USLedgerId: 2/3
Title: 8085 SBC rev 3File: uart_io.schSheet: /UART and I/O/The Glitch WorksJ. Chapman
89U13D
74LS04
G1
P02
R03
P14
R15
P26
R27
P38
R39
P411
R412
P513
R514
P615
R616
P717
R718
P=R 19U7
74LS688
*BSTART
BIO**M
89
10
U5C74LS32
1112
13
U5D74LS32
BA1
*BA1
*UART_CS
*CONTROL_REG_CS
VCC
VCC
D21
D32
RxD 3D45
D56
D67
D78
*TxC 9
*WR10
CLK 20
*CS11
RESET21
C**D12 *DSR 22
*RD13
*RTS 23
RxRDY 14
*DTR 24
TxRDY 15
*RxC 25
SYNDET/BD 16
*CTS 17
D027
TxEMPTY 18
D128
TxD 19
U198251A_USART
BA0
BCLOCK
BR**W*RD
*UART_CS
RESET_OUT
1
23U5A
74LS32
4
56U5B
74LS32
BR**W
*RD*STATUS_REG_CS
12345678 9
10111213141516
SW2
I/O BASE
BA7BA6
BA5
BA4
BA3
BA2
RP
2
10K
GND
VCC
AD7AD6AD5AD4AD3AD2AD1AD0
Q11 1
Q5 2Q4 3
Q6 4
Q3 5Q2 6Q1 7Q0 9CLK10
Reset11
Q8 12Q7 13
Q9 14
Q10 15
U20
4040
Y2
2.4576 MHz
C16
10n
R211K
R221K
BA1 *BA1
GND
768003840019200
9600480024001200
600300150
7537.5
12345678910111213141516
J5
UA
RT
SP
EE
D
UART_CLOCK
UART_CLOCK
1011U13E
74LS04
1213U13F
74LS04
*IO_BASE_SEL
UART Clock Generator
I/O Base Address and Device Select Decode Logic
LOGIC RS232
C1+1
VS+ 2
C1-3
C2+ 4
C2- 5
VS- 6
T2OUT 7
R2IN 8R2OUT9
T2IN10
T1IN11
R1OUT12 R1IN 13
T1OUT 14
GN
D15
VC
C16
U21 MAX232
VCC
GND
C25
CP
C27
CP
C28CP
TxDRxD
*RTS
*CTS
TxD
RxD
*RTS
*CTS
C29CP
GND
VCC
C26
CP
12345
J6
CO
NS
OLEEIATX
EIARX
GND
EIARTS
EIACTS
EIARTS
EIATX
EIACTS
EIARX
C25-C29: 1 to 22 uF
8251A USART
RS-232 Level Shifter
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
A
B
C
D
E
A
B
C
D
E
Date: 2018-07-01KiCad E.D.A. kicad 4.0.4-stable
Rev: 1Size: USLedgerId: 3/3
Title: 8085 SBC rev 3File: memory.schSheet: /Memory Devices/The Glitch WorksJ. Chapman
1112
13
U4D
74LS00BA15*ROM
*BMASKBIO**M
A141
A122
A73A64A55A46A37A28A19A010
*CE 20
D0 11
A1021
D1 12
*OE 22
D2 13
A1123
A924
D3 15
A825
D4 16
A1326
D5 17
*WE 27
D6 18
D7 19U15
62256
BA14BA13BA12BA11BA10
BA9BA8BA7BA6BA5BA4BA3BA2BA1BA0
*RAM_LO_CS
BR**W*RD
*RAM_LO_CS
A01
A12
A23
E14E25E36
O7 7O6 9O5 10O4 11O3 12O2 13O1 14O0 15
U12
74LS138
*RAM_HI_CS
ROM_CS
*BSTART
GND
*ROM_CS
A141
A122
A73A64A55A46A37A28A19A010
*CE 20
D0 11
A1021
D1 12
*OE 22
D2 13
A1123
A924
D3 15
A825
D4 16
A1326
D5 17
*WE 27
D6 18
D7 19U16
62256
BA14BA13BA12BA11BA10
BA9BA8BA7BA6BA5BA4BA3BA2BA1BA0
*RAM_HI_CS
BR**W*RD
A141
A122
A73A64A55A46A37A28A19A010
*CE 20
D0 11
A1021
D1 12
*OE 22
D2 13
A1123
A924
D3 15
A825
D4 16
A1326
D5 17
*WE 27
D6 18
D7 19U17
32K ROM
BA10BA9BA8BA7BA6BA5BA4BA3BA2BA1BA0
*ROM_CS
*ROM_WR*RD
BA11
Mr1
Q0 2
Q0 3D04
D15
Q1 6Q1 7
Cp9
Q2 10
Q2 11D212
D313
Q3 14Q3 15
U2
74LS175*BRESET
RPA0
RPA1
RPA2
RPA0RPA1RPA2
ROM Page Register
This register controls which 4K page of ROM is addressed.Cleared to 0 on *RESET, writable at IO_BASE + 2Bits 0 - 2 set ROM page, bit 7 is user-defined
Memory Device Select Logic
Memory Devices
*CONTROL_REG_CS
A->B 1
A0 2
A1 3
A2 4
A3 5
A4 6
A5 7
A6 8
A7 9B711B612B513B414B315B216B117B018
CE 19
U18
74LS245
*STATUS_REG_CS
RPA0RPA1RPA2
ROM_ENABLED
ROM_AT0
Status Register
Readable at IO_BASE + 2
ROMBASE12ROMBASE13ROMBASE14ROMBASE15
VCC
GND
Q 8
Q 9
Sd
10
Cp11
D12
Cd
13
U3B
74LS74
Cd
1
D2
Cp3
Sd
4
Q 5
Q 6
U3A
74LS74
*BRESET
ROM_ENABLED
*ROM_AT0
*ROM_ADDRESS
*CONTROL_REG_CS
*CONTROL_REG_CS
ROM_AT0
B31
Ia<b 2
Ia=b 3
Ia>b 4
Oa>b 5
Oa=b 6Oa<b 7
B09
A010
B111
A112A213
B214
A315
U11
74LS85
BA14BA13BA12
BA15
ROMBASE12ROMBASE13ROMBASE14ROMBASE15
VCC
GND
4
56U4B
74LS00
89
10
U4C
74LS00
*ROM_AT0
*ROM_ADDRESSROM_ADDRESS_SELECT
ROM_ENABLED
ROM_ADDRESS_SELECT*ROM
ROM Boot Flip-Flop
Places ROM at all memory locations when SETWritable at IO_BASE + 2 bit 3
ROM Enabled Flip-Flop
Allows ROM to be activated when SETWritable at IO_BASE + 2 bit 4
ROM Base Address Decoder
Determines the address of the 4K segment that ROM normallyoccupies when enabled and boot flip-flop is CLEAR
RP
1
10K
AD7
AD3
AD4
AD2
AD1
AD0
AD7AD6AD5AD4
AD3AD2AD1AD0
AD7AD6AD5AD4AD3AD2AD1AD0
AD7AD6AD5AD4AD3AD2AD1AD0
AD7AD6AD5AD4AD3AD2AD1AD0
123
J2
RO
M_E
NA
BLE
D
123
J1 RO
M_B
OO
T
1-2: ROM at ROM Base Only on *RESET2-3: ROM at All Addresses on *RESET
1-2: ROM Disabled at *RESET2-3: ROM Enabled at *RESET
*BRESET
12345678 9
10111213141516
SW3
ROM OPT
GND
5 6U13C
74LS04
3 4U13B
74LS04
BR**W*ROM_WR
R20
4.7K
R134.7K
R34.7K
R144.7K
R44.7K
VCC
VCC
VCC
VCC
R16
4.7K
VCC
R19
330R
12
D3
US
ER
VCC
R18
330R
12
D2
RO
M
VCC
ROM Address Select Logic
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