CMOS - Robert Dickziyang.eecs.umich.edu/~dickrp//eecs312/lectures/print... · 2010. 12. 1. · Squadron s Pen tiu m4 Mcki nley Pre scott Jay hawk( dual) IB M Z9 Latches and ﬂip-ﬂops

Digital Integrated Circuits – EECS 312

http://ziyang.eecs.umich.edu/∼dickrp/eecs312/

Teacher: Robert DickOffice: 2417-G EECSEmail: [email protected]: 734–763–3329Cellphone: 847–530–1824

GSI: Myung-Chul KimEmail: [email protected]

HW engineers SW engineers

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Time (seconds)

Typical Current Draw 1 sec Heartbeat

30 beats per sample

Sampling andRadio Transmission

9 - 15 mA

Heartbeat1 - 2 mA

Radio Receive for

Mesh Maintenance

2 - 6 mA

Low Power Sleep0.030 - 0.050 mA

Year of announcement

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Bipolar

CMOS

VacuumIBM 360

IBM 370 IBM 3033

IBM ES9000

Fujitsu VP2000

IBM 3090S

NTT

Fujitsu M-780

IBM 3090

CDC Cyber 205IBM 4381

IBM 3081

Fujitsu M380

IBM RY5

IBM GP

IBM RY6

Apache

Pulsar

Merced

IBM RY7

IBM RY4

Pentium II(DSIP)

T-Rex

Squadrons

Pentium 4

Mckinley

Prescott

Jayhawk(dual)

IBM Z9

Latches and flip-flopsHomework

Lab 4

Can assume first stage is like an inverter, then experiment.

A few simulation runs are fine.

Not expecting exhaustive search.

Capacitance of first gate? Can assume that γ = 1.

If not clear, email discussion list today so Mr. Kim and I know tomake more suggestions.

Derive and explain.

2 Robert Dick Digital Integrated Circuits


Review

What is charge sharing?

Why are there two different expressions for the voltage to whichVout settles?

Is leakage a significant factor in charge sharing?

How can it be prevented?

What is volatile memory?

What is non-volatile memory?

What is static memory?

What is dynamic memory?

Derive and explain.



Reset/set latchesClocking conventionsD flip-flopOther memory elements

Combinational vs. sequential logic

No feedback between inputs and outputs – combinational

Outputs a function of the current inputs, only

Feedback – sequential

q plain old combinational logic

D flip−flops

q

clock

plain old combinational logic

D flip−flops

q

clock

plain old combinational logic

D flip−flops




Sequential logic

Outputs depend on current state and (maybe) current inputs

Next state depends on current state and input

For implementable machines, there are a finite number of states

Synchronous

State changes upon clock event (transition) occurs

Asynchronous

State changes upon inputs change, subject to circuit delays




Flip-flop introduction

Stores, and outputs, a value.

Puts a special clock signal in charge of timing.

Allows output to change in response to clock transition.

More on this later.

Timing and sequential circuits




Introduction to sequential elements

Feedback and memory.

Memory.

Latches.




Feedback and memory

Feedback or physical state are the root of memory.

Can compose a simple loop from inverters.

However, there is no way to switch the value.




Bistability




TG and NOT-based memory

Can break feedback path to load new value

However, potential for timing problems




One-bit volatile cell

Can break feedback path to load new value.

How can this be made more efficient?

Resize transistors, remove transistors, use state?




Reset/set latch

R

R

S

S

Q

Q

Q




Reset/set timing

100

Reset Hold Set Reset Set Race

R

S

Q

Q

Unstable state Unstable state




RS latch state diagram

01

0010

0001

1111

10

10 01

11

1001

00

output=Q Q

input=R S




Clocking terms

Input

Clock

T su

T h

Clock – Rising edge, falling edge, high level, low level, period

Setup time: Minimum time before clocking event by which inputmust be stable (TSU)

Hold time: Minimum time after clocking event for which inputmust remain stable (TH)

Window: From setup time to hold time




Gated RS latch

S

ENB

R

Q

Q




Gated RS latch

S

R

ENB

Q

Q




Memory element properties

Type Inputs sampled Outputs validUnclocked latch Always LFTLevel-sensitive latch Clock high LFT

(TSU to TH) around falling clock edgeEdge-triggered flip-flop Clock low-to-high transition Delay from rising edge

(TSU to TH) around rising clock edge




Clocking conventions

D Q

CLK

D

Active−high transparent

Q

CLK

Active−low transparent

Negative (falling) edge

D Q

CLKCLK

D Q

Positive (rising) edge




Timing for edge and level-sensitive latches

D

Clk

Q edge

Q level




Latch timing specifications

Minimum clock width, TW

Usually period / 2

Low to high propegation delay, PLH

High to low propegation delay, PHL

Worst-case and typical




Latch timing specifications

Example, negative (falling) edge-triggered flip-flop timing diagram

T su

20 ns

T h

5 ns

T su

20 ns

T h

5 ns

T w

20 ns

T plh

C » Q 27 ns 15 ns

T phl

C » Q 25 ns 14 ns

T plh

D » Q 27 ns 15 ns

T phl

D » Q 16 ns 7 ns

D

Clk

Q




FF timing specifications

Minimum clock width, TW

Usually period / 2

Low to high propagation delay, PLH

High to low propagation delay, PHL




FF timing specifications

Example, positive (rising) edge-triggered flip-flop timing diagram

D

Clk

Q

T su

20 ns

T h

5 ns

T w

25 ns

T plh

25 ns 13 ns

T su

20 ns

T h

5 ns

T phl

40 ns 25 ns




RS latch states

S R Q+ Q+ Notes

0 0 Q Q

0 1 0 11 0 1 01 1 1 1 unstable




Falling edge-triggered D flip-flop

Use two stages of latches

When clock is high

First stage samples input w.o. changing second stageSecond stage holds value

When clock goes low

First stage holds value and sets or resets second stageSecond stage transmits first stage

Q+ = D

One of the most commonly used flip-flops




Edge triggered timing

Positive edge−

t riggered FF

Negative edge−

t riggered FF

100




RS clocked latch

Storage element in narrow width clocked systems.

Dangerous.

Fundamental building block of many flip-flop types.




D flip-flop

Minimizes input wiring.

Simple to use.

Common choice for basic memory elements in sequential circuits.




Toggle (T) flip-flops

State changes each clock tick

Useful for building counters

Can be implemented with other flip-flops

D with XOR feedback




Asynchronous inputs

How can a circuit with numerous distributed edge-triggeredflip-flops be put into a known state?

Could devise some sequence of input events to bring the machineinto a known state.

Complicated.Slow.Not necessarily possible, given trap states.

Can also use sequential elements with additional asynchronousreset and/or set inputs.




Schmitt triggers

A B

A

A B

A

A B

A

transition

A B

A

transition

B

A B

A




Reason for gradual transition

A logic stage is an RC network

Whenever a transition occurs, capacitance is driven throughresistance

Consider the implementation of a CMOS inverter




Debouncing

Mechanical switches bounce!

What happens if multiple pulses?

Multiple state transitions

Need to clean up signal




Debouncing

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-1.0e-03 -5.0e-04 0.0e+00 5.0e-04 1.0e-03 1.5e-03

V

T (s)

Schmidt trig.RC

0.751.65




Latch and flip-flop equations

RS

Q+ = S + R Q

D

Q+ = D

T

Q+ = T ⊕ Q




Upcoming topics

Sequential circuits.

Theoretical foundations for sizing.



Homework assignment

22 November, Monday: Lab 4.

23 November, Tuesday: Read Sections 12.1 in J. Rabaey,A. Chandrakasan, and B. Nikolic. Digital Integrated Circuits: A

Design Perspective. Prentice-Hall, second edition, 2003.

30 November, Tuesday: Read Sections 12.2 in J. Rabaey,A. Chandrakasan, and B. Nikolic. Digital Integrated Circuits: A

Design Perspective. Prentice-Hall, second edition, 2003.


Special topic: Subthreshold circuit applications

Megan and Tyler.

Documents

CMOS - Robert Dickziyang.eecs.umich.edu/~dickrp//eecs312/lectures/print... · 2010. 12. 1. · Squadron s Pen tiu m4 Mcki nley Pre scott Jay hawk( dual) IB M Z9 Latches and ﬂip-ﬂops