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Full Adder Design
Design Practice - MyCAD
Full Adder Design Practice - MyCAD 2
• Preface• XOR2 Design
– XOR2 schematic and symbol– XOR2 simulation– XOR2 layout and results of verification
• AND2 Gate Design– AND2 gate schematic and symbol– AND2 simulation– AND2 gate layout and results of verification
• OR2 Gate Design– AND2 gate schematic and symbol– AND2 simulation– AND2 gate layout and results of verification
• Half Adder Design– Half Adder schematic and symbol– Half Adder simulation– Half Adder layout and results of verification
• Full Adder Design– Full Adder schematic and symbol– Full Adder simulation– Full Adder layout and results of verification
Table of Contents
Full Adder Design Practice - MyCAD 3
Preface
• This document provides the information on how to design Full Adder schematic and layout.
• Full Adder is designed based on MOSIS SCMOS layout rules.
• If you want to get more information, please refer to the related documents as below.– MyCAD Tutorial :
Learn how to use schematic and layout editor.– MySpice Tutorial :
Learn about simulating a circuit.– MyChip Pro Verification Reference Manual :
Look up specific verification commands.
Copyright © 1992 – 2006, SELOCO Incorporated.
Full Adder Design Practice - MyCAD 4
XOR2 schematic and symbol
Logic Symbol
Truth Table Schematic011
101
110
000
OUTBA
Full Adder Design Practice - MyCAD 5
XOR2 Simulation
OUT
A
B
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XOR2 layout and results of verification
Layout
DRC result
LVS result
Full Adder Design Practice - MyCAD 7
AND2 gate schematic and symbol
Logic Symbol
Truth Table
111
001
010
000
OUTBA
OutputInput
Schematic
Full Adder Design Practice - MyCAD 8
AND2 Simulation
Z
A
B
Full Adder Design Practice - MyCAD 9
AND2 layout and results of verification
Layout
DRC result
LVS result
Full Adder Design Practice - MyCAD 10
OR2 gate schematic and symbol
Logic Symbol
Truth Table
111
101
110
000
ZBA
OutputInput
Schematic
Full Adder Design Practice - MyCAD 11
OR2 Simulation
Z
A
B
Full Adder Design Practice - MyCAD 12
OR2 layout and results of verification
Layout
DRC result
LVS result
Full Adder Design Practice - MyCAD 13
HA schematic and symbol
Logic Symbol
Truth Table
1011
0101
0110
0000
C0SBA
Schematic
Full Adder Design Practice - MyCAD 14
HA Simulation
OUTA
B Co
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HA layout and results of verification
Layout
DRC result
LVS result
Full Adder Design Practice - MyCAD 16
FA schematic and symbol
Logic Symbol
Truth Table11111
10011
10101
01001
10110
01010
01100
00000
CoutSumCinBinAin
OutputInput
Schematic
Full Adder Design Practice - MyCAD 17
FA Flip-Flop Simulation
Cout
Q (output)
Bin
Ain
Cin
Full Adder Design Practice - MyCAD 18
FA layout and results of verification
Layout
DRC result
LVS result
The End
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