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Extending the Power of FPGAs to Software Developers:
The Journey has Begun
Salil Raje
Xilinx Corporate Vice President
Software and IP Products Group
The Evolution of FPGAs and FPGA Programming
IP-Centric Design with High Level Languages
Software Defined Systems
Agenda
2
The Evolution of FPGAs and FPGA Programming
The Evolution of Programmable Devices
Logic
Cells
1985 1995 20152005 2025
Programmable
SoCs
PLDs
3D ICs
FPGAs
100
1M
10K
4
Programmable
SoCs
PLDs
3D ICs
FPGAs
The Progression of FPGA Design Methodology
Logic
Cells
1985 1995 20152005 2025
100
1M
10K Schematics
RTL
IP-Centric with
High-level Languages
Software Defined
5
Programmable
SoCs
PLDs
3D ICs
FPGAs
The Shift in Developer Personas
Logic
Cells
1985 1995 20152005 2025
100
1M
10K
Application Developer
Hardware Designer
Algorithm Developer
Embedded SW Dev.
Schematics
RTL
IP-Centric with
High-level Languages
Software Defined
Hardware
Designer
6
IP-Centric Design with High
Level Languages
Example of Hard IP: Zynq MPSOC
Step 1: Leverage Broad Array of Hard and Soft IP
+ Embedded Processors
OTN Subsystem
Examples of Complex Soft IP
Video Subsystem
HMC Controller Digital Pre-Distortion
SmartConnect
AXI4-S router10x10
VDMA
AXI-MM
AXI4-S AXI4-S
AXI4-S
Deinterlacer
AXI4-S AXI4-S
V Scaler
AXI4-S AXI4-S
H Scaler
AXI4-S AXI4-S
CSC
AXI4-S AXI4-S
422-444
AXI4-S AXI4-S
AXI4-S
AXI-Lite interconnect
AXI-LiteAXI-MM
AXI-Lite
420-422420-422
AXI4-S AXI4-S
AXI-MM interconnect
AXI-MM
Letterboxing
AXI4-S AXI4-S
Page 8
Step 2: Develop New IP blocks in C/C++
Page 9
Create IP from C/C++/System C algorithm specification
Abstract algorithm verification 10,000x faster than RTL sim
Traditional FPGA design experience not required
Algorithmic
Specification
Micro-architecture
Exploration
RTL Implementation
FPGA Integration
Step 3: Use Automated IP Assembly
4700 lines of VHDL
(top-level connectivity only)
=
IP Assembly Example:
Zynq Processor Subsystem
+ Video Subsystem
+ 6 IP Blocks
Video Processing IP Subsystem
The Era of Software Defined Systems
Why FPGAs for Software Defined Systems?
The Era of Virtualization
– Reconfigurable computing, storage
and networking in the cloud
The Thirst for Acceleration
– Heterogeneous computing
– Compute-intensive algorithms
• DNA sequencing
• Search engines
• Video processing
• Encryption/Decryption
• Packet routing
Page 12
FPGAs and Programmable SoCs:
• Power-efficient
• Reconfigurable
• Massively-Parallel
• Compute Engines
Compares Query(N) with Reference(M)
genome strings
Involves MxN Matrix Computation and
Dynamic Programming
Maximal parallelism along diagonals
Example of FPGAs as AcceleratorsSmith-Waterman DNA Sequencing Application
Page 13
Reference
Qu
ery
Xilinx Virtex-7
690T
(reference)
Intel® Xeon
E5-2697
12 core
Ratio
Virtex-7 vs.
Intel 12 core
Intel® Xeon
Phi 5110P
60 core
Ratio
Virtex-7 vs.
Intel 60 Core
GCUPS 77.00 19.75 3.90 30.00 2.57
Watts 28.00 130.00 0.22 225.00 0.12
GCUPS/Watt 2.75 0.15 18.10 0.13 20.63
Software Defined SoC DevelopmentStandard
Eclipse IDE
Embedded ARM
Processor Subsystem
Programmable Logic
Applications:
– Machine Vision
– Driver Assistance/ADAS
– Software-Defined Radio (SDR)
– Wireless Radio
– Surveillance
– UAV / Drones
Full System Optimizing Compiler
C/C++ Development
System-level Profiling
Mark C/C++ Functions
for Acceleration
ARM Code
Main( )Connectivity
Accelerator
Func( )
GCCHLS+
SP&R
Page 14
Sample Applications:
– Machine Learning
– Bioinformatics
– Graph Processing
– Stringology
– Data Analytics
– Modelling
– Science Codes
– Signal Processing
– Video & Image Processing
Page 15
Software Defined Algorithm Acceleration in the
Data Center
Software-Defined
FPGA Acceleration
Software Defined Programmable Packet Processing
Page 16
SW & HW
Implementation
‘Softly Defined’ Packet Processor
SDK/API Executable
Image
SP&R
1GB
10GB
40GB
100GB
FPGA or
Programmable SoC
SearchCo-Processor
ExternalMemory
CPU
Compiler
High-level
Specifications
LogiCORE
SmartCORE
Custom Core
SW Function
Moving to P4 industry standard
Rapid Prototyping
RTL output with verification testbench
Deterministic Performance
Optimal HW Implementation
Platforms Enable Software Defined FPGA Systems
Page 17
Board Support
Hardware
System
Design & Host
Software
Stack
Partial
Reconfig
Performance
Analysis
Pre-defined
Platform
Algorithms
C-based IP development + high-level IP assembly are the next step beyond RTL
Software-defined algorithm development + platforms will enable you to exploit
the power of FPGAs & SoCs
Page 18
Summary
HW designers: SW developers:
We’re making major investments in next generation silicon and tools that
will revolutionize FPGA design
Xilinx University Program:
– Early Access Program
– Full license available in donation program
– Academic price on Alpha Data boards
– Visit www.xilinx.com/university
Page 19
Xilinx Wants You: Researchers, Academics
Page 20
Thank You!
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