Evolution in Complexity

Evolution in Complexity

Evolution in Transistor Count

Evolution in Speed/Performance

Intel 4004 Micro-Processor

Intel Pentium (II) microprocessor

Design Abstraction Levels

n+n+S

GD

+

DEVICE

CIRCUIT

GATE

MODULE

SYSTEM

Silicon in 2010

Die Area: 2.5x2.5 cmVoltage: 0.6 VTechnology: 0.07 m

Density Access Time(Gbits/cm2) (ns)

DRAM 8.5 10DRAM (Logic) 2.5 10SRAM (Cache) 0.3 1.5

Density Max. Ave. Power Clock Rate(Mgates/cm2) (W/cm2) (GHz)

Custom 25 54 3Std. Cell 10 27 1.5

Gate Array 5 18 1Single-Mask GA 2.5 12.5 0.7

FPGA 0.4 4.5 0.25

Jan M. Rabaey

The Devices

The MOS Transistor

n+n+

p-substrate

Field-Oxyde

(SiO2)

p+ stopper

Polysilicon

Gate Oxyde

DrainSource

Gate

Bulk Contact

CROSS-SECTION of NMOS Transistor

Current-Voltage Relations

Dynamic Behavior of MOS Transistor

DS

G

B

CGDCGS

CSB CDBCGB

THE INVERTERS

DIGITAL GATES Fundamental Parameters

• Functionality• Reliability, Robustness• Area• Performance

– Speed (delay)– Power Consumption– Energy

The CMOS Inverter: A First Glance

VDD

Vin Vout

CL

VTC of Real Inverter

0.0 1.0 2.0 3.0 4.0 5.0Vin (V)

1.0

2.0

3.0

4.0

5.0

Vou

t (V

)

VMNMH

NML

Delay Definitions

tpHL tpLH

t

t

Vin

Vout

50%

50%

tr

10%

90%

tf

VDD VDD

VinVout

M1

M2

M3

M4Cdb2

Cdb1

Cgd12

Cw

Cg4

Cg3

Vout2

Fanout

Interconnect

VoutVin

CLSimplified

Model

CMOS Inverters

Polysilicon

InOut

Metal1

VDD

GND

PMOS

NMOS

1.2 m=2

Scaling Relationships for Long Channel Devices

COMBINATIONAL LOGIC

Overview

Static CMOS

Conventional Static CMOS Logic

Ratioed Logic

Pass Transistor/Transmission Gate Logic

Dynamic CMOS Logic

Domino

np-CMOS

Static CMOS

VDD

VSS

PUN

PDN

In1In2In3

F = G

In1

In2In3

PUN and PDN are Dual Networks

PMOS Only

NMOS Only

Example Gate: NAND

Transistor Sizing

VDD

AB

C

D

DA

B C

12

22

6

612

12

F

• for symmetrical response (dc, ac)• for performance

Focus on worst-case

Input Dependent

4-input NAND Gate

Out

In1 In2 In3 In4

In3

In1

In2

In4

In1 In2 In3 In4

VDD

Out

GND

VDD

In1 In2 In3 In4

Vdd

GND

Out

Ratioed Logic

VDD

VSS

PDNIn1In2In3

F

RLLoad

VDD

VSS

In1In2In3

F

VDD

VSS

PDNIn1In2In3

FVSS

PDN

Resistive DepletionLoad

PMOSLoad

(a) resistive load (b) depletion load NMOS (c) pseudo-NMOS

VT < 0

Goal: to reduce the number of devices over complementary CMOS

Pseudo-NMOS

VDD

A B C D

FCL

VOH = VDD (similar to complementary CMOS)

kn VDD VTn– VOLVOL

2

2-------------–

kp

2------ VDD VTp– 2=

VOL VDD VT– 1 1kpkn------–– (assuming that VT VTn VTp )= = =

SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!

Dynamic Logic

Mp

Me

VDD

PDN

In1In2In3

OutMe

Mp

VDD

PUN

In1In2In3

Out

CL

CL

p networkn network

2 phase operation:• Evaluation

• Precharge

Example

Mp

Me

VDD

Out

A

B

C

• N + 1 Transistors

• Ratioless

• No Static Power Consumption

• Noise Margins small (NML)

• Requires Clock

Cascading Dynamic Gates

Mp

Me

VDD

Mp

Me

VDD

In

Out1 Out2

Out2

Out1

In

V

t

V

VTn

(a) (b)

Only 0 1 Transitions allowed at inputs!

Domino Logic

Mp

Me

VDD

PDN

In1In2

In3

Out1

Mp

Me

VDD

PDN

In4

Out2

Mr

VDD

Static Inverterwith Level Restorer

Where Does Power Go in CMOS?

• Dynamic Power Consumption

• Short Circuit Currents

• Leakage

Charging and Discharging Capacitors

Short Circuit Path between Supply Rails during Switching

Leaking diodes and transistors

SEQUENTIAL LOGIC

Master-Slave Flip-Flop

S

R

Q

Q Q

QS

R

Q

Q

J

K

MASTER SLAVE

QJ

K Q

PRESET

CLEAR

SI

RI

CMOS Clocked SR- FlipFlop

VDD

Q

Q

RS

M1 M3

M4M2

M6

M5 M7

M8

2 phase non-overlapping clocks

D

In

t12

PipeliningR

EG

REG

R

EG

log.

RE

G

REG

RE

G

.

RE

G

RE

G

logOut Out

a

b

a

b

Non-pipelined version Pipelined version

Arithmetic Building Blocks

A Generic Digital Processor

MEM ORY

DATAPATH

CONTROL

INPU

T-O

UT

PUT

Building Blocks for Digital Architectures

Arithmetic unit- Bit-sliced datapath (adder , multiplier,

shifter, comparator, etc.)

Memory- RAM, ROM, Buffers, Shift registers

Control- Finite state machine (PLA, random logic.)- Counters

Interconnect- Switches- Arbiters- Bus

Bit-Sliced Design

Bit 3

Bit 2

Bit 1

Bit 0

Reg

ister

Add

er

Shift

er

Mul

tiple

xer

Control

Dat

a-In

Dat

a-O

ut

Tile identical processing elements

Layout Strategies for Bit-Sliced Datapaths

Well

ControlWires (M1)

Well

Wires (M1)

GND VDDGND

GND

VDD

GND

Approach I —Signal and power lines parallel

Approach II —

Signal and power lines perpendicular

Sign

als W

ires

(M2)

Sign

als W

ires

(M2)

Layout of Bit-sliced Datapaths

COPING WITH INTERCONNECT

Impact of Interconnect Parasitics

• Reduce Reliability

• Affect Performance

Classes of Parasitics

• Capacitive

• Resistive

• Inductive

Using Cascaded Buffers

C2C1

Ci

CL

1 u u2 uN-1

In Out

uopt = e

ISSUES IN TIMING

The Ellmore Delay

The Clock Skew Problem

CL1 R1 CL2 R2 CL3 R3In Out

t’ t’’ t’’’

tl,min

tl,max

tr,min

tr,max

ti

Clock Edge Timing Depends upon Position

Clock Rates as High as 500 Mhz in CMOS!