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Welcome to this presentation of Software Defined Radio as seen from the FPGA
engineer‘s perspective!
As FPGA designers, we find SDR a very exciting field and wish that all of you will
have a chance to realize a SDR project at least once.
If you have questions, please interrupt me at any time. This will help you and
others to follow the presentation.
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17 May 2011PLC2 FPGA Days 2011 - Software Defined Radio
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17 May 2011PLC2 FPGA Days 2011 - Software Defined Radio
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Superheterodyne: Mixing any channel to a constant IF frequency
In a first step, the RF channel is mixed to an intermediate frequency (IF) using a
variable local oscillator with frequency
fLO = fRF_channel - fIF
In a second step, the signal is mixed to baseband with using
0° and 90° components of an IF oscillator resulting in „complex“ I/Q data
streams.
The I/Q components are then sampled using two ADCs.
Analog I/Q demodulators are not ideal, but could be corrected digitally. The
problem is a stronger signal on the mirror frequency fMirror = fRF_channel + fIF .
Transmitter works the same way, but in the reverse direction.
Single channel systems usually use a transmit/receive switch.
Advantage: Half the sampling frequency per I/Q component.
Disadvantage: DC errors appear like a carrier in the center of the channel.
Multi-channel systems are usually not implemented in this way.
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The RF band of interest (multiple channels) is mixed to an IF frequency and
then directly sampled by a single ADC.
The IF frequency is often chosen as the center of the second Nyquist window
as this simplifies the RF filters while maintaining acceptable ADC performance.
Advantage: I/Q demodulation is performed digitally and therefore almost
ideally.
Disadvantage: Signal dependent AGC not possible in multi-channel systems.
System dynamic range may become a big challenge.
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A direct-IF RF front-end is assumed.
Only a single channel is shown.
Most internal data paths are complex (I/Q).
Filtering/decimating/interpolating complex data is simple. Simply perform the
operation on each of the components (I/Q) separately.
Assumption: Linear phase filters
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Four signed operands, named A, B, C, D
One 48 bit result P
All numbers are in signed two‘s complement representation.
Pre-adder may be used for symmetric FIR filters and some other functions.
A and D inputs are connected to the two samples that are to be multiplied
with the common coefficient B.
25 bit data sample inputs (A, D) and 18 bit coefficient input (B)
Dedicated routing resources for cascading DSP48 slices are not shown here.
Very advanced pipelining options are not shown here.
Rounding can be implemented by adding a suitable rounding constant via the
C input.
All pipelining registers must be used for maximum performance.
Performance in the fastest speed-grade
~600 MHz for Virtex-7/Kintex-7 FPGAs
~500 MHz for Artix-7 FPGAs
600 MHz for Virtex-6 FPGAs
390 MHz for Spartan-6 FPGAs
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Transition band is „relatively“ wide and centered around fs/4.
Only 3dB attenuation in the center of the transition band.
Pass-band and stop-band have the same width.
Usually only useful for decimation/interpolation low-pass filtering.
Every second filter coefficient except the center coefficient is zero.
Almost half the processing power in comparison with regular symmetric FIR
filters.
Increasing the order, flattens the pass-band and attenuates the stop-band. This
may not be optimal for certain applications.
Possible filter orders: 2+N*4
For complex data, the pass-band is twice as wide (positive/negative
frequencies)
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Colors
Green: The channel of interest.
Blue: neighboring channel or interference in the transition-band of the half-
band filter.
Red: neighboring channel or interference in the stop-band of the half-band
filter.
The red frequencies are attenuated and then aliased over the passband.
The two halves of the blue frequencies are aliased over each other in the
transition band.
Interference in the transition-band stays present and must be filtered away by
the next decimation stage or by a „sharp“ channel filter.
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This works basically the same way as the decimator.
The input signal should not contain any frequencies in the transisition-band or
the stop-band of the half-band filter to prevent aliasing.
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When cascading decimation stages, the second stage needs only half as much
processing power of the first stage, because the sampling rate is half.
Optimally, only twice as many DSP slices of the first stage are needed for all
stages.
The same is valid for interpolation.
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Filtering and decimation of four adjacent channels is shown in a hierarchical
tree.
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For simpler cases, a table-only approach may be sufficient. This is especially
true, if the frequency doesn‘t need to be variable and is a rational fraction of
the FPGA system clock.
The same table may be used for sine (I) and cosine (Q) by using a 90° phase
shifter.
The table may be reduced by a factor of four in size by using the symmetry
properties of sine and cosine.
The additional complexity is usually not worthwhile.
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A more complex version with three DSP slices is also possible.
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Most of the delay elements can sometimes be implemented using the cascade
pipeline registers of the DSP48E1 slice.
Pipelining is not shown for simplicity.
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Most of the delay elements can sometimes be implemented using the cascade
pipeline registers of the DSP48E1 slice.
Above architecture wastes 50% of the DSP slice processing power.
More complex (multi-channel) decimators can use the full potential of the DSP
slices.
Pipelining is not shown for simplicity.
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CIC interpolators/decimators are especially useful when performing large or
non-power-of-2 interpolation/decimation ratios.
CIC interpolators/decimators can also be implemented in logic slices when no
more DSP slices are available. Performance is reduced.
The „comb“ transfer function must usually be compensated for using an
„inverse“ FIR filter.
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GFSK: Gaussian Frequency Shift Keying
The Gaussian filter is used to reduce the channel bandwidth required.
One bit is encoded in one symbol.
The number of samples per symbol (N) generated in a modulator is usually
between 4 and 32.
Modulation is always much easier than demodulation!
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A CORDIC block may be used to obtain magnitude and phase of the complex
base band data (I/Q).
The demodulation itself is quite simple, but the difficulty lies in the auxiliary
functions.
Packet start and end detection may use the power level in the channel and/or
the detection of a preamble.
Frequency offset may be estimated using averageing over a long symbol
sequence (data must be white) or by averaging only the preamble (if it is DC
free).
Symbol timing may be recovered using an edge detector and a symbol timing
update table.
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Before implementing a system, various performance metrics must be verified
by simulation.
The bit-error rate under variable path loss (or input power) is one of the most
important.
All components in the signal path from the transmitter to and including the
demodulator may increase the bit-error rate to an inacceptable level.
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This is an example from the Bluetooth specification.
An interferer transmitting a „carrier“ centered in the channel must be tolerable
up to a certain relative power level.
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This is another example from the Bluetooth specification.
An interferer transmitting a pseudo-random GFSK sequence centered in a
neighboring channel must be tolerable up to a certain relative power level.
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