Emanuel Pollacco Liverpool ACTAR Dec 2008

Preview:

DESCRIPTION

General Electronics for Time projection chambers GET a Multi-Project for IRFU/SPhN, GANIL, GSI, Compostela, CENBG, NSCL/MSU, Darsebury, York. Emanuel Pollacco Liverpool ACTAR Dec 2008. Multi-Project & Multi-Laboratory. ACTAR Active Target Saclay & GANIL & Darsebury, Compostel, GSI, York … - PowerPoint PPT Presentation

Citation preview

General Electronics forGeneral Electronics forTime projection chambersTime projection chambers

GETGETa a

Multi-ProjectMulti-Projectforfor

IRFU/SPhN, GANIL, GSI, Compostela, IRFU/SPhN, GANIL, GSI, Compostela, CENBG, NSCL/MSU, Darsebury, YorkCENBG, NSCL/MSU, Darsebury, York

General Electronics forGeneral Electronics forTime projection chambersTime projection chambers

GETGETa a

Multi-ProjectMulti-Projectforfor

IRFU/SPhN, GANIL, GSI, Compostela, IRFU/SPhN, GANIL, GSI, Compostela, CENBG, NSCL/MSU, Darsebury, YorkCENBG, NSCL/MSU, Darsebury, York

Emanuel Pollacco Liverpool ACTAR Dec 2008

1. ACTAR– Active Target– Saclay & GANIL & Darsebury, Compostel, GSI, York …

2. 2p - TPC– Particle decay– CENBG

3. AT-TPC– Fragmentation (+,-) & Active-Target - Magnet– MSU

4. R3B-TPC– Heavy projectile fragmentation – Magnet*– Saclay & R3B collaboration

5. SAMURAI-TPC– Fragmentation (+,-) - Magnet– Riken, Kyoto University, …

Individually, the labs will not be able to build theinstruments to perform the experiments- Costs/engineers

Multi-Project & Multi-Laboratory

Emanuel Pollacco Liverpool ACTAR Dec 2008

FP6 – ACTAR programPhysics – Yellow Book

Detector Simulations Gases & Gas Amplification tests Electronic system studies

Principle element of the projectTo design and build a prototype for general nuclear physics TPCs electronics.System will be an assessment standard for medium size and high throughput system for Nucl. Phys.

Multi-Project & Multi-LaboratoryNuclear Particle Spectroscopy Direct Reactions Resonant Reactions Decay Spallation Fragmentation

Physics

Program

s

Emanuel Pollacco Liverpool ACTAR Dec 2008

FP6 – ACTAR programPhysics – Yellow Book

Detector Simulations Gases & Gas Amplification tests Electronic system studies

Principle element of the projectTo design and build a prototype for general nuclear physics TPCs electronics.System will be an assessment standard for medium size and high throughput system for Nucl. Phys.

Multi-Project & Multi-Laboratory

Emanuel Pollacco Liverpool ACTAR Dec 2008

FP6 – ACTAR programPhysics – Yellow Book

Detector Simulations Gases & Gas Amplification tests Electronic system studies

Principle element of the projectTo draw a detailed Conceptual Design, Build & Test a prototype for general nuclear physics TPCs electronics.System will be an assessment standard for medium size and high throughput system for Nucl. Phys.

Multi-Project & Multi-LaboratoryMedium Sized SystemMultiple ApplicationsModular/Scale-FreeVery High Dynamic RangeHigh through-put for low occupation events

Nucl. P

hys. B

ased

Emanuel Pollacco Liverpool ACTAR Dec 2008

Emanuel Pollacco

FP6 – ACTAR programPhysics – Yellow Book

Detector Simulations Gases & Gas Amplification tests Electronic system studies

Principle element of the projectTo draw a detailed Conceptual Design, Build & Test a prototype for general nuclear physics TPCs electronics.System will be an assessment standard for medium size and high throughput system for Nucl. Phys.

Multi-Project & Multi-Laboratory

High S/N ratio Low Threshold ()

High Dynamic Range (U) Resoln Charge; Time; Position

Internal Trigger Selective Readout Zero Suppress

Base-Line Correction Time Stamp Automated Calibration

Beam

e

Measure Q(t), X, Yper PadSampling ADC

ano

de

wire

gating grid

ZAP

PA

GET

Emanuel Pollacco Liverpool ACTAR Dec 2008

4.Gbit/sMax in

4x2.Gbit/sMax in

288 Pads/PA1.Gbit/sMax out

FPGA

FPGA

TriggerSelective/Calculated-Read out

FPGA

PCI Express

Event-Building

CoBo

InBo

Time-StampZero SuppressBase-Line CorrOrdering

LVDS

PA

ZA

P-

PA

A Simple ArchitectureTo Give

Scale ‘Free’ Modular

Portable - different labsAutomated

A Simple ArchitectureTo Give

Scale ‘Free’ Modular

Portable - different labsAutomated

PA

PA

ZA

P-

ZA

P

ZA

P-

1.Gbit/sMax

25M

hz -

FA

DC

– 1

2bits

AsAd

PA

-72

PA

-72

PA

-72

PA

-72

AS

IC

Emanuel Pollacco Liverpool ACTAR Dec 2008

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

25M

hz -

FA

DC

- 4

ASIC

AsAd

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

25M

hz -

FA

DC

- 4

ASIC

AsAd

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

25M

hz -

FA

DC

- 4

ASIC

AsAd

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

25M

hz -

FA

DC

- 4

ASIC

AsAd

1152 6x105

Pads Samples

FPGA

MUTANT

LVD

S

LVD

S

Optic

PCIFPGA

InBo

FPGA

CoBo

BEN

G

AN

IL

GA

NIL

MS

U

GA

NIL

/MS

U

CE

NB

G/C

EA

CENBG/CEA Emanuel Pollacco Liverpool ACTAR Dec 2008

PCIFPGA

FPGA

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

25M

hz

-FA

DC

- 4

ASIC

AsAd

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

25M

hz

-FA

DC

- 4

ASIC

AsAd

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

25M

hz

-FA

DC

- 4

ASIC

AsAd

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

25M

hz

-FA

DC

- 4

ASIC

AsAd

3456 Pads

FPGA

Trigger

FPGA

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

25M

hz

-FA

DC

- 4

ASIC

AsAd

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

25M

hz

-FA

DC

- 4

ASIC

AsAd

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

25M

hz

-FA

DC

- 4

ASIC

AsAd

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

25M

hz

-FA

DC

- 4

ASIC

AsAd

FPGA

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

25M

hz

-FA

DC

- 4

ASIC

AsAd

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

25M

hz

-FA

DC

- 4

ASIC

AsAd

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

25M

hz

-FA

DC

- 4

ASIC

AsAd

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

ZA

P-7

2

PA

-72

25M

hz

-FA

DC

- 4

ASIC

AsAd

PCI Exp

BEN

Emanuel Pollacco Liverpool ACTAR Dec 2008

FPGA

14,000 Pads – 7x106 Samples – 150 watts

FPGA

Trigger

FPGAFPGA

FPGA

BEN

OtherSub-systems

IOLANEthernet

PCI Exp

Event Rates 1KHz

FPGA

FPGA

FPGA

FPGA FPGA

FPGAFPGA

FPGA FPGA

FPGAFPGA

FPGA FPGA

Emanuel Pollacco Liverpool ACTAR Dec 2008

ASICfor

GETBased on the T2K

Program

15 GeV/c p-Pb (# 20K events)FE electronics

validated on 1728 channels

HARP test set-up at CERN (oct 07))

SEDI/IRFU

Filter

511 cells

Disc

Pulser

ADC

SlowControlPower

Clock

X 76

SPY

Generic Aspects via Slow Control

Memory Bank

Select External

PA + Filter

Adjustable Sample Size & Frequency ADC parameters

Internal TriggerCalculated Read-Out

Pattern

Pattern/Trigger

PA

PA + Filter1) 72 +/- input2) 16 shaping times 3) Adjustable gain/ch

c0c51

0c

509

ci-

2

c1

c.

cici-

1

ci+

1c

i+2

c0c51

0c

509

ci-

2

c1

c.

cici-

1

ci+

1c

i+2

Channel 0

c0c51

0c

509

ci-

2

c1

c.

cici-

1

ci+

1c

i+2

c0c51

0c

509

ci-

2

c1

c.

cici-

1

ci+

1c

i+2

c0c51

0c

509

ci-

2

c1

c.

cici-

1

ci+

1c

i+2

c0c51

0c

509

ci-

2

c1

c.

cici-

1

ci+

1c

i+2

Channel 1

Channel n

Channel 72

Circular memory

Channels 72Cells 511Write freq: 1 to 100 MHzPrecision: 12 bitsStore: 2msec

Read: 25 MHz FADCPrecision: 12 bitsRead: 128/256/ 511 5/ 10/ 20 µsecRead: 360/720/1440 µsec < AllTotal read Time:Read 36/ 72/ 144 µsec < 10% triggerTotal read Time: 100 to 500µsec

An Overview 2

Clock Syn.External Trigger

CoBo

BEM

VX4

VX4

AsAd

VX5ADCAGETInBo

PCI expMemory

Memory

X36 X9X4

Fast Ethernet Slow Control

NIM Crate(s)

X4 X4

Pulser

V & I

Temp

PAPAPAPAPAPAPAPAPAPA

X104

PC

MUTANT

VX4VX4

Trigger

• A Trigger which gives the Multiplicity– Discriminators LE – adj dead time– Integrated at 20MHz pipe lined to Vertex 5– Adjustable sliding time window –

• ~ Drift Time = T

• Channel fired• ~ Drift Time = T

DRIFT TIMEN

0

0

0

0

8

9

11

4

Trigger

ToT1:104

60% Improvement

1-200MHz

12 & 14 bits

<5kHz

Gains & Losses with an Active Target

X5 to X40 in luminosityVery low EPI thresholds to 0.1 MeVE<ET ~ Efficiency 90% for low energy ET ejectile. Energy resoln < 50keVFor Z=1 & 2, mass & charge resoln for <ET.Angular resoln =Nouvelle method Nouvelle discoveries!Instrument adoptable to a number of techniques

Limited max. energy 4 MeV.A within the TPC.

Coupling to MUST2

No Gamma coincidenceE>ET ~ Efficiency 40%Complex Front End ElectronicsHigh data captureTo develop data analysis techniques for Nucl. Phys

Coupling MUST2 &Physics prog.