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EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 1
EE247Lecture 14
• Data Converters – Data converter testing (continued)
• DNL & SNR, INL & SFDR• Effective number of bits (ENOB)
– D/A converter design• Architectures• Performance
– Static– Dynamic
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 2
Summary Last Lecture• Data Converters
– Static testing (continued)• ………………..• Histogram testing
– Dynamic tests• Spectral testing Reveals ADC errors associated with
dynamic behavior i.e. ADC performance as a function of frequency– Direct Discrete Fourier Transform (DFT) based
measurements utilizing sinusoidal signals– DFT measurements including windowing
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 3
INL & SFDRDNL & SNR
INL & SFDR
• Depends on "shape" of INL
• Rule of Thumb:
SFDR ≅ 20 log(2B/INL)
– E.g. 1LSB INL, 10bSFDR≅60dB
DNL & SNR
Assumptions: • DNL pdf uniform
• No missing code
312
22
21
22
2
DNLSQNR
N
+Δ
⎟⎟⎠
⎞⎜⎜⎝
⎛ Δ
=
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 4
Uniform DNL?
• DNL distribution of 12-bit ADC test chip• Not quite uniform...
-0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.50
50
100
150
200
250
DNL
# of
occ
urre
nces
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 5
Effective Number of Bits (ENOB)
• Is a 12-Bit converter with 68dB SNDR really a 12-Bit converter?
• Effective Number of Bits (ENOB)
Bits0.1102.6
76.168dB02.6
dB76.1
=−=
−= SNDRENOB
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 6
ENOB
• At best, we get "ideal" ENOB only for zero thermal noise, zero DNL, zero INL
• Low noise design is costly 4x penalty in power per (ENOB-) bit or 6dB extra SNDR
• Rule of thumb for good performance /power tradeoff: ENOB < N-1
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 7
ENOB Survey
R. H. Walden, "Analog-to-digital converter survey and analysis," IEEE J. on Selected Areas in Communications, pp. 539-50, April 1999
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 8
Example: ADC Spectral Tests
SFDR
SDR
SNR
Ref: W. Yang et al., "A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input," IEEE J. of Solid-State Circuits, Dec. 2001
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 9
D-to-A Converter Design
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 10
D/A Converter Transfer Characteristics
• An ideal digital-to-analog converter:
– Accepts digital inputs b1-bn
– Produces either an analog output voltage or current
– Assumption • Uniform, binary
digital encoding • Unipolar output
ranging from 0 to VFS
D/A
……..…b1 b2 b3 bn
Vo or Io
MSB LSB
FS
FSN
FS2
N # of bi ts
V ful l scale output
min. s tep size 1LSB
V2
Vor N log resolut ion
=
=
Δ = →
Δ =
= →Δ
Nomenclature:
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 11
D/A Converters• D/A architecture examples
– Resistor string DAC– Charge Redistribution DAC– Current source type
• Static performance– Limited by component matching– Architectures
• Unit element• Binary weighted• Segmented
– Dynamic element matching
• Dynamic performance– Limited by timing errors causing glitches
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 12
D/A Converters
• Comprises voltage or charge or current based elements
• Examples for above three categories:– Resistor string voltage – Charge redistribution charge– Current source type current
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 13
Resistor String DAC
R
R
R
R
R
R
R
R
Voltage based:
A B-bit DAC requires: 2B
resistors in seriesAll resistors equal
Generates 2B
equally spaced voltages ready to be chosen based on the digital input word
Vref
3-Bit Resistor String DAC
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 14
R-String DACExample
Example:
• Input code: [d2 d1 d0]=101
Vout= 5Vref /8
• Assuming switch resistance << R:
τsettling = (3R||5R) x C=0.23 x 8RC Vref /8
2Vref /8
3Vref /8
4Vref /8
5Vref /8
6Vref /8
7Vref /8
C
R
Vref
Vout = 5Vref /8
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 15
R-String DAC• Advantages:
– Takes full advantage of availability of almost perfect switches in MOS technologies
– Simple, fast for <8-10bits– Inherently monotonic– Compatible with purely digital
technologies
• Disadvantages:– 2B resistors & ~2x2B switches for B
bits High element count & large area for B >10bits
– High settling time for high resolution DACs:τmax ~ 0.25 x 2B RC
C
Ref:M. Pelgrom, “A 10-b 50-MHz CMOS D/A Converter with 75-W Buffer,” JSSC, Dec. 1990, pp. 1347
Vref
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 16
R-String DAC
•Choice of resistor value:–Since maximum output settling
time:
τmax ~ 0.25 x 2B RC–Choice of resistor value directly
affects DAC maximum operating speed
–Power dissipation: function of Vref
2/ (Rx2B)
Tradeoff between speed and power dissipation
C
Vref
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 17
R-String DAC
• Resistor type:– Choice of resistive material
important
– Diffusion type R high temp. co. & voltage co. • Results in poor INL/DNL
– Better choice is poly resistor beware of poly R 1/f noise
– At times, for high-frequency & high performance DACs, metal R (beware of high temp. co.) or thin film R is used
C
Vref
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 18
R-String DACLayout Considerations
• Number of resistor segments 2B
–E.g. 10-bit R-string DAC 1024 resistors
• Low INL/DNL dictates good R matching
• Layout quite a challenge
–Good matching mandates all R segments either vertical or horizontal - not both
–Matching of metal interconnect and contacts–Need to fold the string
• Difficult to match corner segments to rest• Could result in large INL/DNL
........
R-S
tring
Lay
out
Corner
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 19
R-String DACIncluding Interpolation
Resistor string DAC+ Resistor string interpolator increases resolution w/o drastic increase in complexitye.g. 10bit DAC (5bit +5bit 2x25=26 #of Rs) instead of direct 10bit 210
Considerations:Main R-string loaded by the interpolation stringLarge R values for interpolating string less loading but lower speedCan use buffers
Vout
Vref
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 20
R-String DACIncluding Interpolation
Use buffers to prevent loading of the main ladder
Issues:
Buffer DC offset Buffer limited
bandwidth effect on overall speed
Vref
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 21
Charge Based: Serial Charge Redistribution DACSimplified Operation
• Conversion sequence:– Initialize: Discharge C2 & charge C1 to VREF S2& S4 closed– Charge share: close S1 VC2=VC1=VREF/2
Nominally C1=C2
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 22
• Conversion sequence:–Next cycle
• If S3 closed VC1=0 then when S1 closes VC1 = VC2 = VREF/4• If S2 closed VC1=VREF then when S1 closes VC1 =VC2 =VREF/2+VREF/4
Nominally C1=C2
Serial Charge Redistribution DACSimplified Operation (Cont’d)
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 23
Serial Charge Redistribution DAC• Nominally C1=C2
• Conversion sequence:– Discharge C1 & C2 S3&
S4 closed– For each bit in succession
beginning with LSB, b1:• S1 open- if bi=1 C1
precharge to VREF if bi=0 discharged to GND
• S2 & S3 & S4 open- S1 closed- Charge sharing C1 & C2
½ of precharge on C1 +½ of charge previously stored on C2 C2
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 24
Serial Charge Redistribution DACExample: Input Code 101
• Example input code 101 output (1/8 +0/8 +4/8 )VREF =5/8 VREF
• Very small area• N redistribution cycles for N-bit conversion quite slow
b3 b2 b1
LSB MSB
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 25
Parallel Charge Scaling DAC
Make Cx & Cy function of incoming DAC digital word
Vref
Vout
CCxCyout ref
CxV VCx Cy C+
=+
• DAC operation based on capacitive voltage division
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 26
Parallel Charge Scaling DAC
• E.g. “Binary weighted”
• B+1 capacitors & switches (Cs built of unit elements
2B units of C)
CC2C4C8C2(B-1) C
Vref
Vout
reset
b0 (lsb)b1b2b3bB-1 (msb)
B 1i
ii 0out refB
b 2 CV V
2 C
−
==∑
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 27
Charge Scaling DACExample: 4Bit DAC- Input Code 1011
CC2C4C8C
Vref
Vout
b0 (lsb)b1b2b3
CC2C4C8C
Vref
Voutreset
b0 (lsb)b1b2b3
b- Charge phasea- Reset phase
0 1 3out ref ref4
2 C 2 C 2 C 11V V V2 C 16
=+ +=
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 28
Charge Scaling DAC
• Sensitive to parasitic capacitor @ output– If Cp constant gain error– If Cp voltage dependant DAC nonlinearity
• Large area of caps for high DAC resolution (10bit DAC ratio 1:512)
• Monotonicity depends on element matching (more later)
refP
B
B
i
ii
out VCC
CbV
+=∑
−
=
2
21
0
CC2C4C8C2(B-1) C
Vref
Vout
reset
b0 (lsb)b1b2b3bB-1 (msb)
CP
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 29
Parasitic InsensitiveCharge Scaling DAC
• Opamp helps eliminate the parasitic capacitor effect by producing virtual ground at the sensitive node since CP has zero volts at start & end
– Issue: opamp offset & speed
C2C4C8C2(B-1) C
Vref
Vout
reset
b0 (lsb)b1b2b3bB-1 (msb)
CP
CI
-
+
CI
B 1 B 1i i
i iBi 0 i 0
out ref I out refBI
b 2 C b 2V V , C 2 C V V
C 2
− −
= == = → =∑ ∑
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 30
Charge Scaling DACIncorporating Offset Compensation
• During reset phase:– Opamp disconnected from capacitor array via switch S3– Opamp connected in unity-gain configuration (S1)– CI Bottom plate connected to ground (S2)– Vout ~ - Vos VCI = -Vos
• This effectively compensates for offset during normal phase
C2C4C8C2(B-1) C
Vref
Vout
reset
b0 (lsb)b1b2b3bB-1 (msb)
CP -
+
CI
osV
reset
reset
S1
S2
S3
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 31
Charge Scaling DACUtilizing Split Array
• Split array reduce the total area of the capacitors required for high resolution DACs
– E.g. 10bit regular binary array requires 1024 unit Cs while split array (5&5) needs 64 unit Cs
– Issue: Sensitive to parasitic capacitor
series
al l LSB array CC C
all MSB array C=∑
∑
C 2C 4C
Vref
Vout
reset
b5b4b3b2
+
-
8/7C
C 2C 4C
b1b0
C
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 32
Charge Scaling DAC
• Advantages:– Low power dissipation capacitor array does not dissipate DC power– Output is sample and held no need for additional S/H– INL function of capacitor ratio– Possible to trim or calibrate for improved INL– Offset cancellation almost for free
• Disadvantages:– Process needs to include good capacitive material not
compatible with standard digital process– Requires large capacitor ratios– Not inherently monotonic (more later)
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 33
Segmented DACResistor Ladder (MSB) & Binary Weighted Charge Scaling (LSB)
CC2C4C8C32 C
reset
b1b2b3b5
16C
b4
Vout
b0
..........
SwitchNetwork
6bitresistorladder
6-bitbinary weighted charge redistribution DAC
• Example: 12bit DAC
– 6-bit MSB DACR- string
– 6-bit LSB DAC binary weighted charge scaling
• Complexity much lower compared to
full R-string– Full R string
4096 resistors– Segmented 64
R + 7 Cs (64 unit caps)
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 34
Current based DACUnit Element Current Source DAC
• “Unit elements” or thermometer• 2B-1 current sources & switches • Suited for both MOS and BJT technologies• Monotonicity does not depend on element matching • Output resistance of current source gain error
– Cascode type current sources higher output resistance less gain error
Iref Iref
Iout
IrefIref
……………
……………Iref
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 35
Current Source DACUnit Element
• Output resistance of current source gain error problemUse transresistance amplifier- Current source output held @ virtual ground - Error due to current source output resistance eliminated- New issues: offset & speed of the amplifier
Iref IrefIrefIref
……………
……………
Vout
R
-
+
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 36
Current Source DACBinary Weighted
• “Binary weighted”• B current sources & switches (2B-1 unit current
sources but less # of switches)• Monotonicity depends on element matching
4 Iref Iref
Iout
2Iref2B-1 Iref
……………
……………
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 37
R-2R Ladder Type DAC
• R-2R DAC Basics
– Simple R network divides both voltage & current by 2
R
V
V/2
2R 2RI I/2 I/2
Increase # of bits by replicating circuit
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 38
R-2R Ladder DAC
VB
2R 2R
Emitter-follower added to convert to high output impedance current sources
Series switch resistance does not impair performance
2R 2R 2R 2RR R R R
VEE
Iout
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 39
R-2R Ladder DACHow Does it Work?
VB
Consider a simple 3bit R-2R DAC:
2R 2R 2R 2RR R
VEE
Iout
AunitAunit2Aunit4Aunit
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 40
R-2R Ladder DACHow Does it Work?
VB
Simple 3bit DAC:1- Consolidate first two stages:
2R 2R 2R 2RR R
VEE
ITI1I2I3
AunitAunit2Aunit4Aunit
QTQ1Q2Q3 VB
2R 2R RR R
VEE
I1+ITI2I3
2Aunit2Aunit4Aunit
Q2Q3
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 41
R-2R Ladder DACHow Does it Work?
Simple 3bit DAC-2- Consolidate next two stages:
VB
2R 2R RR R
VEE
I1+ITI2I3
2Aunit2Aunit4Aunit
Q2Q3VB
2R RR
VEE
I2+I1+ITI3
4Aunit4Aunit
Q2Q3
Total Total Total3 2 1 3 2 1T
I I II I I I I , I , I2 4 8= + + → = = =
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 42
R-2R Ladder DACHow Does it Work?
VB
Consider a simple 3bit R-2R DAC:
2R 2R 2R 2RR R
VEE
II2I4I
2I4I
Iout
AunitAunit2Aunit4Aunit
Ref: B. Razavi, “Data Conversion System Design”, IEEE Press, 1995, page 84-87
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 43
R-2R Ladder DAC
VB
2R 2R
Transresistance amplifier added to:- Convert current to voltage- Generate virtual ground @ current summing node so that output impedance of current sources do not cause error- Issue: error due to opamp offset
Vout
R-
+
2R 2R 2R 2RR R R R
VEE
II2I4I8I16I
2I4I8I16I
RTotal
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 44
R-2R Ladder DACOpamp Offset Issue
out inos os Total
Totalout inos os
Totalout inos os Total
Totaloutos
R1V V R
If R l arg e,
V V
If R not l arg eR1V V R
Pr oblem :
Since R is code dependant
V would be code dependant
Gives r ise to INL & DNL
⎛ ⎞+= ⎜ ⎟⎝ ⎠
=
→ ≈
=⎛ ⎞+→ = ⎜ ⎟⎝ ⎠
→
→
Vout
R
-
+
RTotal
osV
Offset Model
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 45
R-2R LadderSummary
• Advantages:– Resistor ratios only x2– Does not require precision capacitors
• Disadvantages:– Total device emitter area AE
unitx 2B
Not practical for high resolution DACs– INL/DNL error due to amplifier offset
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 46
Static DAC Errors -INL / DNLStatic DAC errors mainly due to component mismatch
– Systematic errors• Contact resistance• Edge effects in capacitor arrays• Process gradients• Finite current source output resistance
– Random variations• Lithography etc…• Often Gaussian distribution (central limit theorem)
*Ref: C. Conroy et al, “Statistical Design Techniques for D/A Converters,” JSSCAug. 1989, pp. 1118-28.
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 47
Current Source DACDNL/INL Due to Element Mismatch
• Simplified example:– 3-bit DAC– Assume only two of the current sources mismatched (# 4 & #5)
Iref IrefIrefIref Iref
Iref +ΔIIref -ΔI
Vout
-
+
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 48
max
segment[ m] V [ LSB]DNL[ m]
V [ LSB]
segment[4] V [ LSB]DNL[4]
V [ LSB]
( I I )R IR
IR
DNL[4] I / I [ LSB]
( I I )R IRDNL[5]
IR
DNL[5] I / I[ LSB]
INL I / I [ LSB]
−=
−=
− Δ −=
= −Δ
+ Δ −=
= Δ
→ = −Δ000 001 010 011 100 101 110 111
DigitalInput
Analog Output
7 Iref R
6
5
4
3
2
1xIref R
0
Current Source DACDNL/INL Due to Element Mismatch
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 49
Component MismatchProbability Distribution Function
• Component parameters Random variables
• Each component is the product of many fabrication steps• Most fabrication steps includes random variations
Overall component variation product of several random variables
Assuming each of these variables have a uniform distribution:Joint pdf of a random variable affected by two uniformly distribution is the convolution of the two uniform pdfs…….
pdf [f(x1)]
*
*
pdf [f(x2)] pdf [f(x1,x2)]
pdf [f(x1,x2)] pdf [f(x3,x4)]
..……..pdf [f(xm,xn)]
*Gaussian pdf
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 50
Gaussian Distribution
-3 -2 -1 0 1 2 30
0.1
0.2
0.3
0.4
(x-μ) /σ
Prob
abilit
y de
nsity
p(x
)
( )22
2
x2
2 2
variance
is the expected value and
1p( x ) e2
where:
standard deviation : E( X )
μσ
μ
πσ
σ μσ
−−
→
=
= −
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 51
Yield
( )2xX
2
X
P X x X
1e dx
2
Xerf
2
π
+ −
−
− ≤ ≤ + =
=
⎛ ⎞= ⎜ ⎟⎝ ⎠
∫
0
0.1
0.2
0.3
0.4
Pro
babi
lity
dens
ity
p(x)
0 0.5 1 1.5 2 2.5 30
0.20.40.60.8
1
X/σ
38.3
68.3
95.4
P(-
X ≤
x ≤
+X)
In most cases we are interested in finding the percentage of components (e.g. R) falling within certain bounds:
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 52
YieldX/σ P(-X ≤ x ≤ X) [%]
0.2000 15.85190.4000 31.08430.6000 45.14940.8000 57.62891.0000 68.26891.2000 76.98611.4000 83.84871.6000 89.04011.8000 92.81392.0000 95.4500
X/σ P(-X ≤ x ≤ X) [%]
2.2000 97.21932.4000 98.36052.6000 99.06782.8000 99.48903.0000 99.73003.2000 99.86263.4000 99.93263.6000 99.96823.8000 99.98554.0000 99.9937
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 53
Example
• Measurements show that the offset voltage of a batch of operational amplifiers follows a Gaussian distribution with σ = 2mV and μ = 0.
• Fraction of opamps with |Vos| < 6mV:– X/σ = 3 99.73 % yield
• Fraction of opamps with |Vos| < 400μV:– X/σ = 0.2 15.85 % yield
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 54
Component Mismatch
RR
Δ
10000
100
200
300
400
No.
of r
esis
tors
1004 1008 1012996992988R[ ]Ω
Example: Resistors layouted outside-by-side
E.g. Let us assume in this example 1000 Rs measured & 68.5% within +-4OHM or +-0.4% of average
1σ for resistors 0.4%
After fabrication large # of devices measured & graphed typically if sample size large shape is Gaussian
…….…….
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 55
Component Mismatch
1 2
1 2
2dRR
R RR
2
dR R R
1Area
σ
+=
= −
∝
RR
Δ
00
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
Prob
abilit
y de
nsity
p(x
)
σ 2σ 3σ−σ−2σ−3σdRRFor typical technologies & geometries
1σ for resistors 0.02 to 5%
In the case of resistors σ is a function of area
Example: Two resistors layouted out side-by-side
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 56
DNL Unit Element DAC
i i refR IΔ =
DNL of unit element DAC is independent of resolution!
E.g. Resistor string DAC:
Iref
Vref
B
i
i
2 1
io
median ref median B
i i re f
i mediani
median
i median
imedian median
DNL dRR
RR I where R
2
R I
DNL
R R dR dR
R R R
σ σ
−
Δ = =
Δ =
Δ − Δ=
Δ
−= = ≈
=
∑
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 57
DNL Unit Element DAC
Example:If σdR/R = 0.4%, what DNL spec goes into the datasheet so that 99.9% of all converters meet the spec?
To first order DNL of unit element DAC is independent of resolution!Note similar results for other unit-element based DACs
E.g. Resistor string DAC:
i
i
DNL dRR
σ σ=
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 58
YieldX/σ P(-X ≤ x ≤ X) [%]
0.2000 15.85190.4000 31.08430.6000 45.14940.8000 57.62891.0000 68.26891.2000 76.98611.4000 83.84871.6000 89.04011.8000 92.81392.0000 95.4500
X/σ P(-X ≤ x ≤ X) [%]
2.2000 97.21932.4000 98.36052.6000 99.06782.8000 99.48903.0000 99.73003.2000 99.86263.4000 99.93263.6000 99.96823.8000 99.98554.0000 99.9937
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 59
DNL Unit Element DACExample:If σdR/R = 0.4%, what DNL spec goes into the datasheet so that 99.9% of all converters meet the spec?
Answer:From table: for 99.9%
X/σ = 3.3σDNL = σdR/R = 0.4%3.3 σDNL = 1.3%
DNL= +/- 0.013 LSB
E.g. Resistor string DAC:
i
i
DNL dRR
σ σ=
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 60
DAC INL Analysis
B
A
N=2B-1n
n
N
Out
put [
LSB
]
Input [LSB]
E
Ideal VarianceA=n+E n n.σε
2
B=N-n+E N-n (N-n).σε2
E = A-n r =n/N N=A+B= A-r(A+B)= A (1-r) -B.r
Variance of E:σE
2 =(1-r)2 .σΑ2 + r 2 .σB
2
=N.r .(1-r).σε2
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 61
DAC INL
• Error is maximum at mid-scale (N/2):
• INL depends on DAC resolution and element matching σε
• While σDNL = σε is to first order independent of DAC resolution and is only a function of element matching
Ref: Kuboki et al, TCAS, 6/1982
2 2E
2E
BINL
B
n1n
Nd
To find max. variance : 0dn
n N / 2
12 1
2 with N 2 1
ε
ε
σ σ
σ
σ σ
⎛ ⎞−= ×⎜ ⎟⎝ ⎠
=
→ =
= −
= −0.5 1
0
(2B-1)0.5/2
0n/N
σINL/σε
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 62
Untrimmed DAC INLExample:
Assume the following requirement for a DAC:σINL = 0.1 LSB
Then:σε = 1% B = 8.6σε = 0.5% B = 10.6σε = 0.2% B = 13.3σε = 0.1% B = 15.3
⎥⎦
⎤⎢⎣
⎡+≅
−≅
ε
ε
σσ
σσ
INL
BINL
B 2log22
1221
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 63
Simulation Example
σε = 1%B = 12Random # generator used in MatLab
Computed INL:σINL = 0.3 LSB(midscale)
500 1000 1500 2000 2500 3000 3500 4000-1
0
1
2
bin
DN
L [L
SB
]12 Bit converter DNL and INL
-0.04 / +0.03 LSB
500 1000 1500 2000 2500 3000 3500 4000-1
0
1
2
bin
INL
LSB
] -0.2 / +0.8 LSB
Recommended