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7/28/2019 Ececoursehandout II
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Srinivasan Engineering College, Perambalur
Odd Semester 2011 2012
Course Handout
Subject Code : MA 1201
Subject Title : TRANSFORMS AND PARTIAL DIFFERENTIAL EQUATIONS
Staff Name : R.Vijaya Kumar & A.Padma
Scope and Objective of the Course:
1. To highly dissipative PDE systems with input constraints.
2. To develop the skill of the students in the area of transforms.
3. To get know about the basics of organic chemistry.
Text book(s) [TB]
1. Dr.A.SINGARAVELU, Transforms and Partial Differential Equations, Meenakshi Agency edition 2009
Course Plan / Schedule:
S.No Topics to be covered Learning objectives Ref. to Text
Book
No.
of
lectu
res
1 Periodic function, Dirichlet Conditionsand General Fourier Series, Problems
To find the fourier series under theintervals (0, 2) and (0, l)
TB (1.1-1.34)4
2 Odd, even functions and Half range sineseries
To find the fourier series under theintervals (-,) and (-l, l)
TB(1.34-1.138)4
3 Half range cosine series and Complexform of Fourier series
To find the cosine series functions TB(1.139-1.176)
3
4Parsevals Identity and Harmonic
Analysis
To obtain fourier series expansionby using Parsevals theorem
TB(1.176-1.201) 3
5 Fourier Integral theorem (without proof)
and Fourier Transform pair
To easy to find solution of partial
differential equations
TB(2.1-2.33)3
6 Fourier Sine and Cosine transforms and
their properties
To find sine and cosine transform by
using properties
TB(2.33-2.89)4
7Convolution theorem and Parsevals
Identity
It is easy to obtain sine and cosinetransform by convolution theorem.
TB(2.89-2.108)
2
8 Fourier cosine and sine transform and
inversion formula for fourier cosine and
sine transform
To obtain sine and cosine transform
for the given function by using
formula.
TB- (2.34-2.82)
3
9 Formation of partial differential equationsby elimation of arbitrary constants and
functions
To form the pde by eliminatingarbitrary constants and functions
TB-(3.1-3.41)4
10 Solution of standard types of first order
partial differential equations
To solve first order partial
differential equations
TB-(3.4-3.108)4
11Lagranges linear equation
To solve Lagranges linear equationby using method of multipliers.
TB(3.108-3.131)
3
12 Linear partial differential equations of thesecond and higher order with constant co-
efficients
To find the complete solution of thedifferential equation.
TB-(3.132-3.163) 4
13Classification of second order quasi linear
partial differential equations
To learn nature of the partial
differential equation like ellipse,parabola, circle etc.
TB-(4.1.-4.12)
3
14 Solutions of one dimentional wave
equation.
To find the frequency of fibratingstring.
TB-(4.13-4.56)3
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15 one dimentional equation. of heatconduction
To find the temperature of theparticle.
TB-(4.57-4.72)3
16 Steady state solution of two dimentionalheat equation
To find heat equation in steady statecase
TB-(4.73-4.132)
4
17 Fourier series solution in Cartesian co-ordinates
To find the solution of fourier seriesin Cartesian co-ordinates
TB-(4.134-4.147) 3
18
Z-Transform and elementary properties
Difference equation are also based
on discrete system and theirsolutions and analysis are carried out
by Z-transform.
TB-(5.1-5.52)
3
19Inverse Z-Transform
To learn what are the easy methods
to find inverse Z- transform.
TB-(5.54-5.96)4
20
Convolution theorem
It plays an important role in the
solution difference equation and inprobability problems
TB(5.118-
5.128) 3
21Formation of difference equations.
To form the difference equation bygiven family of curves
TB(5.96-5.113)3
22 Solution of difference equations using Z-Transform
To find the solution of differenceequation by using Z-transform
TB(5.96-5.113) 2
Total number of classes planned: 72
Evaluation scheme Internal Assesment
I. Assignment topic:
Problems based on Convolution theorem.
Problems based on Parsevals Identity.
Timings for chamber consultation: Students should contact the Course Instructor in her/his chamber during lunchbreak.
Notices: All notices will be displayed on the Department Notice Board.
STAFF SIGNATURE HOD
EC
No.
Evaluation
Components
Duration Weightage Date & Time Venue
1 Unit Test 1 1.30hr 30% 19.7.12-25.7.12
Tobe
announced
later
2 Unit Test 2 1.30hr 8.8.12 16.8.12
3 Unit Test 3 1.30hr 24.9.12 29.9.12
4 Model Exam 1 3hr 40% 3.9.12 10.9.12
5 Model Exam 2 3hr 10.10.12 17.10.12
6 Assignment 15 days 10%
7 Attendance
Percentage
Continuous 20%
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COURSE HANDOUT
Subject code : CS1201
Subject Title : Data Structures
Staff name : P.MANJULA
Scope and Objective of the Subject:
To provide an in-depth knowledge in problem solving techniques and data structures
To learn the systematic way of solving problems
To understand the different methods of organizing large amounts of data
To learn to program in C
To efficiently implement the different data structures
To efficiently implement solutions for specific problems
Text book(s) [TB]
1. Weiss, M.A., Data Structures and Algorithm Analysis in C, 2nd Edition,Pearson Education,
2005.
Reference Books [RB]:
1. Aho, A. V., Hopcroft, J.E., and Ullman, J.D., Data Structures and Algorithms, 1st Edition,
Pearson Education, 2003.
2. Ellis Horowitz, Sartaj Sahni and Sanguthevar Rajasekaran, Computer Algorthims/C++,
Universities Press (India) Private Limited, 2nd Edition, 2007.
Course Plan / Schedule:
S.
No
Topics to be covered Learning objectives Ref. to Text
Book
No. of
lectures
1 Analysis of algorithm To know what is
algorithm and analyze
the running timecalculations for
algorithm
R2(1.1
-1.1.6 )
3
2 Time Complexity and Space
complexity
It is used to calculate
the amount of time and
space the algorithm
takes to execute
R1
(1.3.1,1.3.3,1.
3.5-1.3.6)
3
3 Amortized time complexity
and Asymptotic notation.
It explains the various
notations in analyzing
the efficiency of
Algorithm
R2
(1.3.2,1.3.4)
2
4 Arrays and Structures It defines the syntax for creating, declaring and
initializing the arrays
T1(3.1,3.2) 2
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and structures in
implementation of
various Data Structures
5 Stacks and its applications It I a type of data
Structure which
explains how data are
implemented in stack
T1(3.3-3.4) 3
6 Queues and its Representations It I a type of data
Structure which
explains how data are
implemented in Queue
T1(3.4, 6.1-
6.4)
3
7 Lists and Linked Lists It I a type of data
Structure which
explains how data are
implemented in Linked
List
T1(3.2) 3
8 Binary Trees It is a Tree with only
two children and itexplains thevarious
representation in
Binary trees
T1(4.2) 2
9 Operations on Binary Trees It includes the various
operations like
inserting, deleting,
searching and sorting a
node in a tree.
T1(4.3-4.4) 4
10 Binary Tree Traversal Traversal refers to
visiting each node in a
tree, and it includesvarious methods of
traversing.
T1(4.6) 2
11 Huffman Algorithm It is an encoding
algorithm which briefs
about loseless data
compression.
T1(10.1.2) 2
12 Sorting Techniques Sorting refers to
arrange the data in a
order, and it includes
various methods in
sorting
T1(7.1-7.7, .
11)
4
13 Searching Techniques Searching refers to find
a particular data in the
list ,and it includes
various methods in
searching
R2(3.3) 1
14 Tree Traversal Traversal refers to
visiting each node in a
tree. It includes
inorder,preorder and
postorder method
T1(4.1) 3
15 Hashing Hashing is a technique
which finds a value or
places a value in hash
T1(5.1-5.6) 3
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table using hash key
through hash function
16 Graphs and its Representations Graph is a collection of
vertices and edges. It
explains how graph is
represented.
T1(9.1-9.4) 3
17 Topological Sort(Transitive
Closure)
A type of sorting which
examines the neighbour
node in a tree and
results in Transitive
Closure.
T1(9.2) 2
18 Shortest Path Algorithms
(Unweighted, Dijisktra)
Various algorithms
that are employed in
finding the shortest
path from the starting
node to the destination
node.
T1(9.3) 3
19 Minimum Spanning TreeAlgorithm (Prims,Kruskal)
It is a tree which hasonly the edges with
minimum cost. Various
algorithms are used in
finding Minimum
Spanning Tree.
T1(9.5) 3
20 Graph traversal Traversal refers to
visiting each vertex in a
Graph. It includes
Depth First search and
Breadth First search.
T1(9.6) 2
21 General Lists and itsOperations
It explains the variousoperations like
creating, inserting
deleting and searching
an element in the List.
R1(2.1-2.2) 2
22 Linked List Representation It explains the various
operations like
creating, inserting
deleting and searching
an element in the
Linked List
R1(4.1-4.4) 2
23 Automatic List
Management(Reference Count
Method)
It Briefly explains the
Reference count
method for freeing
nodes and managing
the List..
R1(12.1-12.2) 3
24 Garbage Collection It explains about
collecting all the
unwanted free nodes
R1(12.3) 1
25 Collection and Compaction It explains about
collecting all the
unwanted free nodes
R1(12.4) 1
Total number of classes planned: 60
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Evaluation scheme Internal Assessment
II. Assignment topic:
Kruskal and Prims Algorithm
Huffman Algorithm
Question Bank will be issued by the instructor within one week from the starting
date.
Two marks (Part A) question and answers will be provided on completion of eachunit.
Timings for chamber consultation: Students should contact the Course Instructor in her/his
chamber during lunch break.
STAFF SIGNATURE HOD
COURSE HANDOUT
EC
No.
Evaluation
Components
Duration Weightage Date & Time Venue
1 Unit Test 1 1.30hr 30% 19.7.12-25.7.12
Tobe
announced
later
2 Unit Test 2 1.30hr 8.8.12 16.8.12
3 Unit Test 3 1.30hr 24.9.12 29.9.12
4 Model Exam 1 3hr 40% 3.9.12 10.9.12
5 Model Exam 2 3hr 10.10.12 17.10.12
6 Assignment 15 days 10%
7 Attendance
Percentage
Continuous 20%
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Subject code : EC 2203
Subject Title : Digital Electronics
Staff name : ARIVASANTH.M
A.BALASUBRAMANIYAN
Scope and Objective of the Subject:
To learn the basic methods for the design of digital circuits and provide the fundamental
concepts used in the design of digital systems.
To introduce basic postulates of Boolean algebra and shows the correlation between
Boolean expressions
To introduce the methods for simplifying Boolean expressions
To outline the formal procedures for the analysis and design of combinational circuits and
sequential circuits.
To introduce the concept of memories and programmable logic devices.
To illustrate the concept of synchronous and asynchronous sequential circuits
Text book(s) [TB]
1. M. Morris Mano, Digital Design, 3rd Edition, Prentice Hall of India Pvt. Ltd., 2003 /
Pearson Education (Singapore) Pvt. Ltd., New Delhi, 2003.
2. S. Salivahanan and S. Arivazhagan, Digital Circuits and Design, 3rd Edition., Vikas
Publishing House Pvt. Ltd, New Delhi, 2006
Reference book(s) [RB]
1. John F.Wakerly, Digital Design, Fourth Edition, Pearson/PHI, 2006
2. John.M Yarbrough, Digital Logic Applications and Design, Thomson Learning, 2002.
3. Charles H.Roth. Fundamentals of Logic Design, Thomson Learning, 2003.4. Donald P.Leach and Albert Paul Malvino, Digital Principles and Applications, 6 th Edition,
TMH, 2003.
5. William H. Gothmann, Digital Electronics, 2nd Edition, PHI, 1982.
6. Thomas L. Floyd, Digital Fundamentals, 8th Edition, Pearson Education Inc, New Delhi,
2003
7. Donald D.Givone, Digital Principles and Design, TMH, 2003.
Course Plan / Schedule:
S.No Topics to be covered Learning objectives
Ref. to Text
Book
No. of
lecturesUNIT-I-MINIMIZATION TECHNIQUES AND LOGIC GATES
1Boolean postulates and laws,
De-Morgans Theorem
To study basic of Boolean
postulates,De- Morgans
Theorem
T2 40-57
1
2Principle of Duality, Boolean
expression
Analysis of Principle of
Duality, Boolean expression1
3
Minimization of Boolean
expressions, Minterm
,Maxterm
To minimize Boolean
expressions using min and max
terms
1
4 Sum of Products (SOP),Product of Sums (POS) Reduce the Boolean expressionusing SOP and POS 1
5Karnaugh map Minimization,
Dont care conditions
Reduce the Boolean expression
using K map
T2 57-59
T2 64-661
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6Quine-McCluskey method of
minimization
Reduce the Boolean expression
using tabulation methodT2 67-68 1
7
AND,OR,NOT,NAND,NOR,E
xOR and ExNOR,
Implementations
of Logic Functions using gates
Implementation of AND, OR,
NOT, NAND, NOR, ExOR
and ExNOR
T2 78-98 1
8
NANDNOR
implementations, Multi level
gate implementations
Implementation of NANDNOR logic functions
T2 99-108 1
9Multi output gate
implementations
Implementation of Multi output
gate logic functionsT2 108-110 1
10
TTL and CMOS Logic and
their characteristics, Tristate
gates
To study the characteristics of
TTL and CMOS Logic and
Tristate gates
T2 121-135 1
11 ProblemsProblems in Minimization of
Boolean expressionsT2 45-50 1
12 ProblemsProblems in Karnaugh map
MinimizationT2 59-64 1
13 ProblemsProblems in Quine-McCluskey
methodT2 68-72 1
14 Problems Problems in SOP and POS T2 66-67 1
15 ProblemsProblems in NANDNOR
implementationsT2 103-108 1
UNIT-II COMBINATIONAL CIRCUITS
16Design procedure, Half adder ,
Full Adder
To design Half adder and Full
AdderT2 161-165 1
17Half subtractor , Full
subtractor
To design Half subtractor
andFull subtractorT2 165-168 1
18Parallel binary adder, parallel
binary Subtractor
To design Parallel binary
adder, parallel binary
Subtractor
T2 168-171 1
19Fast Adder, Carry Look Ahead
adder
To design Fast Adder, Carry
Look Ahead adderT2 173-175 1
20
Serial Adder/Subtractor, BCD
adder, Binary Multiplier,
Binary Divider
To design Serial
Adder/Subtractor, BCD adder,
Binary Multiplier, Binary
Divider
T2 175-186 1
21
Multiplexer/ Demultiplexer,
Decoder and Encoder
To design
Multiplexer/Demultiplexer,Decoder and Encoder
T2 187-219
T2 220-226 1
22Parity checker,Parity
generators
To design Parity checker,Parity
generatorsT2 227-228 1
23Code converters, Magnitude
Comparator
To design Code converters,
Magnitude ComparatorT2 233-246 1
24 ProblemsProblems in Serial
Adder/SubtractorT2 178
1
25 ProblemsProblems in Multiplexer/
DemultiplexerT2 194-196 1
26 Problems
Problems in Decoder and
Encoder T2 212
1
28 ProblemsProblems in Carry Look Ahead
adderT2 174
1
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29 ProblemsProblems in Parallel binary
adderT2 172
1
UNIT-III SEQUENTIAL CIRCUITS
30Latches, Flip-flops - SR, JK,
D, T, and Master-Slave
To analyze Latches, Flip-flops
- SR, JK, D, T, and Master-
Slave
T2 255-277
1
31Characteristic table andequation,
Application table, Edge
triggering, Level Triggering
To study the Characteristictable and equation, Application
table, Edge triggering, Level
Triggering
1
33
Realization of one flip flop
using other flip flops, Serial
adder/subtractor
To realize one flip flop using
other flip flops and Serial
adder/subtractor
T2 277-289 1
34
Asynchronous Ripple or serial
counter, Asynchronous
Up/Down counter
To design Asynchronous
Ripple or serial counter,
Asynchronous Up/Down
counter
T2 293-295
T2 304-3051
35
Synchronous counters,Synchronous Up/Down
Counters, Programmable
counters
To design Synchronous
Up/Down Counters,
Programmable counters
T2 309-311 1
36
Design of Synchronous
counters: Modulon counter,
state diagram, State tableTo design Synchronous
counters and minimize
Techniques
T2 311-336
1
37
State minimization State
assignment Excitation table
and maps-Circuit
Implementation
1
38
Registers shift registers -
Universal shift registersTo study and analyze of
Registers and Counters
T2 345-361 1
39Shift register counters, Ring
counter, Shift countersT2 361-373 1
40 Sequence generators To study Sequence generators T2 373-381 1
41 ProblemsProblems in Realization of one
flip flop using other flip flopsT2 289 1
42 Problems Problems in serial counter
T2 340-343
1
43 Problems Problems in AsynchronousUp/Down counter 1
44 ProblemsProblems in Design of
Synchronous counters1
45 Problems Problems in Modulon counter 1
UNIT-IV MEMORY DEVICES
46Classification of memories,
ROM - ROM organization
To study Classification of
memories and I/O operation
T2 385-4231
47PROM , EPROM, EEPROM,
EAPROM1
48 RAM RAM
organization,,Write operation,Read operation, Memory cycle
- Timing wave forms
1
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49
Memory decoding memory
expansion, Static RAM Cell,
Bipolar RAM cell
Analyze the Memory decoding 1
50MOSFET RAM cell
Dynamic RAM cellStudy of MOSFET RAM cell 1
51
Programmable Logic Devices,
Programmable Logic Array
(PLA)To design PLD cells
T2 429-440
1
52
Programmable Array Logic
(PAL), Field Programmable
Gate Arrays
1
53
Implementation of
combinational logic circuits
using ROM, PLA, PAL
To implement combinational
logic circuits using ROM,
PLA, PAL
1
54 Problems Problems in RAM T2 4271
55 Problems Problems in ROM T2 400 1
56 Problems Problems in PLA T2 439 157 Problems Problems in PAL T2 441 1
58 Problems Problems in PLD T2430 1
UNIT-V SYNCHRONOUS AND ASYNCHRONOUS SEQUENTIAL CIRCUITS
59General Model of Synchronous
Sequential Circuits
To analyze the General Model
of Synchronous Sequential
Circuits
T2 453-454 1
60
Classification and Design of
Synchronous Sequential
CircuitsTo design Synchronous
Sequential Circuits using
Algorithmic State Machine
T2 454-469 1
61Use of Algorithmic State
Machine T2 469-486 1
62
Analysis of Synchronous
Sequential Circuits, Problems
in Synchronous Sequential
Circuits
To analyze Synchronous
Sequential Circuits and
Problems in Synchronous
Sequential Circuits
T2 486-493 1
63
Design of Fundamental mode
of Asynchronous Sequential
Circuits
To design Fundamental mode
of Asynchronous Sequential
Circuits
T2 496-507 1
64
Pulse mode circuits,
Incompletely specified StateMachines
To design Pulse mode circuits
and Incompletely specifiedState Machines
T2 507-521 1
65 ProblemsProblems in Asynchronous
CircuitsT2 521-525 1
66Design of Hazard Free
Switching circuits
To design Hazard Free
Switching circuitsT2 525-528 1
67
Design of Combinational and
Sequential circuits using
VERILOG
To design Combinational and
Sequential circuits using
VERILOG
T2 634-652 1
68 ProblemsProblems in Pulse mode
circuitsT2 507 1
69 Problems Problems in ASM T2 477 1
70 ProblemsProblems in Hazards
T2 5251
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71 ProgramsPrograms in Combinational
circuits using VERILOGT2 635 1
72 ProgramsPrograms in Sequential circuits
using VERILOGT2 643 1
Evaluation scheme Internal Assessment
III. Assignment topic:
1. Karnaugh map Minimization and Quine-McCluskey method of minimization
2. Design of Synchronous counters using state diagram, State table, State minimization ,State
assignment, Excitation table and maps-Circuit implementation
Question Bank will be issued by the instructor within one week from the starting
date.
Two marks (Part A) question and answers will be provided on completion of each
unit.
Timings for chamber consultation: Students should contact the Course Instructor in her/his
chamber during lunch break.
STAFF SIGNATURE HOD
Course Handout Date:04.07.2011
Course No. : EC1203 3 1 0 4
Course Title : ELECTRONIC CIRCUITS I
EC
No.
Evaluation
ComponentsDuration Weightage Date & Time Venue
1 Unit Test 1 1.30hr
30%
19.7.12-25.7.12
Tobe
announc
ed
later
2 Unit Test 2 1.30hr 8.8.12 16.8.12
3 Unit Test 3 1.30hr 24.9.12 29.9.12
4 Model Exam 1 3hr 40%
3.9.12 10.9.12
5 Model Exam 2 3hr 10.10.12 17.10.12
6 Assignment 15 days 10%
7Attendance
PercentageContinuous 20%
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Course Instructor : P.SUDHAInstructor-in-charge : P.SUDHA
Scope and Objective of the Course:The objective of this course is to introduce the fundamental of electronics, to develop the
foundations for designing and analyzing the Electronic circuits.
Text book(s) [TB]1. Millman, J, and Halkias, C., Integrated Electronics, 4th Edition, TMH, 2007.
2. Robert L. Boylestad and Louis Nashelsky., Electronic Devices and Circuit
3. Electronic circuits-I,U.A.Bakshi and A.P.Godse,Technical Publications Pune
Course Plan / Schedule:S.No Topics to be covered Learning objectives Ref. to Text Book No.
of
lect
ure
s
1 BJT Need for biasing - Stability
factor
To Understand the concept of biasing
transistors
T3(9 -22) 1
2 Fixed bias circuit Load line and
quiescent point Variation of
quiescent point due toFE hvariation within manufacturerstolerance Stability factors
Design and analysis the circuit of biasing,
selecting the operating point using dc load
line and its factors
T3(23-34) 2
3 Different types of biasing circuits Includes fixed, collector to base, self biascircuits
T3(35-49) 2
4 Method of stabilizing the Q point Provides the stability of operating point T3(50-60) 1
5 Advantage of self bias (voltagedivider bias) over other types of
biasing
Gives idea about better biasing circuitamong all other types
T3(35) 2
6 Bias compensation Diode Thermister and sensistor
compensations
To stabilize the biasing circuits, somecompensation techniques were introduced
T3(50-60) 2
7 Biasing of FET and
MOSFET.
To analyze the FET biasing circuits and its
types
T3(61-82) 2
8 CE, CB and CC small signalamplifiers Method of drawing
small signal equivalent circuit
To simplify the analysis of BJT, its differentconfiguration and determination of h-
parameters from characteristics
T3 (133-145) 2
9 Midband analysis of various typesof single stage amplifiers to obtain
gain ,Input impedance and outputimpedance
Simplified analysis of amplifier anddetermination of h-parameters from
characteristics.
T3 (146-168) 3
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10 Millers theorem Proof and analysis of millers theorem T3(169-175) 1
11 Comparison of CB, CE and CCamplifiers and their uses
Comparison of transistor configuration T3 (176) 1
12 Methods of increasing input
impedance using darlingtonconnection and bootstrapping
Techniques of improving input impedance
by analyzing the ac equivalent circuit
T3(176-196) 2
13 CS, CG and CD (FET) amplifiers Emphasize the use of FETs in linear
amplifier applications and its equivalentcircuit for different configuration
T3(247-270) 2
14 Multistage amplifiers Need for cascading, block diagram and
equivalent circuit of cascaded amplifier andits method of coupling
T3291-315) 2
15 Base emitter coupled differential
amplifier circuit Bisectiontheorem Differential
gain CMRR
Explains the basics of differential amplifier
and discusses its d.c and a.c analysis.
T3(341-362) 2
16 Use of constant current circuit to
improve CMRR Derivation oftransfer characteristic.
Methods of improving CMMR and
derivation of transfer characteristics
T3(363-374) 2
17 General shape of frequency
response of amplifiers Definitionof cutoff frequencies and
Bandwidth
Typical frequency response curve and its
ideal characteristics
T3(397-398) 1
18 Low frequency analysis ofamplifiers to obtain lower cutofffrequency hybrid equivalent
circuit of BJTS
Normalized analysis of low frequencyamplifier and to obtain hybrid parameters from its equivalent circuit.
T3(399-409) 2
19 High frequency analysis of BJT
amplifiers toobtain upper cutoff frequency
Gain bandwidth product
Analysis of high frequency amplifier and to
obtain hybrid parameters from itsequivalent circuit.
T3(410-435) 3
20 High frequency analysis of FET
amplifiers Gain Bandwidthproduct of FETS
Simplified equivalent circuit of high
frequency FET amplifier
T3(436-439) 1
21 General expression for frequencyresponse of multistage amplifiers,
Calculation of overall upper andlower cutoff frequencies of
multistage amplifiers
Derivation to obtain Overall lower andupper cut off frequency of multistage
amplifiers
T3(440-442) 1
22 Amplifier rise time and sag, and
their relation to cutoff frequencies.
To calculate rise time from upper 3db
frequency,sag and its relation to lower cutoff frequency
T3(442-445) 1
23 Classification of amplifiers Describes the Concept, features andclassification of amplifiers
T3(453-463) 1
24 Class A large signal amplifiers To analysis series fed, directly coupled class
A amplifier and its graphical representation
T3(463-469) 1
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25 Second harmonicdistortion Higher order harmonic
distortion
To find Harmonic distortion in amplifier forsecond and higher order by using five point
method and its affects
T3(481-489) 2
26 Transformer coupled class A audiopower amplifier Efficiency of
Class A amplifiers
Properties of transformer and to analysistransformer coupled class A amplifier to
obtain its efficiency
T3(472-480) 2
27 Class B amplifier Efficiency
Push-pullamplifier Distortion in amplifiers
To analyze dc and ac operation for finding
efficiency of Push-pull Class Bamplifier
T3(490-500) 1
28 Complementary Symmetry (classB) push-pull
Amplifier
To analyze dc and ac operation for findingefficiency of Complementary Class B
amplifier
T3(501-515) 1
29 Class C amplifier To calculate efficiency of Class C amplifier T3(515) 1
30 Class D amplifier Class Samplifier
To find efficiency of Class D and Samplifier
T3(461) 1
31 MOSFET power amplifier
Thermal stability and heat sink.
To design the MOSFET power amplifiers,
maximum power handled by it and safeoperating area of power transistors
T3(515-522) 1
32 Feedback Amplifier block diagram Concept of feedback and its basic blockdiagram
T3s(1.1-1.5) 1
33 Loop gain Gain with feedback
Effects of negative feedback Sensitivity and desensitivity of
gain Cut-off frequencies
Distortion Noise
General characteristics of negative feedback
amplifier
T3s(1.7-1.15) 1
34 Input impedance and output
impedance with feedback
To calculate input and output impedance of
all types of feedback amplifier
T3s(1.15-1.25) 1
35 Four types of negative feedback
connections Voltage seriesfeedback amplifiers.
To design and analysis the characteristics of
voltage series feedback amplifiers
T3s(1.27-1.34) 2
36 voltage shunt feedback amplifiers To design and analysis the characteristics ofvoltage shunt feedback amplifiers
T3s(1.43-1.45) 1
36 Current series
Feedback amplifiers.
To design and analysis the characteristics of
Current seriesFeedback amplifiers.
T3s(1.35-1.45) 2
37 Current shunt feedback amplifiers. To design and analysis the characteristics of
Current shunt feedback amplifiers
T3s(1.39-1.42) 1
38 Method of identifying feedbacktopology and
feedback factor
To identify the type of feedback amplifierand to find its feedback factor
T3s(1.26) 1
39 Nyquist criterion for stability of
feedback amplifiers
To obtain stability of feedback amplifiers
using Nyquist criterion
T3s(1.46) 1
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Total number of classes planned: 60
Evaluation scheme Internal Assesment
EC
No.
Evaluation
Components
Duration Weightage Date & Time Venue
1 Slip Test 1 40min 20%
Will beannounced bythe exam cell
Tob
e
announced
later
2 Slip Test 2 40min
3 Slip Test 3 40min
4 Slip Test 4 40min
5 Slip Test 5 40min
6 Slip Test 6 40min
7 Slip Test 7 40min
8 Slip Test 8 40min
9 Slip Test 9 40min
10 Slip Test 10 40min
13 Cycle Test 1 1.30hr 15%
14 Cycle Test 2 1.30hr 15%15 Model Exam 3hr 20%
16 Assignment 1 month 10% 11.8.2011
17 AttendancePercentage
Continous 20%
IV. Slip Test Portions:
Slip Test 1
Explain in detail about the fixed bias circuit with neat circuit diagram.
Comparison of all different types of biasing.
Slip test 2
Describe about the bias compensation techniques
Explain in detail about the fixed bias circuit with neat circuit diagram.
Slip test 3
Determination of h-parameters of small signal amplifiers.
Prove the millers theorem.
Slip test 4
Describe about the bootstrapping darlington circuits with neat circuit diagram
Explain in detail about the differential amplifier with neat circuit diagram and method of improving
CMMR.
Slip test 5
High frequency analysis of BJT amplifiers toobtain upper cutoff frequency and Gain bandwidth product
High frequency analysis of FET amplifiers and to calculate Gain, Bandwidth
product of FETS
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Slip test 6
General expression for frequency response of multistage amplifiers, Calculation of overall upper
and lower cutoff frequencies of multistage amplifiers
Explain about sag and risetime.
Slip test 7
Explain in detail about the transformer coupled class A amplifier with neat circuit diagram.
Expression of second harmonic distortion
Slip test 8
Explain in detail about the complementary symmetrical class B amplifier with neat circuit diagram.
Write notes on Heat sink.
Slip test 9 Explain the concept and general characteristics of negative feedback amplifier
Expression of input and output impedance of voltage series and shunt amplifier.
Slip test 10
Expression of input and output impedance of voltage series and shunt amplifier.
Nyquist criterion for stability of feedback amplifiers
V. Assignment topic:
FET amplifiers with neat circuit diagram.
- CS Configuration- CG Configuration- CD Configuration.
VI. Part-A Question with answer will be issued by the instructor on completion of each unit.
Timings for chamber consultation: Students should contact the Course Instructor in her/his chamber during lunchbreak.
Notices: All notices will be displayed on the Department Notice Board.
Hod Instructor-In-Charge Instructor
B.KARTHIGA P.SUDHAP.SUDHA
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COURSE HANDOUT
Subject code : EC 2201
Subject Title : ELECTRICAL ENGINEERING
Staff name : K.VIJAYA KANTH/A.RAJ KUMAR
Scope and Objective of the Subject:
To expose the students to the concepts of various types of electrical machines and
transmission and distribution of electrical power
Text book(s) [TB]1. U.A.Bakshi and V.U.Bakshi ,Electrical engineering technical publications.2. D.P.Kothari and I.J.Nagrath, Basic Electrical Engineering, Tata McGraw Hill
publishing company ltd, second edition, 2007 (Reprint).
3. C.L. Wadhwa, Electrical Power Systems, New Age International, fourth
edition,2007.
Reference book(s) [RB]
1. S.K.Bhattacharya, Electrical Machines, Tata McGraw Hill Publishing companyltd,second edition, 2007
2. V.K.Mehta and Rohit Mehta, Principles of Power System, S.Chand and
CompanyLtd, second edition, 2006
Course Plan / Schedule:
S.
No
Topics to be covered Learning objectives Ref. to Text
Book
No. of
lectures
UNIT-I-
D.C. MACHINES
1 Constructional details To impart knowledge
on Constructionaldetails of DC machines
T.B 1[page 1-8] 1
2 emf equation To derive the emf
equation of generator
T.B 1[page 1-
13]
1
3 Methods of excitation ,Self and
separately
excited generators
To impart knowledge
on excitation
T.B 1[page 1-
20]
1
4 Characteristics of series, shunt
and compound generators
To study the
characteristics of
generators
T.B 1[page 1-
33]
1
5 Principle of operation of D.C.
motor
To impart knowledge
on principle of operation
T.B 1[page 2-1] 1
6 Back emf and torque equation To derive the torque T.B 1[page 2-4] 1
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equation of motors
7 Characteristics of
series, shunt and compound
motors
To study the
characteristics of
motors
T.B 1[page 2-
16]
1
8 Starting of D.C. motors ,
Types of starters
To impart knowledge
on starters
T.B 1[page 2-
24]
2
9 Testing, brake test andSwinburnes test To impart knowledgeon testing of D.C.
machines
T.B 1[page 2-50] 1
10 Speed control of D.C. shunt
motors
To impart knowledge
on speed control
methods
T.B 1[page 2-
38]
1
UNIT-II
TRANSFORMERS
11 Constructional details To impart knowledge
on Constructional
details of transformers
T.B 1[page 3-3] 1
12 Principle of operation To study the operationof transformer
T.B 1[page 3-1] 1
13 emf equation To derive the emf
equation of transformer
T.B 1[page 3-8] 1
14 Transformation ratio To study about the
different types of
transformer
T.B 1[page 3-
10]
1
15 Transformer on no load To study the operation
of transformer when no
load
T.B 1[page 3-
14]
1
16 Parameters referred to HV/LV
windings
To calculate the
equivalent circuit
parameters
T.B 1[page 3-
28]
1
17 Equivalent circuit To derive the
equivalent circuit of
transformer
T.B 1[page 3-
31]
1
18 Transformer on load To study the operation
of transformer when
load is connected
T.B 1[page 3-
21]
1
19 Regulation, Testing To calculate the
efficiency of
transformer
T.B 1[page 3-
48]
1
20 Load test, open circuit and
short circuit
tests
To impart the
knowledge on testing
of transformer
T.B 1[page 3-
48]
2
UNIT-III
INDUCTION MOTORS
21 Construction of induction
motors
To impart knowledge
on Constructional
details of induction
motors
T.B 1[page 4-8] 1
22 Types of induction motors To study the various
types of inductionmotors
T.B 1[page 5-6] 1
23 Principle of operation of three- To study the operation T.B 1[page 4- 1
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phase induction motors of three-phase
induction motors
11]
24 Equivalent circuit To derive the
equivalent circuit of
induction motors
T.B 1[page 4-
52]
1
25 Performance calculation To calculate the
efficiency of induction
motors
T.B 1[page 4-
44]
1
26 Starting methods To study the different
types of starters
T.B 1[page 4-
66]
1
27 speed control of induction
motors
To study the speed
control methods of
induction motors
T.B 1[page 4-
74]
2
28 Single-phase
induction motors
To impart knowledge
on single phase
induction motor
T.B 1[page 5-1] 3
UNIT-IV-
SYNCHRONOUS AND SPECIAL MACHINES
29 Construction of synchronous
machines
To impart knowledge
on Constructional
details of synchronous
machines
T.B 1[page 6-4] 1
30 types of synchronous machines To impart knowledge
on types of
synchronous machines
T.B 1[page 6-
14]
1
31 Induced emf To derive the emf
equation of
synchronous machines
T.B 1[page 6-
18]
1
32 Voltage regulation; emf
and mmf methods
To calculate the
regulation of
synchronous machines
T.B 1[page 6-
43]
1
33 Brushless alternators To study the operation
of Brushless alternators
T.B 1[page 6-6] 1
34 Reluctance motor To study the operation
of Reluctance motor
T.B 1[page 7-1] 2
35 Hysteresis motor To study the operation
of Hysteresis motor
T.B 1[page 7-5] 2
36 Stepper motor To study the operationof stepper motor T.B 1[page 7-8] 2
UNIT-V
TRANSMISSION AND DISTRIBUTION
37 Structure of electric power
systems
To study about the
Structure of electric
power systems
T.B 1[page 8-1] 1
38 Generation of power To study the various
methods of power
generation
T.B 1[page 8-8] 1
39 transmission and distribution
systems
To impart the
knowledge PowerSystem transmission
and distribution
T.B 1[page 8-
29]
2
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40 EHVAC and EHVDC
transmission systems
To impart the
knowledge about the
transmission systems
T.B 1[page 8-
39]
1
41 Substation layout To impart the
knowledge about the
substation
T.B 1[page 8-
49]
1
42 Insulators To study the various
types of insulators
T.B 1[page 8-
58]
2
43 cables To study the various
types of cables
T.B 1[page 8-
72]
2
Evaluation scheme Internal Assessment
VII. Assignment topic:
1. characteristics of DC machines
2. Generation of power
Question Bank will be issued by the instructor within one week from the starting
date.
Two marks (Part A) question and answers will be provided on completion of each
unit.
Timings for chamber consultation: Students should contact the Course Instructor in her/his
chamber during lunch break.
STAFF SIGNATURE HOD
EC
No.
Evaluation
Components
Duration Weightage Date & Time Venue
1 Unit Test 1 1.30hr 30% 19.7.12-25.7.12
Tobe
announced
later
2 Unit Test 2 1.30hr 8.8.12 16.8.12
3 Unit Test 3 1.30hr 24.9.12 29.9.124 Model Exam 1 3hr 40% 3.9.12 10.9.12
5 Model Exam 2 3hr 10.10.12 17.10.12
6 Assignment 15 days 10%
7 Attendance
Percentage
Continuous 20%
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COURSE HANDOUT
Subject code : EC2204
Subject Title : Signals And Systems
Staff name : S.CHITRA
Scope and Objective of the Subject:
To study the properties and representation of discrete andcontinuous signals
To study sampling process and analysis of discrete systems using Z-Transforms
To study analysis and synthesis of discrete time systems
Text book(s) [TB]
1.Signals and system by Ramesh Babu-scitech Publication
Reference book(s) [RB]
1.Signals and system by Bommana Raja Srikrishnna Publication
Course Plan / Schedule:
S.
No
Topics to be covered Learning objectives Ref. to Text
Book
No. of
lectures
UNIT-I-1 Continuous time signals (CT
signals)- Discrete time signals
(DT signals)
To study classifications
of signals and systems
Signals and
systems by
Ramesh babu
1
2 Step,
Ramp, Pulse, Impulse,
Exponential,
To study examples of
signals
1
3 classification of CT and DT
signals
To study classifications
of signals
1
4 periodic and
aperiodic signals,
To study classifications
of signals
1
5 Problems To solve problems 1
6 Random signals, To study classifications
of signals
1
7 Energy & Power signals To study classifications
of signals
1
8 CT systems and DT
systems,
To study classifications
of signals
1
9 Classification of systems. To study classifications
of systems
1
UNIT-II
10 Introduction To study analysis of continuous time signals
Signals andsystems by
Ramesh babu
1
11 Fourier series analysis To solve problems 1
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12 spectrum of Continuous Time
(CT) signals
To study signals 1
13 Problems To solve problems 1
14 Fourier Transform To study signals 1
15 Problems To solve problems 1
16 LaplaceTransform To study transforms 1
17 Problems To solve problems 118 Problems To solve problems 1
UNIT-III
19 Differential Equation To study linear time
invariant continuous
systems
Signals and
systems by
Ramesh babu
1
20 Block diagram representation To study diagram 1
21 Impulse responsand
convolution integrals
To study convolution 1
22 Fourier transform To study transform 1
23 Laplace Transform To study transform 1
24 Problems To solve problems 125 State variables To study variables 1
26 Matrix representation 1
27 Problems To solve problems 1
UNIT-IV-
28 Analysis of Discrete time
signals
To study the analysis of
discrete time signals
Signals and
systems by
Ramesh babu
1
29 Sampling of CT signals To study signals 1
30 Alising To study alising 1
31 DTFT To study DTFT 132 DTFT Properties To study DTFT 1
33 Problems To solve problems 1
34 Z Transform To study transforms 1
35 Z transform Properties To study properties 1
36 Problems To solve problems 1
UNIT-V
37 Introduction to Linear time
invariant discrete time systems
To study analysis of
Linear time invariant
discrete time systems
Signals and
systems by
Ramesh babu
1
38 Difference Equation To study equation 1
39 Block diagram Representation To study diagram 140 Impulse response To study impulse
response
1
41 Convolution sum To study Convolution
sum
1
42 LTI system analysis using
DTFT
To study DTFT 1
43 Z Transforms To study transforms 1
44 State variable equations To study equations 1
45 Matrix representation of
systems
To study matrix
representation
1
Evaluation scheme Internal Assessment
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VIII. Assignment topic:
1.Problems in CT and DT systems
2.Problems in Fourier and Laplace transform
Question Bank will be issued by the instructor within one week from the starting
date.
Two marks (Part A) question and answers will be provided on completion of each
unit.
Timings for chamber consultation: Students should contact the Course Instructor in her/hischamber during lunch break.
STAFF SIGNATURE HOD
EC
No.
Evaluation
Components
Duration Weightage Date & Time Venue
1 Unit Test 1 1.30hr 30% 19.7.12-25.7.12
Tobe
announced
later
2 Unit Test 2 1.30hr 8.8.12 16.8.12
3 Unit Test 3 1.30hr 24.9.12 29.9.124 Model Exam 1 3hr 40% 3.9.12 10.9.12
5 Model Exam 2 3hr 10.10.12 17.10.12
6 Assignment 15 days 10%
7 Attendance
Percentage
Continuous 20%
Recommended