ECE 551: Digital System Design & Synthesis

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ECE 551: Digital System Design & Synthesis

Lecture Set 3 3.1: Verilog - User-Defined Primitives (UDPs)3.2: Verilog – Operators, Continuous Assignments, Behavioral Modeling, Procedural Assignments, Flip-Flop and Latch Models (In separate file)

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ECE 551 - Digital System Design & Synthesis Lecture 3.1 – Verilog - User-Defined Primitives (UDPs)

Overview Uses Syntax Table Notation Combinational Examples Sequential Examples Initialization

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Uses

Definition of primitives beyond the built-in ones

Useful for defining models for ASIC standard cells Simpler than modules Simulate faster than modules Useful for basic combinational and

sequential cells

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Syntax – 1 (FIO*) udp_declaration ::=

primitive udp_identifier (udp_port_list);udp_port_declaration {udp_port_declaration}combinational_body | sequential_bodyendprimitiveo In Verilog 2001, can use ANSI style also.

combinational_body ::=table combinational_entry {combinational_entry}endtable

combinational_entry ::=level_input_list:output_symbol; * For information only

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Syntax -2 (FIO)

sequential body ::=[udp_initial_statement] table sequential

entry {sequential_entry} endtableudp_initial_statement ::=

initial udp_output_port_identifier = init_val;sequential_entry ::=

seq_input_list : current_state : next_state;sequential_input_list ::=

level_input_list | edge_input_list

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Table Notation (including shortcuts)

Levels* 0 - Logic 0 1 - Logic 1 x - Unknown value ? - Iteration of input over 0, 1, x b - Iteration of input over 0, 1 - - No change

* z is not allowed! z on an input becomes x.

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Table Notation (continued)

Edges (vw) - Input change from v to w where v, w can

be any value on prior slide except for – * - Denotes all transitions on the input, i.e., (?,?) r - Rising - Input transition (01) f - Falling - Input transition (10) p - Positive - Input transitions (01), (0x) and (x1) n - Negative - Input transitions (10), (1x) and

(x0)

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Miscellaneous Concepts – Combinational UDPs Only one output bit permitted; first on list of

ports Number of inputs may be limited by

implementation of tools Number of entries in table may be limited by

implementation of tools Table entries in order of port list. Illegal to have same input combinations with

different output values Unspecified input combinations result in

output = x.

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Combinational Example 1 - 1

primitive full_adder_carry (co, a, b, c)output co;input a, b, c;

table// a b c : co

0 0 ? : 00 ? 0 : 0? 0 0 : 0

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Combinational Example 1 - 2

// a b c : co1 1 ? : 1;1 ? 1 : 1;? 1 1 : 1;

/* Note that table has to be specified for x value as well as 1 and 0. Thus, ? Instead of b.*/

endtableendprimitive

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Combinational Example 2 -1

Specify a single bit 2-to-1 Multiplexer with control input S, data inputs D0 and D1 and output Y.

UDPprimitive 2-to-1_mux (Y, S, D0, D1);

input S, D0, D1;output Y;table// S D0 D1 Y

0 0 ? 00 1 ? 1

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Combinational Example 2 -2

0 x ? x //Is this row necessary?1 ? 0 01 ? 1 11 ? x x //Is this row necessary?x 0 0 0x 1 1 1x 0 1 x //Is this row necessary?x 1 0 x //Is this row necessary?x x ? x //Is this row necessary?x ? x x //Is this row necessary?

endtableendprimitive

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Miscellaneous Concepts – Sequential UDPs Additional field represents the current state = current

output value. The output field for a sequential UDP is the next state. Require the output to be declared as a reg to hold the

state All transitions not affecting the output value shall be

explicitly specified to avoid becoming x. Only one input at a time can be a transition. If behavior of UDP is sensitive to any edge, the output

must be specified for all edges of all inputs. If both level sensitive and edge-sensitive cases are used,

level sensitive cases are processed last and dominate.

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Sequential Example - Level-Sensitive - 1primitive s_r_latch (s, r, q);

input s, r;output q;reg q;

table// s r : state : q/next state

0 0 : ? : - ;1 0 : ? : 1 ;0 1 : ? : 0 ;1 1 : ? : x ;//necessary?

endtableendprimitive

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Sequential Example - Level-Sensitive - 2

What’s missing?// s r : state : q/next state

x ? : 1 : x ;? x : 0 : x ;

// Are the above two entries necessary?// How about these entries?// s r : state : q/next state

x 0 : 1 : 1 ;0 x : 0 : 0 ;

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Sequential Example - Edge-Sensitive - 1

primitive d_posedge_ff (q, clk, d);input clk, d;output q;reg q:table //Assumes only 01 causes load of d!// clk d state q/next state

(01) 0 ? : 0 ; //Load 0(01) 1 ? : 1 ; //Load 1(10) ? ? : - ; //Hold on - edge ? (??) ? : - ; //Hold on fixed clock

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Sequential Example - Edge-Sensitive - 2

To check for coverage, count and enumerate all cases Counting:

clk d state q/next state count(??) ? ? 81? (??) ? 81 - overlap

Overlap occurs for (00), (11), (xx) = 0,1,x. There are 3 X 3 X 3 = 27 such cases.

Therefore, total cases = 81 + 81 - 27 = 135

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Sequential Example - Edge-Sensitive - 3

Enumerating all 135 cases (**cases without x output):clk d state q/next state count(01) 0 ? : 0 ; 3 **(01) 1 ? : 1 ; 3 **(10) ? ? : - ; 9 **? (??) ? : - ; 81 **(01) x ? : x ; 3(0x) 0 0 : - ; 1 **(0x) 1 1 : - ; 1 **(0x) remaining cases give x out? ; 7(x1) 0 0 : - ; 1 **(x1) 1 1 : - ; 1 ** (x1)remaining cases give x out? : 7(1x) ? ? : - ; 9 **(x0) ? ? : - : 9 **

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Sequential Example - Edge-Sensitive - 4

Final Resultprimitive d_posedge_ff (q, clk, d);

input clk, d; output q; reg q:table

clk d state q/next state(01) 0 ? : 0 ; (01) 1 ? : 1 ; (0x) 0 0 : - ; (0x) 1 1 : - ; (x1) 0 0 : - ; (x1) 1 1 : - ; (10) ? ? : - ; (1x) ? ? : - ;? (??) ? : - ;

endtable

endprimitive

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Initialization

One procedural assignment statement Assignment to reg/output only Keyword initial Values limited to 1’b0, 1’b1, 1’bx, 1, 0. Assignment at t = 0 for UDP instantiation Example: initial q = 1’b0;

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Summary

Uses Syntax Notation including Shortcuts Combinational Sequential Initialization