Dynamic CMOS

ECE 6130/4130: Advance VLSI Systems

Combinational Logic Styles: Part-IIDynamic Logic

Other Styles

Prof. Saibal MukhopadhyaySchool of Electrical & Computer Engineering

Georgia Institute of Technology

Reading Materials

Chapter 9 : Introduction to VLSI Circuits and Systems, Uyemura,

Chapter 6: Digital Integrated Circuits: A Design Perspectives, J. M. Rabaey, A. Chandrakasan, B. Nikolic

Lecture notes (posted in T-square, under “Resources/Lecture Slides”)

Dynamic CMOS In static circuits at every point in time (except

when switching) the output is connected to either GND or VDD via a low resistance path. fan-in of n requires 2n (n N-type + n P-type)

devices

Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. requires on n + 2 (n+1 N-type + 1 P-type)

transistors

Dynamic Gate

In2 PDNIn3

ClkOut

Two phase operationPrecharge (Clk = 0)Evaluate (Clk = 1)

((AB)+C)

Conditions on Output Once the output of a dynamic gate is

discharged, it cannot be charged again until the next precharge operation.

Inputs to the gate can make at most one transition during evaluation.

Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL

Properties of Dynamic Gates Logic function is implemented by the PDN only

number of transistors is N + 2 (versus 2N for static complementary CMOS)

Full swing outputs (VOL = GND and VOH = VDD) Non-ratioed - sizing of the devices does not affect

the logic levels Faster switching speeds

reduced load capacitance due to lower input capacitance (Cin) reduced load capacitance due to smaller output loading (Cout) no Isc, so all the current provided by PDN goes into discharging CL

Properties of Dynamic Gates Overall power dissipation usually higher than static

CMOS no static current path ever exists between VDD and GND

(including Psc) no glitching higher transition probabilities extra load on Clk

PDN starts to work as soon as the input signals exceed VTn, so VM, VIH and VIL equal to VTn low noise margin (NML)

Needs a precharge/evaluate clock

Issues in Dynamic Design 1: Charge Leakage

ClkOut

Leakage sources

Precharge

Evaluate

Dominant component is subthreshold current

Solution to Charge Leakage

• Precharge: Out is VDD and inverter out is GND, so keeper is on• Evaluation:

• PDN is off => keeper compensates for leakage• PDN is on => keeper fights with PDN

• Higher delay, higher short-circuit power• Proper keeper sizing is necessary to improve robustness while

ensuring a reasonable delay

Keeper

Issue 2: Charge Sharing

Charge stored originally on CL is redistributed (shared) over CL and CA leading to reduced robustness

Assume, CA initially discharged and CL fully charged.A makes a 0 -> 1 transition

Charge Sharing

CLVDD CLVout t Ca VDD VTn VX – +=

Vout Vout t VDD–CaCL-------- VDD VTn VX – –= =

Vout VDDCa

Ca CL+----------------------

case 1) if Vout < VTn

case 2) if Vout > VTnB 0

Clk Me:

L DD Tn

a Tn a Tn

L DD Tn L DD Tn

C VBoundaryC V V

C V C Vcase and caseC V V C V V

Charge Sharing Example

CL=50fF

Ca=15fF

Cc=15fF

Cb=15fF

Cd=10fF

30 2.5 0.9480

L DD L out a out c out

a cout DD

C V C V C V C VC CV V V V

VDD=2.5V, VTn=0.5V

0.6 0.25 2

a c LC C CCase

0.25Tn DD TnV V V

Worst cases:

ABC or ABC

Solution to Charge Redistribution

OutMkp

Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power)

Cascading Dynamic Gates

Out1In

Out2 V

Only 0 1 transitions allowed at inputs!

• Out2 should remain at VDD since Out1 transitions to 0 during evaluation.

• A finite propagation delay for the input to discharge Out1 to GND => the second output also starts to discharge.

• The second dynamic inverter turns off (PDN) when Out1 reaches VTn.

Domino Logic

In2 PDNIn3

Clk Out1

In4 PDNIn5

ClkOut2

1 11 0

0 00 1

Ensures all inputs to the Domino gate are set to 0 at the end of the precharge period. Hence, the only possible transition during evaluation is 0 -> 1

Properties of Domino Logic

Only non-inverting logic can be implemented Very high speed static inverter can be skewed, only L-H transition Input capacitance reduced – smaller logical effort

Designing with Domino Logic

In1In2In3

Inputs = 0during precharge

Can be eliminated!

Footless Domino

The first gate in the chain needs a foot switchPrecharge is rippling – short-circuit currentA solution is to delay the clock for each stage

Clk Mp

InnIn3

0 1 0 1 0 1

1 0 1 0

np-CMOS

In2 PDNIn3

Clk Out1

In4 PUNIn5

Out2(to PDN)

1 11 0

0 00 1

Only 0 1 transitions allowed at inputs of PDN Only 1 0 transitions allowed at inputs of PUN

How to Choose a Logic Style? Static CMOS:

robust, ease of implementation and design automation. Complex gates requires larger area and has lower speed

Pseudo-NMOS: Simple and fast Reduced robustness and static power

Pass transistor/Transmission gate: Attractive for implementation of specific circuits: XOR,

Adders, Multiplexers Dynamic CMOS:

High-performance and area efficient for complex gates Reduced robustness, complex design process, and higher

power dissipation Current Trend: Increased use of Static CMOS

Use of EDA tools for logic optimization More suitable for voltage scaling as CMOS is more robust to

noise and noise does not scale with voltage

Few Other Logic Styles

Mirror CircuitExample: XOR function table.

Equal number of input combinations that produces 0 and 1 in output

Same transistor topology for PUP and PDN paths

XOR and XNOR mirror circuit

XOR XNOR

Tri-state inverter

Clocked CMOS: C2MOS gate.

Clock signals

Example of clocked-CMOS logic gates.

Dynamic CMOS

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