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Berry DG15 Discrete/UMA Schematics Document ArrandaleC
Intel PCH 2010-02-03 REV : A00
C
B
DY :None Installed UMA:UMA platform installed PARK:DIS PARK platform installed M96:DIS M96 platform installed VRAM_1G:VRAM 128M*16 installed Colay :Manual modify BOM
B
A
A
Title Size A3 Date:5 4 3 2
Document Number
Cover PageSheet1
nf @ ho tmof
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
W ednesday, February 10, 2010
he x
Berry
ai
ai
l.c92
Wistron Corporation
1
omRev
A00
5
4
3
2
1
##OnMainBoard
D
1.Park-XT;512MB (64Mx16b*4) Dell P/N:9TGTN$AA HYNIX Dell P/N:C995R$AA SAMSUNG 2.Park-XT;1GB (128Mx16b*4) Dell P/N:PXFYJ$AA HYNIX Dell P/N:C09DT$AA SAMSUNG (1 and 2 co-lay) Clock Generator SLG8SP5857
Berry Block Diagram (Discrete/UMA co-lay)4 85,86,87,88
CPU DC/DCISL62883INPUTS+PWR_SRC
47
OUTPUTS+VCC_CORE
39,
SYSTEM DC/DCTPS51218INPUTS+PWR_SRC
VRAM 1GB/512MB
DDR3 800MHz
Intel CPUPCIe x 16 (Discrete only)
Project code : 91.4HH01.001 PCB P/N : 48.4HH01.0SA Revision : 09909-1DDRIII 800/1066 Channel A
49D
OUTPUTS+1.05V_VTT
4
SYSTEM DC/DCRT8205BINPUTS OUTPUTS+5V_ALW2 +3.3V_RTC_LDO +5V_ALW +3.3V_ALW +15V_ALW
46
AMD GraphicPark-XT (Discrete only)80,81,82,83,84
ArrandaleDDRIII 800/1066 Channel B
DDRIII 800/1066 DDRIII 800/1066
Slot 018
4
+PWR_SRC
Slot 119
SYSTEM DC/DCTPS51116INPUTS OUTPUTS+1.5V_SUS +0.75V_DDR_VTT +V_DDR_REF +PWR_SRC
50
4
8,9,10,11,12,13,14
PCIE x 1 USB x 1C
Mini-Card802.11a/b/g
SYSTEM DC/DCTPS5161153C
Discreet/UMA Co-lay HDMI57
FDIx4x2 (UMA only) Level 57 shifter
DMIx4PCIE x 1
10/100 NICRealtek RTL8103T-VB
HDMI
RJ45 CONN
INPUTS+PWR_SRC
OUTPUTS+CPU_GFX_CORE
4
VGART8208B89
I/O Board Connector
LCD54
LVDS(Dual Channel) RGB CRT
Intel PCH14 USB 2.0/1.1 ports
HM57
PCIE x 3
SATAx1 / USB2.0x1
ESATA/USB Combo Mini-CardWWAN SIM
INPUTS+PWR_SRC
OUTPUTS+VGA_CORE
TI CHARGERBQ24745INPUTS+DC_IN +PBATT26
5
45
CRT CRT BoardLeft Side: USB x 2 77
SATA x 1
PCIE x 1,USB x 1
OUTPUTS+PWR_SRC
ETHERNET (10/100/1000Mb) High Definition Audio SATA ports (6) PCIE ports (8) USB2.0 x 4 LPC I/F ACPI 1.1 PCI/PCI BRIDGE USB 2.0 x 4
SYSTEM DC/DCAPL593051
USB 2.0 x 1 76
Right Side: USB x 1
4
BluetoothB
INPUTS+3.3V_ALW
OUTPUTS+1.8V_RUN +1.8V_RUN_VGAB
73
CAMERA
5420,21,22,23,24,25,26,27,28
USB 2.0 x 1 AZALIA
CardReaderRealtek RTS515978
SYSTEM DC/DCSD/MMC+/MS/ MS Pro/xD
APL593026
90
3
INPUTS
OUTPUTS+1.0V_RUN_VGA
+1.5V_SUS
SwitchesSPI INPUTS LPC Bus SATA x 2 LPC debug port70
OUTPUTS+1.5V_RUN +5V_RUN +3.3V_RUN
Internal Analog MIC
HP1 MIC IN
Azalia CODECIDT 92HD79B130 SPI
HDD59
+1.5V_SUS +5V_ALW +3.3V_ALW
Flash ROM 4MB 62
ODD59
PCB LAYERL1:Top L2:VCC L3:Signal L4:Signal L5:GND L6:Bottom
A
KBCSMBusA
NUVOTONNPCE781BA0DX 2CH SPEAKER ThermalMain:G7922 Sec.EMC210225393
37
Title
58
ai
Flash ROM 256kB 625 4
Touch PAD68
Int. KB68
Block DiagramDocument Number W ednesday, February 10, 2010 Sheet1
Fan2
Date:
he x
Size A3
nf @ ho tmof
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
ai
Berry
2
l.c92
Wistron Corporation
omRev
A00
5
4
3
2
1
RT8208BD
+VGA_CORE
For Discrete
+1.0V_RUN_VGA
APL5930KAID
Adapter
+PWR_SRC ISL62883 TPS51218 TPS51611
TPS51116
AO4407A Charger BQ24745 Battery +PBATT+VCC_CORE +1.05V_VTT+CPU_GFX_CORE
+V_DDR_REF
+0.75V_DDR_VTT
+1.5V_SUS
For UMA
AO4468
RT8205BC
+1.5V_RUN For Discrete +1.5V_RUN_CPUC
+15V_ALW
+3.3V_RTC_LDO
+5V_ALW2
+5V_ALW
+3.3V_ALW
SI2301CDS
UP7534BRA8
AO4468
UP7534BRA8
AO4468
APL5930KAI
PA102FMG
+KBC_PWR
+5V_USB1 I/O Board USB Power
+5V_RUN
+5V_USB2 CRT Board USB Power
+3.3V_RUN
+3.3V_RUN_VGA For Discrete
+1.8V_RUN
+3.3V_LAN
RT9198-33PBG APL5930KAIB
SI3456BD
RTS5159
RTL8103T-VBB
+3.3V_CRT_LDO +1.8V_RUN_VGA For Discrete +LCDVDD+3.3V_RUN_CARD +1.2V_LOM
Power ShapeRegulator LDO Switch
A
A
Title Size A3 Date:5 4 3 2
Document Number
Power Block Diagram
nf @ ho tmof
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
W ednesday, February 10, 2010
Sheet1
he x
Berry
ai
ai
l.c92
Wistron Corporation
3
omRev
A00
A
B
C
D
E
PCH SMBus Block Diagram+3.3V_ALW +3.3V_RUN +3.3V_RUNSRN2K2J-1-GP
KBC SMBus Block Diagram+5V_RUN
SRN2K2J-1-GP
DIMM 1
SMBCLK1
PCH_SMB_CLK PCH_SMB_DATA
PCH_SMBCLK PCH_SMBDATA
SCL PSDAT1 PSCLK1 TPDATA TPCLK
SMBDATA
+3.3V_ALW
SMBus Address:A0
2N7002SPT
+KBC_PWR
SRN2K2J-8-GP
SML1CLK SML1DATA
KBC_SCL1 KBC_SDA1
To KBC2N7002DW-1-GP
DIMM 2+3.3V_ALW
SRN4K7J-8-GP
PCH_SMBCLK PCH_SMBDATA
SCL SDA SCL1 SDA1 BAT_SCL BAT_SDA
SML0CLK SML0DATA
SML0_CLK
+3.3V_RUN
PCH2
SRN2K2J-1-GP
UMASDVO_CTRLCLK SDVO_CTRLDATA PCH_HDMI_CLK PCH_HDMI_DATA
PCH_HDMI_DATA
PCH_SMBCLK PCH_SMBDATA
+3.3V_RUN
SMB_CLK
SMB_DATA
SRN2K2J-1-GP
UMAL_DDC_CLK L_DDC_DATA LDDC_CLK_PCH LDDC_DATA_PCH
SRN0J-6-GP PCH_SMBCLK PCH_SMBDATA
Minicard W-WANSMB_CLK SMB_DATA
GPIO73/SCL2 GPIO74/SDA2
KBC_SCL1 2N7002DW-1-GP KBC_SDA1
UMACRT_DDC_CLK CRT_DDC_DATA PCH_CRT_DDCCLK PCH_CRT_DDCDATA
+3.3V_RUN_VGA
SRN2K2J-1-GP
DIS3
DDC1CLK DDC1DATA
LCD CONNSRN0J-6-GP VGA_CRT_DDCCLK VGA_CRT_DDCDATA
DDC2CLK DDC2DATA
+3.3V_RUN
DIS
+5V_RUN
+3.3V_RUNSRN2K2J-1-GP
SRN0J-6-GP
UMA
+3.3V_RUN_VGA
+5V_RUN
UMA2N7002DW-1-GP
+5V_RUN
SRN2K2J-1-GP4
4
SRN2K2J-1-GP
DISIFPC_AUX_I2CW_SCL IFPC_AUX_I2C_SDA# GPU_HDMI_CLK GPU_HDMI_DATA
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A2 Date:A B C D
ai
Document Number
SMBUS Block Diagram
nf @ ho tm4 of
Wistron Corporation
BerryE
ai
Wednesday, February 10, 2010
he x
Sheet
l.cRev
TSCBTD3305CPWR
HDMI CONN
92
omA00
UMA
VGA
SRN2K2J-1-GP
CRT_DDCCLK_CON CRT_DDCDATA_CON
CRT CONN
UMA
Minicard WLAN
+3.3V_RUN
Level Shift
PCH_HDMI_CLK
SML0_DATA
SMBus Address:A4
SRN2K2J-1-GP
XDP
PCH_SMBCLK PCH_SMBDATA
Clock GeneratorSCLK SDATA
KBC NPCE781BA0DX
SMBus address:D2
SDA
SRN10KJ-5-GP
TouchPad Conn.TPDATA TPCLK TPDATA TPCLK
1
SRN100J-3-GP PBAT_SMBCLK1 PBAT_SMBDAT1
Battery Conn.CLK_SMB DAT_SMB
SMBus address:16
BQ24745SCL SDA
SMBus address:12+3.3V_RUN2
SRN4K7J-8-GP
ThermalTHERM_SCL THERM_SDA SCL SDA
SMBus address:7A
3
A
B
C
D
E
Thermal Block Diagram1
Audio Block Diagram1
SPKR_PORT_D_LSPKR_PORT_D_R+
SPEAKER
Codec 92HD79B1DP1 EMC2102_DP1 MMBT3904-3-GP SC470P50V3JN-2GP2
HP1_PORT_B_L HP1_PORT_B_R
DN1
EMC2102_DN1
HP OUT
2
Thermal G7922R61UDP2 VGA_THERMDA DN2 VGA_THERMDC
Place near CPU PWM CORE
THRMDA
VGATHRMDC
HP0_PORT_A_L HP0_PORT_A_R VREFOUT_A_OR_F
MIC IN
Place near GPU(DISCRETE only).
MMBT3904-3-GP3 3
DMIC_CLK/GPIO1
System Sensor(UMA only)
DMIC0/GPIO2
DP3
EMC2102_DP3 MMBT3904-3-GP SC470P50V3JN-2GP
DN3
EMC2102_DN3
Put under CPU(T8 HW shutdown)
PORTC_L PORTC_R VREFOUT_C
Analog MIC
4
Title Size Document Number Custom Date:A B C D
Thermal/Audio Block Diagram
nf @ ho tm
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
ai
Wistron Corporation
ai
l.c
Wednesday, February 10, 2010
SheetE
he x
Berry
5
of
omRev
4
A0092
A
B
C
D
E
PCH StrappingNameSPKR
Processor StrappingCalpella Schematic Checklist Rev.0_7 Schematics Notes Calpella Schematic Checklist Rev.0_7Pin NameCFG[4]
Strap DescriptionEmbedded DisplayPort Presence PCI-Express Static Lane Reversal PCI-Express Configuration Select Reserved Temporarily used for early Clarksfield samples.
4INIT3_3V# GNT3#/ GPIO55 INTVRMEN GNT0#, GNT1#/GPIO51
Reboot option at power-up Default Mode: Internal weak Pull-down. No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with 8.2-k - 10-k weak pull-up resistor. Weak internal pull-down. Do not pull high. Default Mode: Internal pull-up. Low (0) = Top Block Swap Mode (Connect to ground with 4.7-k pull-down resistor).
Configuration (Default value for each bit is 1 unless specified otherwise)1: Disabled - No Physical Display Port attached to Embedded DisplayPort. 0: Enabled - An external Display Port device is connected to the Embedded Display Port. 1: Normal Operation. 0: Lane Numbers Reversed 15 -> 0, 14 -> 1, ... 1: Single PCI-Express Graphics 0: Bifurcation enabled Clarksfield (only for early samples pre-ES1) Connect to GND with 3.01K Ohm/5% resistor Note: Only temporary for early CFD samples (rPGA/BGA) [For details please refer to the WW33 MoW and sighting report]. For a common motherboard design (for AUB and CFD), the pull-down resistor should be used. Does not impact AUB functionality.
Default Value1
41 1
CFG[3] weak CFG[0]
High (1) = Integrated VRM is enabled Low (0) = Integrated VRM is disabled Default (SPI): Left both GNT0# and GNT1# floating. No pull up required. Boot from PCI: Connect GNT1# to ground with 1-k pull-down resistor. Leave GNT0# Floating. Boot from LPC: Connect both GNT0# and GNT1# to ground with 1-k pull-down resistor. Default - Internal pull-up. Low (0)= Configures DMI for ESI compatible operation (for servers only. Not for mobile/desktops). Default: Do not pull low. Disable ME in Manufacturing Mode: Connect to ground with 1-k pull-down resistor. Enable iTPM: Connect to Vcc3_3 with 8.2-k weak pull-up resistor. Disable iTPM: Left floating, no pull-down required. Enable Danbury: Connect to Vcc3_3 with 8.2-k weak pull-up resistor. Disable Danbury: Connect to ground with 4.7-k weak pull-down resistor. Weak internal pull-up. Do not pull low. Low (0): Flash Descriptor Security will be overridden. High (1) : Flash Descriptor Security will be in effect. Weak internal pull-down. Do not pull high. Weak internal pull-down. Do not pull high. Weak internal pull-down. Do not pull high. Weak internal pull-up. Do not pull low. Default = Do not connect (floating) High(1) = Enables the internal VccVRM to have a clean supply for analog rails. No need to use on-board filter circuit. Low (0) = Disables the VccVRM. Need to use on-board filter circuits for analog rails.
CFG[7]
0
GNT2#/ GPIO53 GPIO33
3SPI_MOSI NV_ALE
3
NC_CLE HAD_DOCK_EN# /GPIO[33] HDA_SDO HDA_SYNC GPIO15 GPIO8 GPIO27
2
2
PCIE RoutingLANE1 LANE2 LANE3 LANE4 LANE5 LANE61
USB TableUSB Pair 0 1 2 3 4 5 6 7 8 9 10 11 12 13 Device USB2 (CRT Board) USB3 (CRT Board) WLAN (I/O Board) RESERVED CARD READER BLUETOOTH HM55 no support HM55 no support USB1 (I/O Board) USB0 (I/O Board ESATA) RESERVED W-WAN (I/O Board) RESERVED CAMERA 0 1 2 3 4 5
SATA TableSATA Pair HDD ODD HM55 no support HM55 no support ESATA RESERVED Device
RESERVED MiniCard WLAN LAN W-WAN RESERVED RESERVEDH55/HM55 no support H55/HM55 no support
LANE7 LANE8
121F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
Title Size A3 Date: Document Number
Table of ContentSheet 6 of
Rev
BerryW ednesday, February 10, 2010 92
A00
5
4
3
2
1
SSID = CLOCK
+3.3V_RUND
X02-20091222+3.3V_RUN_SL585 R701 +1.05V_VTT
X02-20091222+1.05V_RUN_SL585_IO R702D
1
2 0R0603-PAD 1C708 SC1U6D3V2KX-GP C707 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
1
2 0R0603-PAD 1 1C709 SC10U10V5ZY-1GP C710 SCD1U16V2ZY-2GP
1
1
1
1
1
1
DY2
2
2
2
2
2
2
2
2
x01 change tolerant 20091117+3.3V_RUN_SL585 +1.05V_RUN_SL585_IO
2
x01 change tolerant 20091117
+3.3V_RUN
R703
1C
2
CPU_STOP#
15
24
17
29
1
U701
VDD_27
5
VDD_SRC_IO
VDD_CPU_IO
VDD_CPU
VDD_SRC
VDD_DOT
VDD_REF
18
2K2R2J-2-GP
2
DY
C701 SC10U10V5ZY-1GP
C703 SCD1U10V2KX-5GP
C704 SCD1U10V2KX-5GP
C705 SCD1U10V2KX-5GP SCD1U10V2KX-5GP
C706 SCD1U16V2ZY-2GP
1
C702 SC1U6D3V2KX-GP
1
C711 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
DY
C
X01-2009111627MHZ 27MHZ_SS 6 7 16 25 30 28 27 31 32CLK_VGA_27M_NSS_R CLK_VGA_27M_SS_R CPU_STOP# CK_PW RGD FSC CLK_XTAL_IN CLK_XTAL_OUT
X02-20091222RN702 23 CLKIN_DMI# 23 CLKIN_DMI 23 CLK_PCIE_SATA# 23 CLK_PCIE_SATA 23 CLK_CPU_BCLK# 23 CLK_CPU_BCLK
2
22 23 19 20
CPU_0# CPU_0 CPU_1# CPU_1 VSS_SATA VSS_CPU VSS_SRC VSS_DOT VSS_REF VSS_27
XTAL_IN XTAL_OUT SDA SCL
DY2
1
2 RN703 3 CLK_PCIE_SATA#_C 1 4 CLK_PCIE_SATA_C 0R4P2R-PADRN
11 10
SRC_1/SATA# SRC_1/SATA
2
1 33R2J-2-GP
CLK_PCH_14M 23
EC703
SC4D7P50V2CN-1GP
GND
PCH_SMBDATA 18,19,23,76 PCH_SMBCLK 18,19,23,76
+3.3V_RUN_SL585
B
2
2
2 3 1 4 0R4P2R-PADRN
23 CLK_DREF# 23 CLK_DREF CLKIN_DMI#_C CLKIN_DMI_C
4 3 14 13
DOT_96# DOT_96 SRC_2# SRC_2
1
CPU_STOP# CKPWRGD/PD# REF_0/CPU_SEL
R704
DY
EC701 SC4D7P50V2CN-1GP
1
1 R708 1 R709
DIS DY
2 2 33R2J-2-GP 33R2J-2-GP
CLK_VGA_27M_NSS 82 CLK_VGA_27M_SS 82
DY
EC702 SC4D7P50V2CN-1GP
2
8
33
26
21
12
9
SLG8SP585VTR-GP
B
R705 10KR2J-3-GP +1.05V_VTT CK_PW RGD
FSC SPEED
0 133MHz (Default)
12X701 R706
D
1
. . . . .G S
Q701 2N7002E-1-GP
100MHz
CLK_XTAL_IN
1
2 1
CLK_XTAL_OUT
DY 4K7R2J-2-GP1FSC 47 VR_CLKEN#
1C712 SC12P50V2JN-3GP
X-14D31818M-37GP
82.30005.901
2
2
C713 SC12P50V2JN-3GP
2R707 10KR2J-3-GP
1
A
A
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Date:5 4 3 2
Wistron Corporation
Document Number
Clock Generator SLG8SP585BerrySheet1
Rev
A007 of 92
Monday, March 29, 2010
SSID = CPU
5
4
3
2
1
DCPU1A 1 OF 9
DPEG_ICOMPI PEG_ICOMPO PEG_RCOMPO PEG_RBIAS B26 PEG_IRCOMP_R A26 B27 EXP_RBIAS A25 K35 J34 J33 G35 G32 F34 F31 D35 E33 C33 D32 B32 C31 B28 B30 A31 J35 H34 H33 F35 G33 E34 F32 D34 F33 B33 D31 A32 C30 A28 B29 A30 L33 M35 M33 M30 L31 K32 M29 J31 K29 H30 H29 F29 E28 D29 D27 C26 L34 M34 M32 L30 M31 K31 M28 H31 K28 G30 G29 F28 E27 D28 C27 C25PEG_RXN15 PEG_RXN14 PEG_RXN13 PEG_RXN12 PEG_RXN11 PEG_RXN10 PEG_RXN9 PEG_RXN8 PEG_RXN7 PEG_RXN6 PEG_RXN5 PEG_RXN4 PEG_RXN3 PEG_RXN2 PEG_RXN1 PEG_RXN0 PEG_RXP[0..15] PEG_RXP15 PEG_RXP14 PEG_RXP13 PEG_RXP12 PEG_RXP11 PEG_RXP10 PEG_RXP9 PEG_RXP8 PEG_RXP7 PEG_RXP6 PEG_RXP5 PEG_RXP4 PEG_RXP3 PEG_RXP2 PEG_RXP1 PEG_RXP0 PEG_C_TXN15 PEG_C_TXN14 PEG_C_TXN13 PEG_C_TXN12 PEG_C_TXN11 PEG_C_TXN10 PEG_C_TXN9 PEG_C_TXN8 PEG_C_TXN7 PEG_C_TXN6 PEG_C_TXN5 PEG_C_TXN4 PEG_C_TXN3 PEG_C_TXN2 PEG_C_TXN1 PEG_C_TXN0 PEG_C_TXP15 PEG_C_TXP14 PEG_C_TXP13 PEG_C_TXP12 PEG_C_TXP11 PEG_C_TXP10 PEG_C_TXP9 PEG_C_TXP8 PEG_C_TXP7 PEG_C_TXP6 PEG_C_TXP5 PEG_C_TXP4 PEG_C_TXP3 PEG_C_TXP2 PEG_C_TXP1 PEG_C_TXP0 C816 C815 C814 C813 C812 C811 C810 C809 C808 C807 C806 C805 C804 C803 C802 C801 C832 C831 C830 C829 C828 C827 C826 C825 C824 C823 C822 C821 C820 C819 C818 C817 R801 1 R802 1
2 49D9R2F-GP 2 750R2F-GP
CLARKSFIELD
22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22
DMI_PTX_CRXN0 DMI_PTX_CRXN1 DMI_PTX_CRXN2 DMI_PTX_CRXN3 DMI_PTX_CRXP0 DMI_PTX_CRXP1 DMI_PTX_CRXP2 DMI_PTX_CRXP3
A24 C23 B22 A21 B24 D23 B23 A22 D24 G24 F23 H23 D25 F24 E23 G23
DMI_RX#0 DMI_RX#1 DMI_RX#2 DMI_RX#3 DMI_RX0 DMI_RX1 DMI_RX2 DMI_RX3 DMI_TX#0 DMI_TX#1 DMI_TX#2 DMI_TX#3 DMI_TX0 DMI_TX1 DMI_TX2 DMI_TX3
PEG_RXN[0..15]
PEG_RXN[0..15]
80
DMI_CTX_PRXN0 DMI_CTX_PRXN1 DMI_CTX_PRXN2 DMI_CTX_PRXN3 DMI_CTX_PRXP0 DMI_CTX_PRXP1 DMI_CTX_PRXP2 DMI_CTX_PRXP3
PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8 PEG_RX#9 PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15 PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8 PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15 PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8 PEG_TX#9 PEG_TX#10 PEG_TX#11 PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15 PEG_TX0 PEG_TX1 PEG_TX2 PEG_TX3 PEG_TX4 PEG_TX5 PEG_TX6 PEG_TX7 PEG_TX8 PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15
DMI
PEG_RXP[0..15] 80
C
22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22
FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7 FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7
E22 D21 D19 D18 G21 E19 F21 G18 D22 C21 D20 C18 G22 E20 F20 G19 F17 E17 C17 F18 D17
FDI_TX#0 FDI_TX#1 FDI_TX#2 FDI_TX#3 FDI_TX#4 FDI_TX#5 FDI_TX#6 FDI_TX#7 FDI_TX0 FDI_TX1 FDI_TX2 FDI_TX3 FDI_TX4 FDI_TX5 FDI_TX6 FDI_TX7 FDI_FSYNC0 FDI_FSYNC1 FDI_INT FDI_LSYNC0 FDI_LSYNC1
C
Intel(R) FDI
PCI EXPRESS -- GRAPHICS
PEG_TXN[0..15]
PEG_TXN[0..15] 80
22 FDI_FSYNC0 22 FDI_FSYNC1 22 FDI_INT 22 FDI_LSYNC0 22 FDI_LSYNC1
BDIS
R804 1KR2J-1-GP
1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS 1 DIS
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP
PEG_TXN15 PEG_TXN14 PEG_TXN13 PEG_TXN12 PEG_TXN11 PEG_TXN10 PEG_TXN9 PEG_TXN8 PEG_TXN7 PEG_TXN6 PEG_TXN5 PEG_TXN4 PEG_TXN3 PEG_TXN2 PEG_TXN1 PEG_TXN0 PEG_TXP[0..15] PEG_TXP15 PEG_TXP14 PEG_TXP13 PEG_TXP12 PEG_TXP11 PEG_TXP10 PEG_TXP9 PEG_TXP8 PEG_TXP7 PEG_TXP6 PEG_TXP5 PEG_TXP4 PEG_TXP3 PEG_TXP2 PEG_TXP1 PEG_TXP0 PEG_TXP[0..15] 80
B
1
8 7 6 5
DIS1 2 3 4
RN801 SRN1KJ-4-GP
2
x01 change tolerant 20091117CLARKUNF
62.10055.341 SEC. 62.10053.561A
A21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
Title Size Date: Document Number
CPU (PCIE/DMI/FDI)Sheet 8 of
Rev
BerryMonday, March 29, 2010 92
A00
5Processor Compensation Signals+1.05V_VTT
4 SSID = CPUCPU1B 2 OF 9 BCLK BCLK# BCLK_ITP BCLK_ITP# PEG_CLK PEG_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK# A16 BCLK_CPU_C_P B16 BCLK_CPU_C_N AR30 AT30 E16 D16 A18 A17 BCLK_ITP_P BCLK_ITP_N CLK_EXP_C_P CLK_EXP_C_N AT23 AT24 G16 AT26 AH24 AK14 COMP3
X02-20091222RN
3BCLK_CPU_P BCLK_CPU_N 25 25 S3_RST_GATE# 25 +1.5V_SUS CLK_EXP_P 23 CLK_EXP_N 23
2
1
Processor PullupsR902 2 49D9R2F-GP 2 68R2-GP H_CATERR# R903 H_PROCHOT# H_CPURST# TPAD14-GP R904
1 1 1
2 20R2F-GP 2 20R2F-GP 2 49D9R2F-GP 2 49D9R2F-GP 1
H_COMP3 H_COMP2 H_COMP1 H_COMP0 SKTOCC#_R H_CATERR#
R901 1 R907 1 R906 1
COMP2
1 RN901 4 2 3 0R4P2R-PAD RN
CLARKSFIELD
COMP1 COMP0 SKTOCC# CATERR#
CLOCKS
MISC
1 R905
DY
2 68R2-GP
TP901
1 RN902 4 2 3 0R4P2R-PAD
X01 20091117Q901 G 1 R908 1KR2J-1-GP 2 D 1
. . . . .
THERMAL
DDR3_DRAMRST#
18,19
.
D
25 H_PECI
AT15
SM_DRAMRST# SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 PM_EXT_TS#0 PM_EXT_TS#1
F6 AL1 AM1 AN1 AN15 AP15 SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2 PM_EXTTS#0_C PM_EXTTS#1_C
SM_DRAMRST#
S 2N7002E-1-GP
PECI
PM_EXTTS#0_C 53 RN903 4 3 RN +1.05V_VTT 1 2 1 R909
47 H_PROCHOT#
AN26
PROCHOT#
DY
2 0R2J-2-GP
x01 change tolerant 20091117DDR3 Compensation SignalsSM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2 R913 1 R914 1 R916 1 2 100R2F-L1-GP-U 2 24D9R2F-L-GP 2 130R2F-1-GP
25,37,42,82
H_THERMTRIP#
AK15
THERMTRIP#
DDR3 MISC
SRN10KJ-5-GP XDP_PRDY# XDP_PREQ# XDP_TCLK XDP_TMS XDP_TRST# XDP_TDI_R XDP_TDO_R XDP_TDI_M XDP_TDO_M H_DBR#_R XDP_OBS0 XDP_OBS1 XDP_OBS2 XDP_OBS3 XDP_OBS4 XDP_OBS5 XDP_OBS6 XDP_OBS7 1 2 4 3 RN904 0R4P2R-PAD PM_EXTTS#0 18 PM_EXTTS#1 19
PRDY# PREQ# TCK TMS TRST# TDI TDO TDI_M TDO_M DBR# BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7
AT28 AP27 AN28 AP28 AT27 AT29 AR27 AR29 AP29 AN25 AJ22 AK22 AK24 AJ24 AJ25 AH22 AK23 AH23
H_CPURST#
AP26 AL15
X03-20100118
RESET_OBS# PM_SYNC VCCPWRGOOD_1 VCCPWRGOOD_0 SM_DRAMPWROK VTTPWRGOOD TAPPWRGOOD RSTIN#
22 H_PM_SYNC
JTAG & BPM
X02-20091222+1.05V_VTT 1 R911 2 0R0402-PAD XDP_DBRESET# XDP_TMS R919 XDP_TDI_R +1.5V_RUN_CPU XDP_PREQ# 1 R922 R915 1KR2J-1-GP XDP_TCLK R923 1 R920 1 1 1
X02-2009122225,42 H_PWRGD 22 PM_DRAM_PWRGD 1 R910 2 0R0402-PAD 1 R912 2 0R0402-PAD VCCPWRGOOD VDDPWRGOOD_R
AN14 AN27 AK13 AM15
2
C903 SCD1U10V2KX-5GP
D
PWR MANAGEMENT
DY 2 DY 2 DY 2 DY 2
51R2J-2-GP 51R2J-2-GP 51R2J-2-GP 51R2J-2-GP
X01 20091121 VTTPWRGOOD signal must be clean and close to CPU 21,37,70,76,78,80 PLT_RST# For EMI49 H_VTTPWRGD
H_PWRGD_XDP PLT_RST#_R 1 R918 750R2F-GP 2
AM26 2 AL14
DYSM_DRAMRST# 2
1
C
XDP_RST#_R VCCPWRGOOD VDDPWRGOOD_R H_VTTPWRGD PLT_RST#_R XDP_DBRESET# 2E 2E 2E 2E 2E 2E EC906 C906 SCD1U10V2KX-5GP EC905 C905 SCD1U10V2KX-5GP EC904 C904 SCD1U10V2KX-5GP EC903 C903 SCD1U10V2KX-5GP EC902 C902 SCD1U10V2KX-5GP EC901 C901 SCD1U10V2KX-5GP
R917 1K54R2F-GP
X01 20091111R921 100KR2J-1-GP 2
+3.3V_RUN
A00-20100226U901 1 2 3 A B GND VCC Y 5 4 VTT_PWRGD_C 1
DY1
DY1
DY1
DY1
DY1
1
50 0D75V_EN
x01 change tolerant 20091117+1.5V_SUS 1 +1.5V_RUN_CPU 1
XDP_TDI_R R927 1K54R2F-GP R941 1 2 1K54R2F-GP XDP_TDO_M 1 VDDPWRGOOD_KBC 37
1
CLARKUNF
C
XDP1 NP1 61 2 62 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 63 64 NP2
NL17SZ08DFT2G-GP
1 R928 1 R929
DY 2 DY2
XDP_TDI 0R2J-2-GP XDP_TRST# XDP_TDO 1 R932 0R2J-2-GP 51R2J-2-GP 2 0R2J-2-GP
VDDPWRGOOD_R
2
1 XDP_PREQ# XDP_PRDY# 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59
1
DY
XDP_OBS2 XDP_OBS3
2
2
2
DYVDDPWRGOOD_R
R924 1K1R2F-GP
DY
R925 1K1R2F-GP
XDP_OBS0 XDP_OBS1
XDP_TDI_M XDP_TDO_R +1.05V_VTT
2 1 R933
R930 750R2F-GP
X02-20091224
R931 0R0402-PAD
DY 2
1 R934 2 0R0402-PAD
X02-20091222 JTAG MAPPING
R926 3KR2F-GP
1
DY2
X01 20091112
XDP_OBS4 XDP_OBS5 XDP_OBS6 XDP_OBS7
x01 change tolerant 20091117C901 SCD1U10V2KX-5GP BCLK_ITP_P BCLK_ITP_N XDP_RST#_R 1 R939 XDP_TRST# XDP_TDI XDP_TMS 1
DY
Scan Chain (Default) CPU Only GMCH Only
DY2
+1.05V_VTT
H_PWRGD H_PWRGD_XDP
22 PM_PWRBTN#_R
B
1 R935 1 R937 1 R938
DY DY DY
H_CPUPWRGD_XDP 2 2 1KR2J-1-GP PM_PWRBTN#_XDP 0R2J-2-GP PCIE_CLK_XDP_P 2 0R2J-2-GP
R936 51R2J-2-GP 2
Stuff --> R928, R931, R934 No Stuff --> R929, R933 Stuff --> R928, R929 No Stuff --> R931, R934, R933 Stuff --> R933, R934 No Stuff --> R928, R929, R931
DY
2H_CPURST# 1KR2J-1-GP
1
XDP_DBRESET# 22,23 XDP_TDO
C902 SCD1U10V2KX-5GP
DY
23 SML0_DATA 23 SML0_CLK XDP_TCLK
B
x01 change tolerant 20091117
2
1
XDP_RST#_R
1 R940
2 DY0R2J-2-GP
PLT_RST# 21,37,70,76,78,80
PAD-60P-GP
A00-20100208
A
AWistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Date: Document Number
CPU (THERMAL/CLOCK/PM )BerrySheet 9 of
Rev
A0092
Monday, March 29, 2010
5
4
3
2
1
5
4
3
2
1
SSID = CPUCPU1C 3 OF 9
CPU1D
4 OF 9
18 M_A_DQ[63..0]D
M_A_DQ[63..0] M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63
C
B
A10 C10 C7 A7 B10 D10 E10 A8 D8 F10 E6 F7 E9 B7 E7 C6 H10 G8 K7 J8 G7 G10 J7 J10 L7 M6 M8 L9 L6 K8 N8 P9 AH5 AF5 AK6 AK7 AF6 AG5 AJ7 AJ6 AJ10 AJ9 AL10 AK12 AK8 AL7 AK11 AL8 AN8 AM10 AR11 AL11 AM9 AN9 AT11 AP12 AM12 AN12 AM13 AT14 AT12 AL13 AR14 AP14
CLARKSFIELD
SA_CK0 SA_CK#0 SA_CKE0
AA6 AA7 P7
M_CLK_DDR0 18 M_CLK_DDR#0 18 M_CKE0 18
SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63
SA_CK1 SA_CK#1 SA_CKE1
Y6 Y5 P6
M_CLK_DDR1 18 M_CLK_DDR#1 18 M_CKE1 18
SA_CS#0 SA_CS#1
AE2 AE8
M_CS#0 18 M_CS#1 18
SA_ODT0 SA_ODT1
AD8 AF9
M_ODT0 18 M_ODT1 18
SA_DM0 SA_DM1 SA_DM2 SA_DM3 SA_DM4 SA_DM5 SA_DM6 SA_DM7
B9 D7 H7 M7 AG6 AM7 AN10 AN13
M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7
M_A_DM[7..0] 18 M_A_DQS#[7..0] 18 M_A_DQS[7..0] 18
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY - B
SA_DQS#0 SA_DQS#1 SA_DQS#2 SA_DQS#3 SA_DQS#4 SA_DQS#5 SA_DQS#6 SA_DQS#7
C9 F8 J9 N9 AH7 AK9 AP11 AT13
M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7
M_A_A[15..0] 18
SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7
C8 F9 H9 M9 AH8 AK10 AN11 AR13
M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7
18 M_A_BS0 18 M_A_BS1 18 M_A_BS2
AC3 AB2 U7
SA_BS0 SA_BS1 SA_BS2
18 M_A_CAS# 18 M_A_RAS# 18 M_A_W E#
AE1 AB3 AE9
SA_CAS# SA_RAS# SA_WE#
SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15
Y3 W1 AA8 AA3 V1 AA9 V8 T1 Y9 U6 AD4 T2 U3 AG8 T3 V9
M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15
M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63
B5 A5 C3 B3 E4 A6 A4 C4 D1 D2 F2 F1 C2 F5 F3 G4 H6 G2 J6 J3 G1 G5 J2 J1 J5 K2 L3 M1 K5 K4 M4 N5 AF3 AG1 AJ3 AK1 AG4 AG3 AJ4 AH4 AK3 AK4 AM6 AN2 AK5 AK2 AM4 AM3 AP3 AN5 AT4 AN6 AN4 AN3 AT5 AT6 AN7 AP6 AP8 AT9 AT7 AP9 AR10 AT10
SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63
CLARKSFIELD
19 M_B_DQ[63..0]
M_B_DQ[63..0]
SB_CK0 SB_CK#0 SB_CKE0 SB_CK1 SB_CK#1 SB_CKE1
W8 W9 M3 V7 V6 M2
M_CLK_DDR2 19 M_CLK_DDR#2 19 M_CKE2 19 M_CLK_DDR3 19 M_CLK_DDR#3 19 M_CKE3 19
D
SB_CS#0 SB_CS#1
AB8 AD6
M_CS#2 19 M_CS#3 19
SB_ODT0 SB_ODT1
AC7 AD1
M_ODT2 19 M_ODT3 19
SB_DM0 SB_DM1 SB_DM2 SB_DM3 SB_DM4 SB_DM5 SB_DM6 SB_DM7
D4 E1 H3 K1 AH1 AL2 AR4 AT8
M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7
M_B_DM[7..0] 19 M_B_DQS#[7..0] 19 M_B_DQS[7..0] 19
SB_DQS#0 SB_DQS#1 SB_DQS#2 SB_DQS#3 SB_DQS#4 SB_DQS#5 SB_DQS#6 SB_DQS#7
D5 F4 J4 L4 AH2 AL4 AR5 AR8
M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7
M_B_A[15..0] 19
C
SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7
C5 E3 H4 M5 AG2 AL5 AP5 AR7
M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7
B
19 M_B_BS0 19 M_B_BS1 19 M_B_BS2 19 M_B_CAS# 19 M_B_RAS# 19 M_B_W E#
AB1 W5 R7 AC5 Y7 AC6
SB_BS0 SB_BS1 SB_BS2 SB_CAS# SB_RAS# SB_WE#
SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15
U5 V2 T5 V3 R1 T8 R2 R6 R4 R5 AB5 P3 R3 AF7 P5 N1
M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15
CLARKUNFA
CLARKUNF
A
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Date:5 4 3 2
Wistron Corporation
Document Number
CPU (DDR)Sheet1
Rev
BerryMonday, March 29, 2010 10 of 92
A00
5
4
3
2
1
SSID = CPU
CPU1E
5 OF 9
D
RSVD#AJ13 RSVD#AJ12
AJ13 AJ12 AH25 AK26 AL26 AR2 AJ26 AJ27
D
CLARKSFIELD
CFG0
PCI-Express Configuration SelectR1101 3KR2F-GP
DY2
CFG0
1:Single PEG 0:Bifurcation enabled
AP25 AL25 AL24 AL22 AJ33 AG9 M27 L28 J17 H17 G25 G17 E31 E30
RSVD#AP25 RSVD#AL25 RSVD#AL24 RSVD#AL22 RSVD#AJ33 RSVD#AG9 RSVD#M27 RSVD#L28 SA_DIMM_VREF SB_DIMM_VREF RSVD#G25 RSVD#G17 RSVD#E31 RSVD#E30
RSVD#AH25 RSVD#AK26 RSVD#AL26 RSVD_NCTF_37 RSVD#AJ26 RSVD#AJ27
1
TPAD14-GP TPAD14-GP TPAD14-GP CFG3
TP1101 TP1102 TP1103 TP1104 TP1105 TP1106 TP1107 TP1108 TP1109 TP1110 TP1111 TP1112 TP1113 TP1114 TP1115
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CFG3 - PCI-Express Static Lane ReversalR1104 3KR2J-2-GP
TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP
DIS2C
RESERVED
CFG3
1 :Normal Operation 0 :Lane Numbers Reversed 15 -> 0, 14 -> 1, ...
CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17
AM30 AM28 AP31 AL32 AL30 AM31 AN29 AM32 AK32 AK31 AK28 AJ28 AN30 AN32 AJ32 AJ29 AJ30 AK30 H16
CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 RSVD_TP_86
RSVD#AL28 RSVD#AL29 RSVD#AP30 RSVD#AP32 RSVD#AL27 RSVD#AT31 RSVD#AT32 RSVD#AP33 RSVD#AR33
AL28 AL29 AP30 AP32 AL27 AT31 AT32 AP33 AR33
1
C
RSVD#AR32 RSVD_TP#E15 RSVD_TP#F15 KEY RSVD#D15 RSVD#C15 RSVD#AJ15 RSVD#AH15
AR32 E15 F15 A2 D15 C15 AJ15 AH15
CFG4
CFG4 - Display Port PresenceR1105 3KR2F-GP
B19 A19 A20 B20 U9 T9 AC9 AB9
1
RSVD#B19 RSVD#A19 RSVD#A20 RSVD#B20 RSVD#U9 RSVD#T9 RSVD#AC9 RSVD#AB9 SA_CK2 SA_CK#2 SA_CKE2 SA_CS#2 SA_ODT2 SA_CK3 SA_CK#3 SA_CKE3 SA_CS#3 SA_ODT3 SB_CK2 SB_CK#2 SB_CKE2 SB_CS#2 SB_ODT2 SB_CK3 SB_CK#3 SB_CKE3 SB_CS#3 SB_ODT3 VSS
DY2
CFG4
1:Disabled; No Physical Display Port attached to Embedded Display Port 0:Enabled; An external Display Port device is connected to the Embedded Display Port
AA5 AA4 R8 AD3 AD2 AA2 AA1 R9 AG7 AE3 V4 V5 N2 AD5 AD7 W3 W2 N3 AE5 AD9 AP34
CFG7 R1106 3KR2F-GP
B
CFG7(Reserved) - Temporarily used for early Clarksfield samples. CFG7 Clarksfield (only for early samples pre-ES1) Connect to GND with 3.01K Ohm/5% resistor. Note: Only temporary for early CFD sample (rPGA/BGA) [For details please refer to the WW33 MoW and sighting report]. For a common M/B design (for AUB and CFD), the pull-down resistor shouble be used. Does not impact AUB functionality.
1
DY2
J29 J28
RSVD#J29 RSVD#J28
VSS (AP34) can be left NC is CRB implementation; EDS/DG recommendation to GND.R1107 RSVD_VSS
B
1 2 0R0402-PAD
CLARKUNF
X02-20091224
A
A
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Date:5 4 3 2
Document Number
CPU (RESERVED)Sheet1
Rev
BerryWednesday, February 10, 2010 11 of 92
A00
5
4
3
2
1
SSID = CPU+VCC_CORE
CPU1F
6 OF 9
CLARKSFIELD
PROCESSOR CORE POWER+VCC_CORED
x01 change tolerant 20091117VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 AH14 AH12 AH11 AH10 J14 J13 H14 H12 G14 G13 G12 G11 F14 F13 F12 F11 E14 E12 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11 1 1 1 1 1 1 1 1C1209 SC10U10V5ZY-1GP C1202 SC10U6D3V5KX-1GP C1210 SC10U10V5ZY-1GP C1211 SC10U6D3V5KX-1GP C1212 SC10U6D3V5KX-1GP C1203 SC10U6D3V5KX-1GP C1204 SC10U10V5ZY-1GP C1213 SC10U10V5ZY-1GP
+1.05V_VTT
x01 change tolerant 20091117C1201 SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP C1225 SC10U6D3V5KX-1GP C1205 SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP C1206 SC10U6D3V5KX-1GP C1207 SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP C1215 SC10U6D3V5KX-1GP C1208 SC10U6D3V5KX-1GP
48A
DY2
DY2
x01 change tolerant 200911171 1 1 1 1C1219 C1220 SC22U6D3V5MX-2GP C1221 SC10U6D3V5KX-1GP C1222 SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP
2
2
DY2
DY2
1
DY
2
2
2
x01 change tolerant 200911171 1 1 1 1 1 1C1227 SC10U6D3V5KX-1GP
2
2
2
2
2
2
2
2
2
DY
DY
DY
DY
DY
1
C1226 SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP
C1228 SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP
C1229 SC10U6D3V5MX-3GP
C1230 SC10U6D3V5KX-1GP
C1231 SC10U6D3V5KX-1GP
C1232 SC10U6D3V5MX-3GP
x01 change tolerant 20091117VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 AF10 AE10 AC10 AB10 Y10 W10 U10 T10 J12 J11 J16 J15C1234
DY
1
C
C1233 SC10U6D3V5KX-1GP
1
2
C1223 SC10U6D3V5KX-1GP
C1224 SC10U6D3V5KX-1GP
x01 change tolerant 200911171 1 1 1 1C1236 SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP C1237 SC10U6D3V5KX-1GP C1238 SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP C1239 SC10U6D3V5MX-3GP
1
1
DY
DY
1
C1235 SC10U6D3V5KX-1GP
C1240 SC10U6D3V5KX-1GP
C1241 SC22U6D3V5MX-2GP
C1242 SC10U6D3V5KX-1GP
2
2
2
2
2
2
2
2
DY
C1243 SC22U6D3V5MX-2GP
2
DY
B
AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
C1214 SC10U10V5ZY-1GP
2
2
2
2
2
2
2
2
2
DY
DY
DY
DY
DYD
1
1
1
1
1
2
2
2
2
1
x01 change tolerant 200911171 1 1C1216 SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP C1217 SC10U6D3V5KX-1GP C1218 SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP
+1.05V_VTT
1.1V RAIL POWER
DY
The decoupling capacitors, filter recommendations and sense resistors on the CPU/PCH Rails are specific to the CRB Implementation. Customers need to follow the recommendations in the Calpella Platform Design Guide.
+1.05V_VTT
1
CPU CORE SUPPLY
C
SC10U6D3V5MX-3GP
DY2
2
Please note that the VTT Rail Values are Auburndale VTT=1.05V; Clarksfield VTT=1.1VPSI# VID VID VID VID VID VID VID PROC_DPRSLPVR AN33 AK35 AK33 AK34 AL35 AL33 AM33 AM35 AM34H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6 PSI# 47 H_VID[6..0] 47
1
POWER
CPU VIDS
PM_DPRSLPVR
47B
VTT_SELECT
G15
H_VTTVID1
1
TP1201
TPAD14-GP
H_VTTVID1 = Low, 1.1V H_VTTVID1 = High, 1.05V+VCC_CORE
1 ISENSE AN35IMVP_IMON 47 R1201 100R2F-L1-GP-U
SENSE LINES
VCC_SENSE VSS_SENSE VTT_SENSE VSS_SENSE_VTT
AJ34 AJ35 1 B15 A15R1202 100R2F-L1-GP-U
2
VCC_SENSE 47 VSS_SENSE 47 VTT_SENSE 49 TP1202 TPAD14-GP
TP_VSS_SENSE_VTT 1
A
2
A
CLARKUNF
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Date:5 4 3 2
Document Number
CPU (VCC_CORE)Sheet1
Rev
BerryMonday, March 29, 2010 12 of 92
A00
5
4
3
2
1
SSID = CPU+CPU_GFX_CORE
22A1 1 1 1 1 1 1 1C1301 SC10U6D3V5MX-3GP C1302 SC10U6D3V5MX-3GP C1303 SC10U6D3V5MX-3GP C1304 SC10U6D3V5MX-3GP C1305 C1306 C1307 C1308
CPU1G
7 OF 9
1
D
2
2
2
2
2
2
2
2
DY
DY
DY
DY UMASC10U6D3V5MX-3GP
UMASC10U6D3V5MX-3GP SC10U6D3V5MX-3GP
UMASC10U6D3V5MX-3GP
UMASC10U6D3V5MX-3GP
DIS2
R1302 0R3J-0-U-GP
- 1.5V RAILS
C
Please note that the VTT Rail Values are: Auburndale VTT=1.05V Clarksfield VTT=1.1V
POWER
AT21 AT19 AT18 AT16 AR21 AR19 AR18 AR16 AP21 AP19 AP18 AP16 AN21 AN19 AN18 AN16 AM21 AM19 AM18 AM16 AL21 AL19 AL18 AL16 AK21 AK19 AK18 AK16 AJ21 AJ19 AJ18 AJ16 AH21 AH19 AH18 AH16
VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG
CLARKSFIELD
SENSE LINES
VAXG_SENSE VSSAXG_SENSE
AR22 AT22
VCC_AXG_SENSE 53 VSS_AXG_SENSE 53
D
GRAPHICS VIDs
GFX_VID GFX_VID GFX_VID GFX_VID GFX_VID GFX_VID GFX_VID GFX_VR_EN GFX_DPRSLPVR GFX_IMON
AM22 AP22 AN22 AP23 AM23 AP24 AN24R1305
GFX_VID0 GFX_VID1 GFX_VID2 GFX_VID3 GFX_VID4 GFX_VID5 GFX_VID6
53 53 53 53 53 53 53
1
1
1
1
1
1
1
C1309 SC1U6D3V2KX-GP SC1U6D3V2KX-GP
C1310 SC1U6D3V2KX-GP SC1U6D3V2KX-GP
C1311 SC1U6D3V2KX-GP SC1U6D3V2KX-GP
C1312 SC1U6D3V2KX-GP SC1U6D3V2KX-GP
C1313 SC1U6D3V2KX-GP SC1U6D3V2KX-GP
C1314 SC22U6D3V5MX-2GP
C1315
1
2
2
2
2
2
2
2
2
1
1
1
C1331 SCD1U10V2KX-5GP
C1332 SCD1U10V2KX-5GP SCD1U10V2KX-5GP
C1333 SCD1U10V2KX-5GP SCD1U10V2KX-5GP
C1334 SCD1U10V2KX-5GP
DY2
DY2
DY2
+1.05V_VTT
DDR3
1
C1316 SC10U6D3V5KX-1GP
1
C1317 SC10U6D3V5KX-1GP
J24 J23 H25
VTT1 VTT1 VTT1
x01 change tolerant 20091117+1.05V_VTT
VTT0 VTT0 VTT0 VTT0
P10 N10 L10 K10 1C1318 SC10U6D3V5KX-1GP
2
2
2.6A1C1319 SC10U6D3V5KX-1GP
2
1.1V
1
1
1
B
C1320 SC10U6D3V5KX-1GP
DY
1
C1321 SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP
C1322 SC10U6D3V5KX-1GP
C1323 SC10U6D3V5KX-1GP
1.8V
K26 J27 J26 J25 H27 G28 G27 G26 F26 E26 E25
VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1
VTT1 VTT1 VTT1 VTT1 VTT1 VTT1
J22 J20 J18 H21 H20 H19
2
+1.05V_VTT
x01 change tolerant 20091117
18A
x01 change tolerant 200911171C1324 SC10U6D3V5KX-1GP
+1.05V_VTTB
2
2
2
2
C1325 SC4D7U6D3V3KX-GP DY
2
VCCPLL VCCPLL VCCPLL
L26 L27 M26
2
1
1.35A2 2 1 1C1328 C1329 SC2D2U6D3V3KX-GP SC2D2U6D3V3KX-GP
+1.8V_RUN
1
C1330 SC10U6D3V5MX-3GP
1
1
2
2
CLARKUNF
x01 change tolerant 20091117
A
2
C1326 SC1U6D3V2KX-GP
C1327
2
1
GRAPHICSFDI PEG & DMI
2
AR25 AT25 AM24
UMA1 R1304
1 4K7R2J-2-GP
GFX_IMON_C
DY
2 0R2J-2-GP
GFX_VR_EN 53 GFX_DPRSLPVR 53 GFX_IMON 53 +1.5V_RUN_CPU
1 R1303 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ AJ1 AF1 AE7 AE4 AC1 AB7 AB4 Y1 W7 W4 U1 T7 T4 P1 N7 N4 L1 H1
2 DIS 1KR2J-1-GP
3ATC1301 +1.5V_SUSC
DY SE330U2D5VDM-2GP x01 change tolerant 20091117 S3 Reduction
SC22U6D3V5MX-2GP
DY
SC4D7U6D3V3KX-GP
SC1U6D3V2KX-GP
A
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Date:5 4 3 2
Wistron Corporation
Document Number
CPU (VCC_GFXCORE)BerrySheet1
Rev
A0013 of 92
Monday, March 29, 2010
5
4
3
2
1
SSID = CPUCPU1H 8 OF 9 CPU1I 9 OF 9
D
C
B
AT20 AT17 AR31 AR28 AR26 AR24 AR23 AR20 AR17 AR15 AR12 AR9 AR6 AR3 AP20 AP17 AP13 AP10 AP7 AP4 AP2 AN34 AN31 AN23 AN20 AN17 AM29 AM27 AM25 AM20 AM17 AM14 AM11 AM8 AM5 AM2 AL34 AL31 AL23 AL20 AL17 AL12 AL9 AL6 AL3 AK29 AK27 AK25 AK20 AK17 AJ31 AJ23 AJ20 AJ17 AJ14 AJ11 AJ8 AJ5 AJ2 AH35 AH34 AH33 AH32 AH31 AH30 AH29 AH28 AH27 AH26 AH20 AH17 AH13 AH9 AH6 AH3 AG10 AF8 AF4 AF2 AE35
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M10 L35 L32 L29 L8 L5 L2 K34 K33 K30
K27 K9 K6 K3 J32 J30 J21 J19 H35 H32 H28 H26 H24 H22 H18 H15 H13 H11 H8 H5 H2 G34 G31 G20 G9 G6 G3 F30 F27 F25 F22 F19 F16 E35 E32 E29 E24 E21 E18 E13 E11 E8 E5 E2 D33 D30 D26 D9 D6 D3 C34 C32 C29 C28 C24 C22 C20 C19 C16 B31 B25 B21 B18 B17 B13 B11 B8 B6 B4 A29 A27 A23 A9
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
CLARKSFIELD
CLARKSFIELD
D
C
VSS
NCYF TEST PIN: A35,AT1,AT35,B1,A3,A33,A34, AP1,AP35,AR1,AR35,AT2,AT3, AT33,AT34,C1,C35,B35
NCTF
VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF#A35 VSS_NCTF#AT1 VSS_NCTF#AT35 VSS_NCTF#B1 RSVD_NCTF#A3 RSVD_NCTF#A33 RSVD_NCTF#A34 RSVD_NCTF#AP1 RSVD_NCTF#AP35 RSVD_NCTF#AR1 RSVD_NCTF#AR35 RSVD_NCTF#AT2 RSVD_NCTF#AT3 RSVD_NCTF#AT33 RSVD_NCTF#AT34 RSVD_NCTF#C1 RSVD_NCTF#C35 RSVD_NCTF#B35
AR34 B34 B2 A35 AT1 AT35 B1 A3 A33 A34 AP1 AP35 AR1 AR35 AT2 AT3 AT33 AT34 C1 C35 B35TP_MCP_VSS_NCTF1 TP_MCP_VSS_NCTF2 TP_MCP_VSS_NCTF3 TP_MCP_VSS_NCTF4
1 1 1 1
TP1401 TP1402 TP1403 TP1404
B
CLARKUNF
CLARKUNF
A
A
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
Wistron Corporation
CPU (VSS)Size Date:5 4 3 2
Document Number
Rev
BerryW ednesday, February 10, 2010 Sheet1
A0014 of 92
5
4
3
2
1
D
D
C
C
(Blanking)
B
B
A
A
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date:5 4 3 2
Wistron Corporation
Document Number
ReservedSheet1
Rev
BerryW ednesday, February 10, 2010 15 of 92
A00
5
4
3
2
1
D
D
C
C
(Blanking)
B
B
A
A
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date:5 4 3 2
Wistron Corporation
Document Number
ReservedSheet1
Rev
BerryW ednesday, February 10, 2010 16 of 92
A00
5
4
3
2
1
D
D
C
C
(Blanking)
B
B
A
A
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date:5 4 3 2
Wistron Corporation
Document Number
ReservedSheet1
Rev
BerryW ednesday, February 10, 2010 17 of 92
A00
5
4
3
2
1
SSID = MEMORYDM1 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15 10 M_A_BS2 10 M_A_BS0 10 M_A_BS1 10 M_A_DQ[63..0] 98 97 96 95 92 91 90 86 89 85 107 84 83 119 80 78 79 109 108 M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 10 M_ODT0 10 M_ODT1 +V_DDR_REF C1819 SC1U6D3V2KX-GP C1820 SC1U6D3V2KX-GP C1821 SC1U6D3V2KX-GP C1822 SC1U6D3V2KX-GP 1 1 1 1 5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194 10 27 45 62 135 152 169 186 12 29 47 64 137 154 171 188 116 120 126 1 30 203 204 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2 BA0 BA1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7# DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 ODT0 ODT1 VREF_CA VREF_DQ RESET# VTT1 VTT2 NP1 NP2 RAS# WE# CAS# CS0# CS1# CKE0 CKE1 CK0 CK0# CK1 CK1# DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 SDA SCL EVENT# VDDSPD SA0 SA1 NC#1 NC#2 NC#/TEST VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NP1 NP2 110 113 115 114 121 73 74 101 103 102 104 11 28 46 63 136 153 170 187 200 202 198 199 197 201 77 122 125 75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124 2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206 SA0_DIM0 SA1_DIM0 M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7
M_A_DM[7..0]
10 10 10 10
M_A_DQS#[7..0] M_A_DQS[7..0] M_A_A[15..0]
M_A_RAS# 10 M_A_WE# 10 M_A_CAS# 10 M_CS#0 10 M_CS#1 10 M_CKE0 10 M_CKE1 10
SA0_DIM0 SA1_DIM0 1 1
Note: If SA0 DIM0 = 0, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA0 SO-DIMMA TS Address is 0x30R1803 10KR2J-3-GP 2 2 R1804 10KR2J-3-GP
D
If SA0 DIM0 = 1, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA2 SO-DIMMA TS Address is 0x32
D
M_CLK_DDR0 10 M_CLK_DDR#0 10 M_CLK_DDR1 10 M_CLK_DDR#1 10
PCH_SMBDATA 7,19,23,76 PCH_SMBCLK 7,19,23,76 PM_EXTTS#0 9 +3.3V_RUN
C1802
x01 change tolerant 20091117
1
2
+1.5V_SUS
2
C1801 SCD1U10V2KX-5GP
DY
1
SC2D2U6D3V3KX-GP
+1.5V_SUS
SODIMM A DECOUPLING x01 change tolerant 20091117TC1801 SE330U2D5VDM-2GP C1803 SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP C1804 SC10U6D3V5KX-1GP C1805 SC10U10V5ZY-1GP C1806 SC10U6D3V5KX-1GP C1807 SC10U6D3V5KX-1GP C1808 SC10U10V5ZY-1GP C1809 SC10U6D3V5KX-1GP C1810 SC10U6D3V5KX-1GPC
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
+V_DDR_REF
x01 change tolerant 200911181 1 C1812 SC2D2U6D3V3KX-GP 1
2
2
2
C1811 SCD1U10V2KX-5GP
DY
C1813 SCD1U10V2KX-5GP
1
1
1
Layout Note: Place these Caps near SO-DIMMA.
1
C1814 SCD1U10V2KX-5GP
C1815 SCD1U10V2KX-5GP
C1816 SCD1U10V2KX-5GP
C1817 SCD1U10V2KX-5GP
x01 change tolerant 20091117
2
2
2
2
S3 Power Reduction+0.75V_DDR_VTT 1
+0.75V_DDR_VTT
R1806 22R2J-2-GP 2B
B
1
+0.75V_DDR_VTT
Place these caps close to VTT1 and VTT2.
2
DY
C1818 SC10U6D3V5KX-1GP
Q1801
. . . .G
DY2
DY2
9,19 DDR3_DRAMRST# +0.75V_DDR_VTT
2
2
42,50 PS_S3CNTRL
84.2N702.D31
x01 change tolerant 20091117
H =4mm
DDR3-204P-47-GP
62.10017.P31 SEC. 62.10017.P11
A
S
2N7002E-1-GP
D
.
2
2
DY
DY
DY
DY
DY
1
C
DISCHARGE_0D75VA
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
DDR3-SODIMM1Size Date:5 4 3 2
Document Number
Rev
BerryMonday, March 29, 20101
A00Sheet 18 of 92
5
4
3
2
1
SSID = MEMORYM_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15D
DM2 98 97 96 95 92 91 90 86 89 85 107 84 83 119 80 78 79 109 108 M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 10 M_ODT2 10 M_ODT3 +V_DDR_REF +0.75V_DDR_VTT 5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194 10 27 45 62 135 152 169 186 12 29 47 64 137 154 171 188 116 120 126 1 30 203 204 C1918 SC1U6D3V2KX-GP C1919 SC1U6D3V2KX-GP C1920 SC1U6D3V2KX-GP C1921 SC1U6D3V2KX-GP A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2 BA0 BA1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7# DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 ODT0 ODT1 VREF_CA VREF_DQ RESET# VTT1 VTT2 NP1 NP2 RAS# WE# CAS# CS0# CS1# CKE0 CKE1 CK0 CK0# CK1 CK1# DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 SDA SCL EVENT# VDDSPD SA0 SA1 NC#1 NC#2 NC#/TEST VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NP1 NP2 110 113 115 114 121 73 74 101 103 102 104 11 28 46 63 136 153 170 187 200 202 198 199 1 197 201 77 122 125 75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124 2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206 SA0_DIM1 SA1_DIM1 1 C1902 SC2D2U6D3V3KX-GP C1901 SCD1U10V2KX-5GP +1.5V_SUS M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7 PCH_SMBDATA 7,18,23,76 PCH_SMBCLK 7,18,23,76 PM_EXTTS#1 9 +3.3V_RUN M_B_RAS# 10 M_B_WE# 10 M_B_CAS# 10 M_CS#2 10 M_CS#3 10 M_CKE2 10 M_CKE3 10 M_CLK_DDR2 10 M_CLK_DDR#2 10 M_CLK_DDR3 10 M_CLK_DDR#3 10 M_B_DM[7..0] 10 10 10 10 2 1 M_B_DQS[7..0] M_B_A[15..0] R1902 10KR2J-3-GP +3.3V_RUN
M_B_DQS#[7..0]
SA1_DIM1 SA0_DIM1 1
Note: If SA0 DIM0 = 0, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA0 SO-DIMMA TS Address is 0x30D
10 M_B_BS2 10 M_B_BS0 10 M_B_BS1 10 M_B_DQ[63..0]
R1903 10KR2J-3-GP 2
If SA0 DIM0 = 1, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA2 SO-DIMMA TS Address is 0x32
2
x01 change tolerant 20091118
C
2
DY
C
SODIMM B DECOUPLING+1.5V_SUS
x01 change tolerant 20091117C1903 SC10U10V5ZY-1GP C1904 SC10U10V5ZY-1GP C1905 SC10U6D3V5KX-1GP C1906 SC10U6D3V5KX-1GP C1907 SC10U6D3V5KX-1GP C1908 SC10U10V5ZY-1GP C1909 SC10U6D3V5KX-1GP C1910 SC10U6D3V5KX-1GP
1
1
1
1
1
1
1
DY2
2
2
2
2
2
2
x01 change tolerant 200911171 1 1 SCD1U10V2KX-5GP 2 SCD1U10V2KX-5GP 2
Layout Note: Place these Caps near SO-DIMMB.
B
SCD1U10V2KX-5GP 2
2
1
C1911 SCD1U10V2KX-5GP
C1912
C1913
C1914
2
DY
DY
DY
1
B
+V_DDR_REF
x01 change tolerant 200911181 1 C1916 SC2D2U6D3V3KX-GP 1 2 C1917 SCD1U10V2KX-5GP
2
2
C1915 SCD1U10V2KX-5GP
DY
9,18 DDR3_DRAMRST#
Place these caps close to VTT1 and VTT2.
H = 8mm
1
1
1
1
DDR3-204P-55-GP
DY2
DY2
2
2
62.10017.Q31 SEC. 62.10017.N71Note: SO-DIMMB SPD Address is 0xA4 SO-DIMMB TS Address is 0x34 SO-DIMMB is placed farther from the Processor than SO-DIMMA
x01 change tolerant 20091117
A
A
Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
DDR3-SODIMM2Size Date:5 4 3 2
Document Number
Rev
BerryMonday, March 29, 20101
A00Sheet 19 of 92
5
4
3
2
1
+3.3V_RUN
55 PCH_VGA_BLEN 55 PCH_LCDVDD_END
T48 T47 Y48LDDC_CLK_PCH LDDC_DATA_PCH LCTRL_CLK LCTRL_DATA LIBG
L_BKLTEN L_VDD_EN L_BKLTCTL L_DDC_CLK L_DDC_DATA L_CTRL_CLK L_CTRL_DATA LVD_IBG LVD_VBG LVD_VREFH LVD_VREFL LVDSA_CLK# LVDSA_CLK
SDVO_TVCLKINN SDVO_TVCLKINP SDVO_STALLN SDVO_STALLP SDVO_INTN SDVO_INTP
BJ46 BG46 BJ48 BG48 BF45 BH45
4 3RN2006
U2001D
4 OF 10
RN2001 54,82 GPU_LVDS_CLK 54,82 GPU_LVDS_DATA
55 PCH_LBKLT_CTL
UMASRN2K2J-1-GPD
1 2
UMA
4 3
AB48 Y45 AB46 V48 AP39 AP41
SRN0J-6-GP
R2002
1
TPAD14-GP R2001 2K37R2F-GP
TP2001
2
DY
1 PCH_LCDVDD_EN
Place near PCH UMA2
1LVDS_VBG RN2004 1 4 LVD_VREFH AT43 2 3 LVD_VREFL AT42
SDVO_CTRLCLK SDVO_CTRLDATA DDPB_AUXN DDPB_AUXP DDPB_HPD DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P DDPC_CTRLCLK DDPC_CTRLDATA DDPC_AUXN DDPC_AUXP DDPC_HPD DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P DDPD_CTRLCLK DDPD_CTRLDATA DDPD_AUXN DDPD_AUXP DDPD_HPD DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P
T51 T53 BG44 BJ44 AU38 BD42 BC42 BJ42 BG42 BB40 BA40 AW38 BA38 Y49 AB49 BE44 BD44 AV40 BE40 BD40 BF41 BH41 BD38 BC38 BB36 BA36 U50 U52 BC46 BD46 AT38 BJ40 BG40 BJ38 BG38 BF37 BH37 BE36 BD36HDMI_DATA2#_C HDMI_DATA2_C HDMI_DATA1#_C HDMI_DATA1_C HDMI_DATA0#_C HDMI_DATA0_C HDMI_CLK#_C HDMI_CLK_C
1 2
PCH_HDMI_CLK 57 PCH_HDMI_DATA 57
UMA
100KR2J-1-GP
SRN0J-6-GP 55 PCH_LVDSA_TXC# 55 PCH_LVDSA_TXC 55 PCH_LVDSA_TX0# 55 PCH_LVDSA_TX1# 55 PCH_LVDSA_TX2#
AV53 AV51 BB47 BA52 AY48 AV47 BB48 BA50 AY49 AV48 AP48 AP47 AY53 AT49 AU52 AT53 AY51 AT48 AU50 AT51
LVDS
HDMI_PCH_DET
57
+3.3V_RUN 55 PCH_LVDSA_TX0 55 PCH_LVDSA_TX1 55 PCH_LVDSA_TX2
Impedance:85 ohm4 3 2 1C
LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3 LVDSB_CLK# LVDSB_CLK LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3 LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3
Digital Display Interface
LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3
UMA1 UMA1 UMA1 UMA1 UMA1 UMA1 UMA1 UMA1
2 2 2 2 2 2 2 2
C2001 C2002 C2003 C2004 C2005 C2006 C2007 C2008
SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP
HDMI_PCH_DATA2# 57,82 HDMI_PCH_DATA2 57,82 HDMI_PCH_DATA1# 57,82 HDMI_PCH_DATA1 57,82 HDMI_PCH_DATA0# 57,82 HDMI_PCH_DATA0 57,82 HDMI_PCH_CLK# 57,82 HDMI_PCH_CLK 57,82
Close to VGAC
UMA5 6 7 8
RN2002 SRN2K2J-4-GP
55 PCH_LVDSB_TXC# 55 PCH_LVDSB_TXC 55 PCH_LVDSB_TX0# 55 PCH_LVDSB_TX1# 55 PCH_LVDSB_TX2# 55 PCH_LVDSB_TX0 55 PCH_LVDSB_TX1 55 PCH_LVDSB_TX2
Impedance:85 ohm
Impedance:100 ohm
LCTRL_DATA LCTRL_CLK LDDC_CLK_PCH LDDC_DATA_PCH
Close to ball
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