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Daniele Ielmini
Logic and neuromorphic computing with
resistive switches
Daniele Ielmini
Dipartimento di Elettronica, Informazione e Bioingegneria
Politecnico di Milano
daniele.ielmini@polimi.it
Daniele Ielmini
Outline
• Introduction
• Logic computing with resistive switches
Logic gates
1-bit adder
• Neuromorphic computing with resistive switches
2T1R synapse
1T1R synapse
Demonstration of unsupervised learning
• Conclusions
2
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Daniele Ielmini
Extending Moore’s law 3
MEMS RF CMOS Image sensors
III-V semiconductors Tunnel FET
2D semiconductors
Spintronics Quantum computing Memristor
G-ReRAM Workshop
ITRS 2013
Daniele Ielmini
RRAM device 4
Set Reset
VA VA < 0
VA TiN
TiN
HfO2 Ti Set
Reset
IC = 9 mA
VA > 0
G-ReRAM Workshop
Daniele Ielmini
Outline
• Introduction
• Logic computing with resistive switches
Logic gates
1-bit adder
• Neuromorphic computing with resistive switches
2T1R synapse
1T1R synapse
Demonstration of unsupervised learning
• Conclusions
5
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Daniele Ielmini
Conditional switching: the HP approach 7
G-ReRAM Workshop
• Apply voltages Vcond and Vset:
p=0 unconditional set
p=1 no change in q
• Issues:
All other logic functions must be constructed from IMP
Transfer missing
J. Borghetti, et al.,
Nature 464, 873 (2010)
Daniele Ielmini
AND gate 8
G-ReRAM Workshop
Enable pulse
P = 0
Q = 0
P’ = 0
Q’ = 0
P = 1
Q = 1
P’ = 1
Q’ = 1
P = 0
Q = 1
P’ = 0 Q’ = 0
P = 1
Q = 0 P’ = 0
Q’ = 0 P
Q
I VQ VP
V
P’ Q = 0
P = 1
Q’ = 0
P’ = 0
V V
VQ VP
P Q
I
VP
VQ
V
Q = 0
P = 0
Q’ = 0
P’ = 0
V > 0 V
V
P
I VP
Q’
VQ
Q
V
Q = 1
P = 0
Q’ = 0
P’ = 0
V
VP
P Q
I VQ
V
Q = 1
P = 1
Q’ = 1
P’ = 1
V V
P' = Q' = P*Q
AND condition:
Vset < V < 2Vset
P Q P'=P*Q Q'=P*Q
0 0 0 0
0 1 0 0
1 0 0 0
1 1 1 1
Q = 1: bit transfer
S. Balatti, et al., IEEE
T-ED 62, 1831 (2015)
Daniele Ielmini
Material implication (IMP) 9
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V
Enable pulse
V V
|V|
P
I VQ VP
Q = 0*
P = 1
Q’ = 0*
P’ = 1
V
P
I VP
Q
VQ
|V|
Q = 1
P = 0
Q’ = 1
P’ = 0
V V
VP
P Q
I VQ
|V|
Q = 1
P = 1
Q’ = 1
P’ = 1
Q' = PQ
IMP condition:
Q = 0*: NOT gate
V VQ VP
P Q = 0*
I
|V|
Q’ VP
VQ Q = 0*
P = 0
Q’ = 1
P’ = 0
V < 0
P = 0
Q = 0* P’ = 0
Q’ = 1
P = 1
Q = 1
P’ = 1
Q’ = 1
P = 0
Q = 1
P’ = 0
Q’ = 1
P = 1
Q = 0*
P’ = 1
Q’ = 0*
|V| > |Vreset|
P Q P'=P Q'=PQ
0 0* 0 1
0 1 0 1
1 0* 1 0*
1 1 1 1
Daniele Ielmini
State 0* 10
G-ReRAM Workshop
VC
V
Vset
VC
V
Vset
VC
V
Vset
0 0
0* 1
Q = 0*
P = 0
Q’ = 1
P’ = 0
P = 0
Q = 0
P, Q ?
Unpredictable
reset
Regeneration of state 0*:
Daniele Ielmini
1-bit adder 12
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S. Balatti, et al., IEEE Trans. Electron Devices 62, 1839 (2015)
Daniele Ielmini
Logic computing: summary
• Resistive-switch logic demonstrated with input variable =
output variable = R
• Advantages:
Universal logic gate as opposed to topogical gates
such as CMOS
Ultrahigh density in 3D crosspoint array
Zero static power thanks to nonvolatile switch
Logic-in-memory overcoming the memory bottleneck of
traditional Von Neumann architecture
• Disadvantages:
Resistive switching is slow and power hungry
Limited endurance
Switching variability
14
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Daniele Ielmini
Outline
• Introduction
• Logic computing with resistive switches
Logic gates
1-bit adder
• Neuromorphic computing with resistive switches
2T1R synapse
1T1R synapse
Demonstration of unsupervised learning
• Conclusions
15
G-ReRAM Workshop
Daniele Ielmini
Neuromorphic computing 16
G-ReRAM Workshop
• Neuromorphic architectures aim at
replicating cognitive behaviors
(learning, recognition, decision
making)
• Density in the human cortex
Cells = 107 cm-2
Synapses = 1011 cm-2 (104 average
connectivity)
In vivo In silico
Neuron CMOS
Axons/dendrites Interconnect
Synapses RRAM/memristors
Daniele Ielmini
17
Pre-synaptic
neuron
Post-synaptic
neuron
Potentiation
Dt > 0
Depression
Dt < 0
Dt=tpost - tpre
DG
Synapse PRE POST
Spike timing dependent plasticity (STDP)
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Daniele Ielmini
Spike timing dependent plasticity (STDP) 18
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Memristor + control logic for time-
voltage conversion
S. H. Jo, et al., Nano Lett. 10 (2010)
G.-Q. Bi and M.-M. Poo,
J. Neuroscience 18, 1998
Daniele Ielmini
2-transistor/1-resistor (2T1R) approach 19
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Fire gate PRE VCG
Communication
gate BE
VTE
- +
VTE
VCG
POST
C
Integrate Fire
Vint
VFG
Daniele Ielmini
Communication 20
G-ReRAM Workshop
Fire gate PRE VCG
Communication
gate BE
VTE
- +
VTE
VCG
POST
C
Integrate Fire
Vint
VFG
t
t
VTE
VCG
VTE,max
VTE,min
150ms
1ms
Daniele Ielmini
t
t
VTE
VFG
Dt > 0
Long-term potentiation (LTP) 21
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Fire gate PRE VCG
Communication
gate BE
VTE
- +
VTE
VCG
POST
C
Integrate Fire
Vint
VFG
VTE,max
VTE,min
150ms
1ms
Daniele Ielmini
t
t
VTE
VFG
Dt < 0
Long-term depression (LTD) 22
G-ReRAM Workshop
Fire gate PRE VCG
Communication
gate BE
VTE
- +
VTE
VCG
POST
C
Integrate Fire
Vint
VFG
VTE,max
VTE,min
150ms
1ms
Daniele Ielmini
STDP dependence on HRS and LRS
• STDP demonstrated for both partial LRS (variable IC) and
partial HRS (variable Vstop)
• Analytical model accounts for measurements
23
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|Vstop|
|Vstop|
S. Ambrogio, et al., IEEE T-ED 61 (2014)
IC
Daniele Ielmini
STDP dependence on random state
• STDP demonstrated in 2T1R synapses
• Suitable for unsupervised learning
• Issue: 2T1R circuit might be too large to achieve high density
synaptic networks
24
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Measured Calculated
0
1
0.75
0.5
0.25
Z.-Q. Wang, et al., Front. Neurosci. 8(438) 2015
Daniele Ielmini
1T1R synapse 25
PRE
-
VG
POST
Integrate Fire
Vint
VG BE
+
VTE Synapse
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Daniele Ielmini
26
PRE
- +
VG
Synapse PRE spike
VTE = const.
VTE
Integrate Fire
BE VG
POST
Vint
Communication
G-ReRAM Workshop
Daniele Ielmini
27
-
PRE
Synapse
VG
VTE+
BE VG
VTE
+
VTE-
POST
Integrate Fire
Vint
POST spike
PRE spike
Plasticity
G-ReRAM Workshop
Daniele Ielmini
Depression (Dt < 0) 28
-
Dt<0
Reset
PRE
Synapse
VG BE
+
VTE
POST spike
PRE spike
VG
POST
Integrate Fire
Vint
PRE spike
G-ReRAM Workshop
Daniele Ielmini
Potentiation (Dt > 0) 29
-
Dt>0
PRE
VG BE
+
VTE
VG
Set
POST
Integrate Fire
Vint
Synapse
POST spike
PRE spike
PRE spike
G-ReRAM Workshop
Daniele Ielmini
STDP characteristics
• State-dependent STDP characteristics can be reproduced by our
analytical RRAM model
• Squared STDP is not quite bio-realistic: can it learn?
30
Data Simulations
S. Ambrogio, et al. IEEE T-ED, 61(7) (2014)
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Daniele Ielmini
31
First layer (64
neurons)
Pattern
Synapses
PRE
POST 1
…
1
2
3
64
Learning demonstration by simulations
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Daniele Ielmini
32
Abrupt set/reset transitions make learning unstable
Unsupervised pattern learning
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Daniele Ielmini 33
B
A
C A
C B
Stochastic set emulates gradual set
VA
HRS
LRS
Set variability
G-ReRAM Workshop
Daniele Ielmini
34
Improved learning with 50% set probability
Pattern learning by stochastic STDP
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Daniele Ielmini
35
Second layer
(4 neurons)
Inhibitory synapses
Pattern First layer
(3600 neurons)
Synapses
Pesi N1 Pesi N2
Pesi N3 Pesi N4
Input
G-ReRAM Workshop
Learning of multiple patterns
Daniele Ielmini
• Logic gates for multiple
operations (AND, IMP OR,
etc.), transfer, cascading
• STDP demonstrated with
RRAM using 2T1R and
1T1R synapses
• Pattern learning, forgetting
and recognition
demonstrated through
simulations
36
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Summary
1 2 3 4 5 6 7 8
1
2
3
4
5
6
7
8
1 2 3 4 5 6 7 8
1
2
3
4
5
6
7
8
Initial state Final state
Measured Calculated
0
1
0.75
0.5
0.25
P
Q
I VQ VP
V
P’
Q = 0
P = 1
Q’ = 0
P’ = 0
V V
Daniele Ielmini
Acknowledgments
• Postdocs: S. Balatti, N. Ciocchini, Z.-Q. Wang
• Students: S. Ambrogio, M. Laudato, R. Carboni,
V. Milo, A. Taddei, A. Amirkhani, S. Ozdem,
A. Bricalli, G. Pedretti, E. Ambrosi, F. Polino
• Support:
37
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2014 Consolidator Grant:
RESCUE – Resistive-switch computing beyond CMOS
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