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CPSC318 Lecture 8 Vuong Spring 04 UBC1
Cpsc 318Computer Structures
Lecture 8 Assembly Programming
Instruction Representation (2)
Dr. Son Vuong
(vuong@cs.ubc.ca)
Feb 3, 2002
CPSC318 Lecture 8 Vuong Spring 04 UBC2
Overview
Arithmetic and data transfer instructions
Branch instructions
Calling procedures
Register conventions
Shift, Load/Store Bytes Instructions
Instruction representation (2)
CPSC318 Lecture 8 Vuong Spring 04 UBC3
ReviewMIPS defines instructions to be same size as
data (one word) so that they can use the same memory (can use lw and sw).
Machine Language Instruction: 32 bits representing a single instruction
opcode rs rt Immediate (16)opcode rs rt rd functshamtR
I
Computer actually stores programs as a series of these machine intructions.
opcode target address (26)J
CPSC318 Lecture 8 Vuong Spring 04 UBC4
Outline
Addressing modes
Branch instruction encoding
Jump instructions
Disassembly
Pseudoinstructions and “True” Assembly Language (TAL) vs. “MIPS” Assembly Language (MAL)
CPSC318 Lecture 8 Vuong Spring 04 UBC5
Addressing modesRegister addressing
add $t0,$s1,$s2
Base or displacement addressing sw $17,32($18)
Immediate addressing add $t0,$s1, 4 #part of the instruction
PC-relative addressing beq $s4, $s5, Label
Pseudo-direct addressing j 80000 # jump to location 80000
CPSC318 Lecture 8 Vuong Spring 04 UBC6
Addressing modes
op rs rt immediate
op rs rt rd ... funct
op Address (26 bits)
op rs rt Address (16b)
op rs rt Address (16b)
+
+
:
register
PC
PC
register
byte halfword word
word
word
memory
memory
memory
Immediate addressing
Register addressing
Base addressing
PC-relative addressing
Pseudo-direct addressing
CPSC318 Lecture 8 Vuong Spring 04 UBC7
Branches: PC-Relative Addressing (1/5)Use I-Format
opcode rs rt immediate
opcode specifies beq v. bne
Rs and Rt specify registers to compare
What can immediate specify?Immediate is only 16 bitsPC is 32-bit pointer to memorySo immediate cannot specify entire address to
branch to.
CPSC318 Lecture 8 Vuong Spring 04 UBC8
Branches: PC-Relative Addressing (2/5)How do we usually use branches?
Answer: if-else, while, forLoops are generally small: typically up to 50
instructionsFunction calls and unconditional jumps are done
using jump instructions (j and jal), not the branches.
Conclusion: Though we may want to branch to anywhere in memory, a single branch will generally change the PC by a very small amount.
CPSC318 Lecture 8 Vuong Spring 04 UBC9
Branches: PC-Relative Addressing (3/5)Solution: PC-Relative Addressing
Let the 16-bit immediate field be a signed two’s complement integer to be added to the PC if we take the branch.
Now we can branch +/- 215 bytes from the PC, which should be enough to cover any loop.
Any ideas to further optimize this?
CPSC318 Lecture 8 Vuong Spring 04 UBC10
Branches: PC-Relative Addressing (4/5)Note: Instructions are words, so they’re word
aligned (byte address is always a multiple of 4, which means it ends with 00 in binary).
So the number of bytes to add to the PC will always be a multiple of 4.
So specify the immediate in words.
Now, we can branch +/- 215 words from the PC (or +/- 217 bytes), so we can handle loops 4 times as large.
CPSC318 Lecture 8 Vuong Spring 04 UBC11
Branches: PC-Relative Addressing (5/5)Branch Calculation:
If we don’t take the branch:
PC = PC + 4
PC+4 = byte address of next instruction
If we do take the branch:
PC = (PC + 4) + (immediate * 4)Observations
Immediate field specifies the number of words to jump, which is simply the number of instructions to jump.
Immediate field can be positive or negative. Due to hardware, add immediate to (PC+4),
not to PC; will be clearer why later in course
CPSC318 Lecture 8 Vuong Spring 04 UBC12
Branch Example (1/3)
MIPS Code:Loop: beq $9,$0,End
add $8,$8,$10addi $9,$9,-1
j Loop
End:
Branch is I-Format:opcode = 4 (look up in table)
rs = 9 (first operand)
rt = 0 (second operand)
immediate = ???
CPSC318 Lecture 8 Vuong Spring 04 UBC13
Branch Example (2/3)
MIPS Code:Loop: beq $9,$0,End
addi $8,$8,$10addi $9,$9,-1
j Loop
End:
Immediate Field:Number of instructions to add to (or subtract
from) the PC, starting at the instruction following the branch.
In beq case, immediate = 3
CPSC318 Lecture 8 Vuong Spring 04 UBC14
Branch Example (3/3)MIPS Code:
Loop: beq $9,$0,Endaddi $8,$8,$10
addi $9,$9,-1 j Loop
End:
4 9 0 3
Decimal representation:
Binary representation:
000100 01001 00000 0000000000000011
CPSC318 Lecture 8 Vuong Spring 04 UBC15
Questions on PC-addressing
Does the value in branch field change if we move the code?
What do we do if its > 2^15 instructions?
Since its limited to +- 2^15 instructions, doesn’t this generate lots of extra MIPS instructions?
Why do we need all these addressing modes? Why not just one?
CPSC318 Lecture 8 Vuong Spring 04 UBC16
J-Format Instructions (1/5)For branches, we assumed that we won’t
want to branch too far, so we can specify change in PC.
For general jumps (j and jal), we may jump to anywhere in memory.
Ideally, we could specify a 32-bit memory address to jump to.
Unfortunately, we can’t fit both a 6-bit opcode and a 32-bit address into a single 32-bit word, so we compromise.
CPSC318 Lecture 8 Vuong Spring 04 UBC17
J-Format Instructions (2/5)Define “fields” of the following number of
bits each:
6 bits 26 bits
opcode target address
As usual, each field has a name:
Key ConceptsKeep opcode field identical to R-format and I-
format for consistency.Combine all other fields to make room for large
target address.
CPSC318 Lecture 8 Vuong Spring 04 UBC18
J-Format Instructions (3/5)For now, we can specify 26 bits of the 32-bit
address.
Optimization:Note that, just like with branches, jumps will only
jump to word aligned addresses, so last two bits are always 00 (in binary).
So let’s just take this for granted and not even specify them.
CPSC318 Lecture 8 Vuong Spring 04 UBC19
J-Format Instructions (4/5)So, we can specify 28 bits of the 32-bit
address.
Where do we get the other 4 bits?By definition, take the 4 highest order bits from
the PC.Technically, this means that we cannot jump to anywhere in memory, but it’s adequate 99.9999…% of the time, since programs aren’t that long.
If we absolutely need to specify a 32-bit address, we can always put it in a register and use the jr instruction.
CPSC318 Lecture 8 Vuong Spring 04 UBC20
J-Format Instructions (5/5)Summary:
New PC = PC[31..28] || target address (26
bits) || 00 Note: II means concatenation
4 bits || 26 bits || 2 bits = 32-bit address
Understand where each part came from!
CPSC318 Lecture 8 Vuong Spring 04 UBC21
Computers in the news
9/10/01Fujitsu announced a new miniature humanoid robot, named HOAP-1 (Humanoid for Open Architecture Platform). Fujitsu is disclosing the internal interface architecture of HOAP-1 to allow users to develop their own programs. "Hoap-1 is the world's first attempt to sell a humanoid robot that users can program freely." Hoap-1 will run on RT-Linux. They hope to sell 100 units within 3 years, and price is about $40,000.
Height: 19 inchesWeight: 13 pounds20 degrees of freedom
CPSC318 Lecture 8 Vuong Spring 04 UBC22
Sony SDR-4X
Sony introduced the SDR-4X for Robodex 2002. Great new android to compete against the HOAP-1
CPSC318 Lecture 8 Vuong Spring 04 UBC23
Honda Asimo (2002)Honda Motor Co (Tokyo, Japan) has a new walking android called Asimo (Advanced Step in Innovative Mobility). This android is 1.2m tall (47.25"), 0.45m wide (18"), and 0.44m deep. Asimo weighs 43 kg (95 lb.).
A new version of Asimo is now available which understands human gestures and movements and which moves its head to follow the speaker. It will rent for 20 Million Yen per year ($166,666).
Honda has revealed that they spent more than $100 MILLION (US) on that project - estimated to be at least 200 man years. This android is referred to internally as P2.
CPSC318 Lecture 8 Vuong Spring 04 UBC24
HRP-2P (Kawada) (03/2002)
The robot, called HRP-2P (which stands for Humanoid Robotics Project-2 Prototype) is agile , and its creator Kawada says it will be good for more than just entertainment – this robot is designed to do useful work.HRP-2P runs on a real-time version of the Linux operating system, called ART-Linux.
HRP-2P was designed to resemble a human, with similar degrees of freedom in its arms and legs. The silver and blue-coloured HRP-2P is 154cm tall (just over 5 feet), and weighs 58kg, and has 30 DOF.
CPSC318 Lecture 8 Vuong Spring 04 UBC25
Outline
Branch instruction encoding
Jump instructions
Disassembly
Pseudoinstructions and “True” Assembly Language (TAL) v. “MIPS” Assembly Language (MAL)
CPSC318 Lecture 8 Vuong Spring 04 UBC26
Decoding Machine LanguageHow do we convert 1s and 0s to C code?
Machine language => C
For each 32 bits:Look at opcode: 0 means R-Format, 2 or 3 mean J-
Format, otherwise I-Format.Use instruction type to determine which fields
exist. Write out MIPS assembly code, converting each
field to name, register number/name, or decimal/hex number.
Logically convert this MIPS code into valid C code. Always possible? Unique?
CPSC318 Lecture 8 Vuong Spring 04 UBC27
Decoding Example (1/7)Here are six machine language instructions
in hex:
000010250005402A110000030044102020A5FFFF 08100001
Let the first instruction be at address 4,194,30410 (0x00400000).
Next step: convert to binary
CPSC318 Lecture 8 Vuong Spring 04 UBC28
Decoding Example (2/7)The six machine language instructions in binary:
0000000000000000000100000010010100000000000001010100000000101010000100010000000000000000000000110000000001000100000100000010000000100000101001011111111111111111 00001000000100000000000000000001
Next step: identify opcode and format
CPSC318 Lecture 8 Vuong Spring 04 UBC29
Decoding Example (3/7)Select the opcode (first 6 bits)
to determine the format:
0000000000000000000100000010010100000000000001010100000000101010000100010000000000000000000000110000000001000100000100000010000000100000101001011111111111111111 00001000000100000000000000000001
Look at opcode: 0 means R-Format,2 or 3 mean J-Format, otherwise I-Format.
Next step: separation of fields
RRIRIJ
Format:
CPSC318 Lecture 8 Vuong Spring 04 UBC30
Decoding Example (4/7)Fields separated based on format/opcode:
0 0 0 2 3700 0 5 8 4204 8 0 +30 2 4 2 3208 5 5 -12 1,048,577
Next step: translate (“disassemble”) to MIPS assembly instructions
R
R
I
R
I
J
Format:
CPSC318 Lecture 8 Vuong Spring 04 UBC31
Decoding Example (5/7)MIPS Assembly (Part 1):
0x00400000 or $2,$0,$00x00400004 slt $8,$0,$50x00400008 beq $8,$0,3
0x0040000c add $2,$2,$40x00400010 addi $5,$5,-10x00400014 j 0x100001
Better solution: translate to more meaningful instructions (fix the branch/jump and add labels)
CPSC318 Lecture 8 Vuong Spring 04 UBC32
MIPS Registers
The constant 0 $0 $zeroReserved for Assembler $1 $atReturn Values $2-$3 $v0-$v1Arguments $4-$7 $a0-$a3Temporary $8-$15 $t0-$t7Saved $16-$23 $s0-$s7More Temporary $24-$25 $t8-$t9Used by Kernel $26-27 $k0-$k1Global Pointer $28 $gpStack Pointer $29 $spFrame Pointer $30 $fpReturn Address $31 $ra
(From COD 2nd Ed. p. A-23)Use names for registers -- code is clearer!
CPSC318 Lecture 8 Vuong Spring 04 UBC33
Decoding Example (6/7)MIPS Assembly (Part 2):
or $v0,$0,$0
Loop: slt $t0,$0,$a1beq $t0,$0,Exit
add $v0,$v0,$a0addi $a1,$a1,-1
j Loop
Exit:Next step: translate to C code (be creative!)
CPSC318 Lecture 8 Vuong Spring 04 UBC34
Decoding Example (7/7)
C code: Mapping: $v0: product
$a0: multiplicand$a1: multiplier
product = 0;while (multiplier > 0) {product += multiplicand; multiplier - = 1; }
CPSC318 Lecture 8 Vuong Spring 04 UBC35
Outline
Branch instruction encoding
Jump instructions
Disassembly
Pseudoinstructions and “True” Assembly Language (TAL) vs. “MIPS” Assembly Language (MAL)
CPSC318 Lecture 8 Vuong Spring 04 UBC36
Review from Last Lecture: luiSo how does lui help us?
Example:
addi $t0,$t0, 0xABABCDCD
becomes:
lui $at, 0xABABori $at, $at,
0xCDCD add $t0,$t0,$at
Now each I-format instruction has only a 16-bit immediate.
Wouldn’t it be nice if the assembler would do this for us automatically?
If number too big, then just automatically replace addi with lui, ori, add
CPSC318 Lecture 8 Vuong Spring 04 UBC37
True Assembly Language
Pseudoinstruction: A MIPS instruction that doesn’t turn directly into a machine language instruction.
What happens with pseudoinstructions?They’re broken up by the assembler into several
“real” MIPS instructions.But what is a “real” MIPS instruction? Answer in a
few slides
First some examples
CPSC318 Lecture 8 Vuong Spring 04 UBC38
Example Pseudoinstructions
Register Movemove reg2, reg1Expands to:
add reg2, $zero, reg1
Load Immediateli reg, valueIf value fits in 16 bits:
addi reg, $zero, valueelse:
lui reg, upper 16 bits of valueori reg, $zero, lower 16 bits
CPSC318 Lecture 8 Vuong Spring 04 UBC39
True Assembly Language
Problem: When breaking up a pseudoinstruction, the
assembler may need to use an extra register. If it uses any regular register, it’ll overwrite
whatever the program has put into it.
Solution: Reserve a register ($1, called $at for “assembler
temporary”) that the assembler will use when breaking up pseudo-instructions.
Since the assembler may use this at any time, it’s not safe to code with it.
CPSC318 Lecture 8 Vuong Spring 04 UBC40
Example Pseudoinstructions
Rotate Right Instructionror reg, valueExpands to:
srl $at, reg, valuesll reg, reg, 32-valueor reg, reg, $at
0
0
No operation instructionnopExpands to instruction = 0ten,
sll $0, $0, 0
CPSC318 Lecture 8 Vuong Spring 04 UBC41
Example Pseudoinstructions
Wrong operation for operand addu reg, reg, value # should be addiu
If value fits in 16 bits:
addiu reg,reg,value
else:
lui $at,upper 16 bits of value
ori $at,$zero,lower 16 bitsaddu reg,reg,$at
CPSC318 Lecture 8 Vuong Spring 04 UBC42
True Assembly LanguageMAL (MIPS Assembly Language): the set of
instructions that a programmer may use to code in MIPS; this includes pseudoinstructions
TAL (True Assembly Language): the set of instructions that can actually get translated into a single machine language instruction (32-bit binary string)
A program must be converted from MAL into TAL before it can be translated into 1s and 0s.
CPSC318 Lecture 8 Vuong Spring 04 UBC43
Questions on Pseudoinstructions
How does MIPS recognize
pseudoinstructions?
CPSC318 Lecture 8 Vuong Spring 04 UBC44
Summary
Machine Language Instruction: 32 bits representing a single instruction
opcode rs rt immediateopcode rs rt rd functshamtR
IJ target addressopcode
Branches use PC-relative addressing, Jumps use absolute addressing.
Disassembly is simple and starts by decoding opcode field.
Assembler expands real instruction set (TAL) with pseudoinstructions (=>MAL)
CPSC318 Lecture 8 Vuong Spring 04 UBC45
MIPS R3000 ISA (Summary)Instruction Categories
Load/Store
Computational Jump and Branch Floating Point
coprocessor
Memory Management Special
R0 - R31
PCHI
LO
OP
OP
OP
rs rt rd sa funct
rs rt immediate
jump target
3 Instruction Formats: all 32 bits wide
Registers
CPSC318 Lecture 8 Vuong Spring 04 UBC46
Bonus slides
The following slides are more practice on the differences between a pointer and a value, and showing how to use pointers
The claim is that most 318 students don’t understand these ideas
which motivates your instructors to prove them wrong sure
might be interesting to see if we are successful by testing, so be forewarned
CPSC318 Lecture 8 Vuong Spring 04 UBC47
Assembly Code to Implement Pointersdereferencing data transfer in asm.
... = ... *p ...; load
(get value from location pointed to by p)load word (lw) if int pointer, load byte unsigned (lbu) if char pointer
*p = ...; store
(put value into location pointed to by p)
CPSC318 Lecture 8 Vuong Spring 04 UBC48
Assembly Code to Implement Pointersc is int, has value 100, in memory at address 0x10000000, p in $a0, x in $s0 p = &c; /* p gets 0x10000000 */
x = *p; /* x gets 100 */
*p = 200; /* c gets 200 */
# p = &c; /* p gets 0x10000000 */ lui $a0,0x1000 # p = 0x10000000
# x = *p; /* x gets 100 */ lw $s0, 0($a0) # dereferencing p
# *p = 200; /* c gets 200 */ addi $t0,$0,200 sw $t0, 0($a0) # dereferencing p
CPSC318 Lecture 8 Vuong Spring 04 UBC49
Pointers to structures
struct node {struct node *next;int value;
};
If p is a pointer to a node, declared
with struct node *p, then:
(*p).value or p->value for “value” field,
(*p).next or p->next for pointer to next node
value
value0
value
value
C Example - linked list:
CPSC318 Lecture 8 Vuong Spring 04 UBC50
Linked-list in C
main (void) { struct node *head, *temp, *ptr; int sum;
/* create the nodes*/ head = (struct node *)
malloc(sizeof(struct node)); head->value = 23; head->next = 0;
temp = (struct node *) malloc(sizeof(struct
node)); temp->next = head; temp->value = 42;
head = temp;
/* add up the values */ ptr = head; sum = 0; while (ptr != 0) { sum += ptr->value; ptr = ptr->next; }}
CPSC318 Lecture 8 Vuong Spring 04 UBC51
Linked-list in MIPS Assember (1/2)# head:s0, temp:s1, ptr:s2, sum:s3
# create the nodesli $a0,8 # sizeof(node)jal malloc # the callmove $s0,$v0 # head gets resultli $t0,23sw $t0,4($s0) # head->value = 23sw $zero,0($s0)# head->next = NULL
li $a0,8jal mallocmove $s1,$v0 # temp = mallocsw $s0,0($s1) # temp->next = headli $t0,42sw $t0,4($s1) # temp->value = 42
move $s0,$s1 # head = temp
CPSC318 Lecture 8 Vuong Spring 04 UBC52
Linked-list in MIPS Assember (2/2)
# head:s0, temp:s1, ptr:s2, sum:s3
# add up the values move $s2,$s0 # ptr = head move $s3,$zero # sum = 0
loop: beq $s2,$zero,exit # exit if done lw $t0,4($s2) # get value addu $s3,$s3,$t0 # compute new sum lw $s3,0($s2) # ptr = ptr->next j loop # repeat
exit: done
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