Column-Matching Based Mixed‑Mode BIST Technique

Column-Matching Based Column-Matching Based Mixed‑Mode BIST TechniqueMixed‑Mode BIST Technique

Petr FiPetr FišeršerCzech Technical UniversityCzech Technical University

Karlovo nám. 13, 121 35 Prague 2Karlovo nám. 13, 121 35 Prague 2e-mail: fiserp@fel.cvut.cze-mail: fiserp@fel.cvut.cz

OutlineOutlineThe aims of the DissertationThe aims of the Dissertation Introduction to BISTIntroduction to BISTProposed BIST design methodProposed BIST design methodBOOMBOOMExperimental resultsExperimental resultsConclusions & future workConclusions & future work

Ph.D. ThesisPh.D. Thesis

The main aim:The main aim:To develop a new BIST design method, as a To develop a new BIST design method, as a better alternative to other state-of-the-art better alternative to other state-of-the-art techniques, like bit-flipping, bit-fixing, etc.techniques, like bit-flipping, bit-fixing, etc.

Better alternative =Better alternative = Less area overheadLess area overhead More scalabilityMore scalability

Introduction to BISTIntroduction to BIST

Built-in Self-TestBuilt-in Self-Test Enables the device to test itselfEnables the device to test itself

Why (to) BIST?Why (to) BIST? With increasing integration density, the amount of With increasing integration density, the amount of manufacture faults is increasingmanufacture faults is increasing Thus, we have to test the chipThus, we have to test the chip With increasing complexity of the design, it becomes With increasing complexity of the design, it becomes impossible to test the chip externallyimpossible to test the chip externally Thus, we HAVE TO use BISTThus, we HAVE TO use BIST

Rule of TensRule of Tens

BIST Equipment StructureBIST Equipment Structure

[E.C. Stroud]

Test Vectors

[E.C. Stroud]

Responses

[E.C. Stroud]

Pass/Fail

The objective: the TPG designThe objective: the TPG design

[E.C. Stroud]

Two General Approaches to BISTTwo General Approaches to BIST

Test-per-scanTest-per-scanConnect the CUT flip-flops into a scan chainConnect the CUT flip-flops into a scan chainTest the circuit seriallyTest the circuit serially

Test-per-clockTest-per-clockTests the circuit in parallelTests the circuit in parallel

Scalability ProblemsScalability Problems

Aspects involved:Aspects involved:BISTE design timeBISTE design timeBISTE area overheadBISTE area overheadDuration of the BIST (number of clock cycles Duration of the BIST (number of clock cycles needed to test the circuit)needed to test the circuit)Fault coverageFault coverage

These cannot be satisfied at one time

What Do Designers Want?What Do Designers Want?

Design the BIST equipment as fast as possible, regardless the area overhead and the fault coverage (no time to wait) (no time to wait)Design the BIST equipment to be as small as possible, regardless the time it takes (low (low power)power)High fault coverage is the most important aspect, the area overhead is next. The design time is not that important (common practice)(common practice)

Naive MethodsNaive MethodsExhaustive TestingExhaustive Testing

Generates all the 2n patterns 100% fault coverage ensured Extremely slow – impossible to use in practice

Pseudo-Random TestingPseudo-Random Testing Apply several pseudo-random patterns to the CUT Fast 100% fault coverage is not achieved

ROM-based BISTROM-based BIST Test patterns are stored in ROM Fast, 100% fault coverage Big area overhead

State-of-the-art MethodsState-of-the-art Methods

ReseedingReseedingThe pseudo-random test patterns are generated by

LFSRMore LFSR seeds are applied

Weighted Pattern BISTWeighted Pattern BISTChange the probability of occurrence of 1s and 0s in

the PR sequence

Bit-Fixing, Bit-Flipping, Row-matchingBit-Fixing, Bit-Flipping, Row-matchingModify the PR patterns by additional logic

Proposed Mixed-Mode BISTProposed Mixed-Mode BIST

Combination of pseudo-random and Combination of pseudo-random and deterministic BISTdeterministic BIST

Decoder

Switch

Novel approach: the two phases are separated

Pseudo-random patterns are applied first

Then deterministic patterns are applied

Decoder

Switch

PR patterns

Decoder

Switch

PR patterns

Decoder

Switch

Det. patterns

Column-MatchingColumn-Matching

Newly proposed algorithm to synthesize the Newly proposed algorithm to synthesize the DecoderDecoder logic logic

Deterministic BIST:Deterministic BIST:LFSR produces pseudo-random code words(C-matrix)(C-matrix)These are then transformed into deterministic tests computed by ATPG(T-matrix)(T-matrix)

Basic PrincipleBasic PrincipleTry to reorder test patterns, so that most of the Decoder outputs will be implemented as wires – a MatchThis will be accomplished when two particular columns of the LFSR and test matrices will be equalCombinational logic – the order is insignificantUnmatched outputs have to by synthesized by a Boolean minimizer => BOOM

ExampleExample1 0 0 0 10 0 1 1 00 0 1 0 11 0 0 0 01 1 0 0 1

0 1 0 0 11 0 0 1 00 1 1 1 11 1 1 0 01 1 0 0 1

Output Decoder PLA

x - x y - y40 0 4

10001001101011100101111111000010011110111100110010

0100110010011111110011001

1000100110001011000011001

0100110010011111110011001

C-Matrix

T-Matrix Pruned C-Matrix

PRPG Patterns

Test Patterns Output Decoder PLA

y0 = x4’ + x1y1 = x3’y2 = x2 x3’ + x2’ x4’y3 = x0’y4 = x4

Mixed-Mode CMMixed-Mode CM

1. Simulate first n LFSR patterns2. Determine undetected faults3. Compute a test for them (ATPG)4. Design a decoder generating vectors for

this test and following LFSR patterns

10100010100010110110010111000111100011100011110111

Pseudo-randomsequence }Simulate Non-covered

faultsATPG Test

Vectors

1X0001010X110110001X

101001101101011 0000110000

(non-det)Deterministicsequence

x-x0 4 y-y0 4

10100010100010110110010111010011011010110000110000

Final test sequence

ColumnMatching

x0 x1 x2 x3 x4

y0 y1 y2 y3 y4

Deterministicmode

y = x0 0

y = xy = xy = xy = x +x

4 0 1+

Decoder

Switch

Output Decoder DesignOutput Decoder Design

Recall:Recall:“Unmatched outputs have to by synthesized by

a Boolean minimizer => BOOM”

Why BOOM?Why BOOM?Output decoder = multiple-output function having many inputs and outputs Many = thousandsAvailable tools couldn’t handle such functions

BOOMBOOMHeuristic two-level multi-output Boolean minimizerVery fast, low memory demandsEfficient especially for functions having a large number of both input and output variables (up to thousands) Advantageous for weakly specified functions (only few terms defined)Novel approach to implicant generation (see CD-Search)

BOOMBOOM

Main Phases:

CD-SearchCD-SearchImplicant ExpansionImplicant ExpansionImplicant ReductionImplicant ReductionCP SolutionCP SolutionOutput reductionOutput reduction

CD-SearchCD-Search

Most innovative partMost innovative partImplicants are generated top-down:Implicants are generated top-down:by reducing the universal hypercubeby reducing the universal hypercubeWe add literals to a term, until it becomes an We add literals to a term, until it becomes an implicantimplicantBased on a frequency of occurrence inBased on a frequency of occurrence inon-seton-set

BOOM - IEBOOM - IE

Implicant Expansion

The implicants from CD-search are The implicants from CD-search are expanded into PIsexpanded into PIs

BOOM - IRBOOM - IR

Implicant Reduction

Reduces PIs into group implicantsReduces PIs into group implicants

BOOM - CPBOOM - CP

Covering problem solution

Selects an irredundant set of Selects an irredundant set of implicants implicants covering the on-setcovering the on-set

Greedy heuristic is usedGreedy heuristic is used

Iterative minimizationIterative minimization

The result quality is improved by repeating the minimization and collecting implicants

Several speed-up techniques used (buffers)

BOOM ExperimentsBOOM Experiments

MCNC benchmarks, comparison with ESPRESSO

139 benchmarks solved67 (48.2%) solved by BOOM in a shorter time for 52 (37.4%) BOOM gave the same result30 (57.7%) of these equal results were reached faster

BOOM ExperimentsBOOM Experiments

Very large problems. Espresso unusable

Just two examples:200 inputs, 200 defined terms: in 0.06 s1000 inputs, 1000 defined terms: in 4 s

And the Most Important And the Most Important ExperimentsExperiments

Output decoder design

37 output decoders37 output decodersfor 37 (100%) BOOM gave (sometimes much) better result27 (73%) solved in (a sometimes much) shorter time5 couldn’t be solved by Espresso at all

And the Most Important And the Most Important ExperimentsExperiments

Output decoder design (some of them)BOOM ESPRESSO

Bench i/o/p GEs Time [s] GEs Time [s]

d_c2670 (3) 233/36/104 159.5 740.18 344.5 24 710.07

d_c7552 (1) 207/48/81 196.5 807.84 373.0 27 574.93

d_c7552 (2) 207/72/207 389.5 23 933.46 - > 24 h

d_s9234 (1) 247/77/216 655.0 18835.6 - > 24 h

d_s9234 (2) 247/38/99 186.5 266.78 252.5 17 298.0

d_s13207.1 (2) 700/58/197 293.5 1550.25 316.5 190 038

d_ s15850.1 (1) 611/96/313 197.5 3416.4 - > 24 h

d_ s15850.1 (2) 611/48/180 78.5 516.3 120.0 37 818.65

d_s38417 1664/1454/520 759.0 1923.0 - > 24 h

d_s38584.1 (1) 1664/464/307 158.0 321.9 - > 24 h

d_s38584.1 (2) 1664/464/45 11.0 46.6 31.0 20 361.71

Scalability Once MoreScalability Once More

Four important BIST aspects:Four important BIST aspects:

BISTE design timeBISTE design timeFault coverageFault coverageBISTE area overheadBISTE area overheadBIST run lengthBIST run length

Cannot be satisfied at one time!

Every designer wants something else=> need for Scalability

Four important BIST aspects:Four important BIST aspects:

BISTE design timeBISTE design timeFault coverage – given by ATPGBISTE area overheadBISTE area overheadBIST run lengthBIST run length

Four important BIST aspectsFour important BIST aspectsWe can freely adjust the lengths of the phases

Longer PR phase Longer Det. phase

BIST design time decreased increased

Area overhead decreased decreased

BIST run length increased increased

CM Experimental ResultsCM Experimental ResultsComparison with state-of-the-art methods. Equal Comparison with state-of-the-art methods. Equal

test lengths, the area overhead is comparedtest lengths, the area overhead is compared

Compared with:Compared with:Bit-Fixing[N.A. Touba, E.J. McCluskey: Bit-Fixing in Pseudorandom Sequences for Scan BIST, IEEE Transactions on CAD, Vol. 20, No. 4, April 2001, pp. 545-555]Weighted-pattern BIST[S. Wang: Low Hardware Overhead Scan Based 3-Weight Weighted Random BIST. Proc. 2001 IEEE International Test Conference]Row Matching[M. Chatterjee, D.K. Pradhan: A BIST Pattern Generator Design for Near-Perfect Fault Coverage, IEEE Transactions on Computers, vol. 52, no. 12, December 2003, pp. 1543-1558]

CM always better

CM better in 71%

CM better in 60%

CM Experimental ResultsCM Experimental Results

BenchBench PRPR TLTL Time [s]Time [s] OverheadOverhead

c2670 4.5 M 5 K 437 15 %c7552 > 100 M 10 K 887 16 %s9234.1 10 M 200 K 3500 5 %s13207.1 100 K 50 K 13 0.6 %s15850.1 > 10 M 100 K 1200 5 %s38417 > 10 M 100 K 4600 14 %s35841.1 > 1 G 100 K 34 1 %b12 5 M 10 K 1080 7 %

b15 > 100 M 1 M 4800 17 %

Hard-to-test (and “big”) benchmarksHard-to-test (and “big”) benchmarks

Conclusions & ContributionsConclusions & ContributionsThe Column-Matching principle proposedInfluence of the lengths of the phases is studiedVery scalable, many design parameters freely adjustableThe results obtained by CM are mostly better (wrt. the area overhead) than those obtained by state-of-the-art methodsThe method should serve as a basic guideline how to design more complex BIST designs, i.e., the multiple‑scan chain based BIST, the STUMPS architecture, etc.It can be very advantageously used to test SoCs, since the LFSR may be reused for more cores.

Further WorkFurther Work

Use of different PRPGs instead of a LFSR (cellular automata)Scaling the PRPG sizeCombination with other methods (reseeding, weighted pattern testing)Decomposition of the CUTMore intense incorporation of BOOM into CM

Use of different PRPGs instead of a LFSR (cellular automata)Scaling the PRPG sizeCombination with other methods (reseeding, weighted pattern testing))Decomposition of the CUTMore intense incorporation of BOOM into CM

BOOM ConclusionsBOOM Conclusions

Novel Boolean minimizer proposedNovel Boolean minimizer proposedDifferent approach to implicant generationDifferent approach to implicant generationFast for functions with many inputs and outputsFast for functions with many inputs and outputsOutperforms Espresso in most casesOutperforms Espresso in most casesEssential for CM Output Decoder synthesisEssential for CM Output Decoder synthesis

FC-Min (good for many outputs)FC-Min (good for many outputs)BOOM-II (combination of BOOM and FC-Min)BOOM-II (combination of BOOM and FC-Min)Decomposition (single-level partitioning)Decomposition (single-level partitioning)Output groupingOutput groupingESOP minimizationESOP minimizationSeveral minor enhancementsSeveral minor enhancementsMultiple-valued minimizationMultiple-valued minimization??????

FC-Min (good for many outputs)BOOM-II (combination of BOOM and FC-Min)Decomposition (single-level partitioning)Output groupingESOP minimizationESOP minimizationSeveral minor enhancementsSeveral minor enhancementsMultiple-valued minimizationMultiple-valued minimization??????

PublicationsPublicationsBOOM

8 international conference publications1 journal publication1 research report4 citations

Extensions of BOOM5 international conference publications

Column-Matching9 international conference publications1 journal publication

Other8 international conference publications

Q & AQ & A

Q: Q: Could you compare overheads of a decoder for transformation of pseudo-random patterns to deterministic patterns and the needed control unit with a BIST technique using RAM or ROM for deterministic patterns?

A: A: In fact, not yet. The ROM-based approach would definitely consume more space. Experiments on real HW are in progress.

Q & AQ & A

Q:Q: What do you think about using column matching algorithms for a deterministic test set with more than one pattern for one fault in the context of complexity (time, memory size)?

A: A: Already done. It helps a lot. For a cost of a design time. See [DDECS’06].

Q & AQ & A

Q:Q: Is it possible to use the developed BIST technique for delay faults?

A: A: Probably yes, after some modification of the CM algorithm. Here we have to keep two successive deterministic patterns together. A topic to think about…

Q & AQ & A

Q:Q: What do you think about using your BIST for concurrent testing of more than one digital block in SoC with different number of deterministic patterns and/or the use of parallel test access mechanisms?

A: A: No problem. The LFSR may be shared among the blocks, the Decoder and MUX for each block have to be synthesized by CM. We are working on it now (and doing even more…).

Bench inps 100% FC TL (PR + Det.) M SWGEs

TotalGEs

BIST Overhead Time [s]

s420 34 165 K 400 + 600 32 21 3.5 24.5 13 % 0.75

5 K + 1 K 34 18 0 18 9 % 5.01

s641 54 200 K 500 + 500 52 21 2 23 9 % 0.47

3 K + 1 K 54 15 0 15 6 % 0.21

s713 54 300 K 500 + 500 52 24 3 27 8 % 0.56

3 K + 1 K 54 18 0 18 5 % 0.32

s838 67 > 100 M 1 K + 1 K 37 81 45 126 32 % 26.20

10 K + 2 K 46 79.5 29 108.5 28 % 51.51

s1196 32 200 K 2 K + 1 K 28 13.5 23.5 37 7 % 1.20

9 K + 1 K 32 6 0 6 1 % 0.04

s9234 247 10 M 50 K + 1 K 208 163.5 156 319.5 8 % 350

200 K + 1 K 225 127.5 66 193.5 5 % 3500

s13207.1 700 100 K 1 K + 1 K 638 456 294 750 13 % 4000

50 K + 1 K 700 36 0 36 < 1 % 13

s15850.1 611 > 10 M 10 K + 1 K 478 397.5 187 584.5 9 % 812

100 K + 2 K 553 306 66.5 372.5 5 % 1244

s38417 1664 > 10 M 10 K + 1 K 1240 1365 1389.5 1389.5 17 % 24 K

100 K + 1 K 1000 1239 142 2284 14 % 4660

s38584.1 1464 > 1 G 10 K + 1 K 1435 379.5 57.5 437 3 % 650

100 K + 1 K 1464 165 0 165 1 % 34

b07 50 200 K 1 K + 1 K 45 33 8.5 42.5 11 % 4

10 K + 1 K 50 24 0 24 6 % 0.5

b12 126 5 M 1 K + 1 K 117 37.5 45 82.5 9 % 40

10 K + 1 K 118 33 34 67 7 % 1080

b14 277 > 100 M 1 M / 2 K 84 318 8017 8335 141 % 170 K

100 M / 1 K 90 328.5 2663.5 3319.5 56 % 100 K

b15 485 > 100 M 100 K / 1 K 241 558 4709 5267 67 % 50 K

1 M / 1 K 378 373.5 667 1355.5 17 % 4800

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