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Philipossian
1NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Tutorial onChemical Mechanical Polishing (CMP)
Ara Philipossian
Intel Corporation
1999 Arizona Board of Regents for The University of Arizona
Philipossian
2NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Outline of the Tutorial
• Section A: Overview– Generalized schematics of CMP and Post-CMP Clean– Current CMP environment– Evolution of CMP– The CMP Module– The CMP Infrastructure
• Section B: Polishing equipment trends• Section C: Polishing process issues• Section D: Consumables (pads & slurries)
– Quality issues– Factors affecting productivity– Critical pad and slurry parameters
Philipossian
3NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Outline of the Tutorial
• Section E: Industry - University Gaps• Section F: Environmental Health and Safety (EHS)
considerations• Section G: Slurry fluid dynamics• Section H: Slurry re-use• Section I: Post-CMP cleaning
Philipossian
4NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Section A: Overview
Philipossian
5NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Schematic Diagram ofChemical Mechanical Polishing Process
Carrier
RetainingRing
Slurry
Polish Platen
Pad
Pad Conditioner
Downforce
Philipossian
6NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Schematic Diagram ofPost-CMP Scrubbing
wafer
PVA brush
Cleaning Fluid
Philipossian
7NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
CMP Environment• CMP has become the widely accepted planarization method of choice
for < 0.5 micron technologies• The overall CMP market is growing at a rate of ~ 50% per year• The current momentum in process integration and scaling far exceeds
the fundamental understanding of complex interactions among:– Equipment– Consumables (i.e. slurry, pad, carrier film)– Process parameters– IC type and density
• Processes and consumables are formulated to provide optimum performance for a given equipment and IC product set
• For a 4 metal layer process with STI, ILD and W CMP steps, approximately 20 polishers are needed ( 60% utilization, 20 wafers per hour, 5000 wafer starts per week factory)
Philipossian
8NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
CMP Environment
• Protection of intellectual property hinders shared learning among IC, equipment and consumables manufacturers, but also provides a technological advantage:
– Internally developed equipment, precision parts and sub-systems
• Morimoto & Patterson, US Patent No. 5,104,828 (1992)• Breivogel, Blanchard & Prince, US Patent No. 5,216,843 (1993)• Breivogel, Louke, Oliver, Yau & Barns, US Patent No. 5,554,064 (1996)
– Internal slurry formulations licensed to suppliers for exclusive use– Customized pads– 3rd party modifications of off-the-shelf consumables and equipment
Philipossian
9NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Evolution of CMP
0
2
4
6
8
10
12
1994 (0.25to 0.50micron)
1997 (0.25to 0.35micron)
Num
ber o
f Pol
ish
Ste
ps
Tungsten
Oxide
Philipossian
10NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Evolution of CMP
Generation Application CMPAttributes
Post-CMP CleanAttributes
First
(0.8 to 0.5um)
ILD Single platen, single head,one step polish
Wet station,scrubber, DI water
Second
(0.5 to 0.25um)
ILD, Doped ILD,STI & W
Multiple platens, multipleheads, buffing, end-point
detection & on-boardmetrology
Scrubber, DI water& NH4OH
Third
(0.25 to 0.18um)
ILD, Doped ILD,STI, W, Low KILD, Cu, Al &
polysilicon
Integrated Dry-In Dry-Out,multiple platens, multiple
heads, non-rotary (i.e. orbitaland linear), multiple step
polish, end point detectionand on-board metrology
Integrated Dry-InDry-Out, scrubbing,DI water, NH4OH,HF, novel cleaning
methods andchemistries
Philipossian
11NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
W S
lurr
y 2 3
ILD
Slu
rry 5 6
ILD
Top
Pad
8
Nor
mal
ized
Cos
t per
Waf
er
a - Negotiate Priceb - Insert competitionc - Reduce disposal volumed - reclaim and re-use
a - Negotiate Priceb - Insert competitionc - Increase pad life via better QCd - Increase pad life via better chemistry
Total Cost Chemical Expenditure per fully Processed Product Wafer
(Disposal and Treatments Costs are Included)
Philipossian
12NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
The CMP Module
Polish
In-Situ Measure
Measure & Inspect
Measure & Inspect
Re-work
Product and Test Wafers
Water
Slurry
Pad
Energy
Clean
Product and Test Wafers
Liquid Waste
Energy
Filter
Solid Waste
Carrier Film
Philipossian
13NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
• Polishing: Rotary (single or multiple heads and platens)– Orbital (single or multiple heads and platens)– Linear (multiple heads)
• Cleaning: Mechanical scrubbing (with & without chemistry or megasonics) Wet cleaning (with and without megasonics)
• Measurement and inspection: Removal Rate– Thickness uniformity (wafer-to-wafer, within-die, die-to-die)– Defect density– Dishing– Erosion– Plug recess Planarity– Surface Roughness
The CMP Infrastructure
Philipossian
14NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
• In-situ Measurement:
– End-point detection• Consumables:
Pad (polyurethane, impregnated felt, fixed abrasive) Slurry (silica, alumina or ceria abrasives, organic and inorganic
additives)– Filter (point-of-use or post-slurry-blending)– Conditioning (diamonds)
• Slurry delivery• Water delivery• Waste treatment:
– Off-site disposal– Recycling Re-use
The CMP Infrastructure
Philipossian
15NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Section B: Polishing Equipment Trends
Philipossian, Morimoto and Cadien, CMP-MIC,Santa Clara, CA (1996)
Philipossian
16NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Equipment Environment
• In high-volume manufacturing, the balance between high throughput, size and complexity needs to be maintained
Polisher Number ofPolish Heads
Number ofPolish Plattens
A 1 1B 2 1C 3 3D 4 4E 5 1F 6 1
Philipossian
17NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Equipment Environment• Development of automated dry-in-dry-out systems that:
• Improve throughput• Reduce footprint• Reduce total cost• Reduce ergonomic issues• Reduce number of people
Robot
CleanI/O
Polish 1 Polish 2
Polish
I/O
Clean
• Ability to polish 300-mm wafers• In-situ metrology for device wafers with closed-loop control
Philipossian
18NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Section C: Polishing Process Issues
Philipossian, Morimoto and Cadien, CMP-MIC,Santa Clara, CA (1996)
Philipossian
19NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Process Issues• Within-Wafer Non-Uniformity (WIWNU):
– Wafer flatness– Carrier film, pad & slurry type (discussed earlier)– Carrier design– Pad conditioning method– Platen & carrier speeds– Retaining ring design (i.e. extent of pressure discontinuity between wafer
edge and retaining ring)– Slurry injection scheme
• Defect density:– Pad & slurry type– Use of secondary platen– Post-CMP cleaning method
• Removal rate:– Carrier film, pad & slurry type (discussed earlier)– Downforce– Platen & carrier speeds
Philipossian
20NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Process Issues• Planarity:
– Pad type– Circuit density & structure size– Extent of ILD removed– Downforce, platen speed & carrier speeds
– Step Height Ratio (SHR) = Post Step Height / Pre Step Height– The goal is to minimize SHR and maximize PD thereby minimizing Within-Die Non-
Uniformity (WIDNU)Planarization Distance (PD)
Post
PrePolish
Philipossian
21NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Effect of Structure Size & Densityon Post Step Height
0
2000
4000
6000
8000
0 4 8 12 16
Structure Size (mm)
Post
Ste
p H
eigh
t (A)
0
500
1000
1500
2000
0 20 40 60 80 100
Structure Density (%)Po
st S
tep
Hei
ght (
A)
• SHR is greater on metal pads compared to isolated narrow lines• Areas with lower circuit density polish faster than areas with dense underlying topography• Each circuit design will have a different WIDNU due to variations in size and density of interconnects
Philipossian
22NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Effect of Downforce on Removal Rate & Planarity
500
1000
1500
2000
2500
0 2 4 6 8 10
Downforce (psi)
Rem
oval
Rat
e (A
/min
)
0
0.2
0.4
0.6
0.8
1
0 2 4 6 8 10
Downforce (psi)SH
R
• Increase in downforce (wafer pressure applied to the polishing pad) results in a linear increase in removal rate (i.e. Preston’s Equation)• Increase in downforce degrades planarity due to pad deformation and subsequent increase in local pressure at the ‘valley’ regions (i.e. Hook’s Law)
Philipossian
23NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Effect of Platen Speed on Removal Rate & Planarity
1000
1500
2000
2500
3000
0 20 40 60 80 100
Platen Speed (RPM)
Rem
oval
Rat
e (A
/min
)
0
0.2
0.4
0.6
0.8
1
0 20 40 60 80 100
Platen Speed (RPM)SH
R
• Increase in platen speed increases removal rate linearly (i.e. Preston’s Equation)• Increase in platen speed improves planarity• At higher speeds the pad contacts mainly the ‘hill’ regions since it does not have sufficient time to conform to the ‘valley’ regions
Philipossian
24NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Effect of Carrier Speed onWafer Center & Edge Removal Rates
1000
1500
2000
2500
3000
0 20 40 60 80 100
Carrier Speed (RPM)
Rem
oval
Rat
e (A
/min
)
• Platen speed is maintained at 70 RPM• Center-to-edge removal rate difference increases with increasing carrier speed• Carrier diameter << platen diameter & at low carrier speeds, the linear velocity vector created by the carrier is much smaller than that created by the platen• As carrier speeds approach & exceed platen speed, the linear velocity vector created by the carrier becomes significant
Edge
Center
Philipossian
25NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Effect of Pad Hardness onPost Step Height and Planarization Distance
0
2000
4000
6000
8000
0 0.5 1 1.5 2 2.5 3 3.5 4
Horizontal Distance (mm)
Post
Ste
p H
eigh
t (A
)
• Harder pads deform less under pressure thus leading to:- Lower SHR, higher PD, and improved WIDNU (i.e in mm range)- Poorer WIWNU (i.e. in cm range)
• Harder pads also result in higher removal rates and higher defect densities
Soft Pad
Hard Pad
Philipossian
26NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Effect of Pad Compressibilityon Electrical Integrity of ILDKaufman, Proceedings of Spring MRS, CA (1995)
6
7
8
9
10
11E-
Fiel
d at
50%
Fai
ls(M
V/cm
)
As DepositedGlass Bead / PolymerPolymerStacked PolymerFelt
Philipossian
27NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Section D: CMP Consumables
Philipossian, Sanaulla, and Moinpour, Semicon West Technical Session on CMP, CA (1998)
Philipossian
28NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
CMP Slurries and PadsAreas of Concern
Availability
Design
EHS
Legal
Supplier
Quality & Reliability
Manufacturability
Total Cost
Philipossian
29NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Quality IssuesIntel Corporation
All Chemicals
Procedural34%
Packaging24%
Intrinsic Material
27%
Delivery & Warehousing
15%
Philipossian
30NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Quality IssuesIntel Corporation
CMP Slurries
Procedural19%
Packaging19%
Intrinsic Material
43%
Delivery & Warehousing
19%
70% Abrasive Issues20% Foreign Matter10% Other
Philipossian
31NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Quality Issues Intel Corporation
CMP Pads
Procedural15%
Intrinsic Material
75%
Delivery & Warehousing
10%
40% Texture30% Foreign Matter20% Adhesive10% Other
Philipossian
32NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Impact of Quality IssuesThe Quality Indicator (QI)
QI = 100 - (2) [(a) + (2) (b) + (4) (c) + (8) (d) + (16) (e)]
SCAR: Supplier Corrective Action RequestNote: The Quality Indicator is measured on a quarterly basis for each supplier
e = No. of factory interrupts (i.e. issues resulting in tool or factory downtime, or product loss)
d = No. of near misses (i.e. issues requiring extra Intel resources to keep the factory running)
c = No. of repeat SCARs
b = No. of SCARs (i.e. issues caused by gross supplier negligence)
a = No. of issues (i.e. all issues regardless of impact to Intel)
Philipossian
33NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Supplier ComparisonCMP Suppliers vs. Photoresist and Wet Chemical Suppliers
(Data Collected Since 1Q96)
0
20
40
60
80
100
Pad & SlurrySuppliers
PhotoresistSuppliers
Wet ChemicalSuppliers
Aver
age
Qua
lity
Indi
cato
r
Challenge
Philipossian
34NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Equipment - Availability - Reliability
- Integrated Run Rate
Productivity
Factors Influencing Productivity
Labor - EHS
- Ergonomics - Automation
Process Stability & Manufacturability- RR- WIWNU, WTWNU, WIDNU
- Defects- Planarity- Pad life- Pad & slurry quality
Philipossian
35NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Tool Integration and AutomationIntegrated Run Rate
Robot
R1
CMP#1R2
CMP#2R3
Cleaner
R4
Robot
R1
Wafers Wafers
WafersRobot
R1 R5
CleanerRobot
R1
CMP#3
CMP#1R2
CMP#2
R3
R4
Wafers
Robot Limited
Cleaner Limited
Philipossian
36NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
• Changing pads in high-volume manufacturing poses a serious ergonomic issue:
– Frequency of change– Difficulty of change
• A compromise must be reached between adhesive strength and its effect on the polishing process:
– Hardness– Compressibility– Corrosion resistance– Use of chemicals to remove
adhesive residues• Mechanical pad-pullers are
becoming a requirement in factories
0
10
20
30
40
50
60
0 2000 4000 6000 8000 10000 12000
WSPW
# of
pad
cha
nges
per
wee
k
Polishing Pad LifeFrequency of Changing Pads as a Function of Pad Life
Philipossian
37NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Polishing Pad LifeEffect of Pad Life on Tool Availability
• Availability (%) = 100 - Scheduled Downtime - Unscheduled Downtime• Scheduled Downtime:
– Tool PM, facilities PM, monitors, tool qualification and consumables changeout• Unscheduled Downtime:
– Out-of-control conditions, repairs
80
85
90
95
100 200 300 400 500 600Pad Life
Tool
Ava
ilabi
lity
(%)
Philipossian
38NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
• 5000 WSPW• 5 oxide polish steps• Pad life of 500 (i.e. number of
wafers polished before pad change)
• Pad change duration:– Complexity of process
qualification on fresh pad (i.e. pad break-in)
– Other consumable changes (i.e. wafer carrier & pad conditioner)
– Ergonomics of pad change (i.e. pad size and adhesive strength)
5 Layers
0
20
40
60
80
100
120
0 5 10 15 20 25
# of Polishers
% A
vaila
bilit
y
0.5 hours
1 hour
2 hours
4 hours
6 hours
No. of Polishers vs. Tool AvailabilityEffect of Pad Change Duration
(Pad Life & Scheduled and Unscheduled Downtime are Fixed)
Philipossian
39NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
5 Layers
0
20
40
60
80
100
120
0 5 10 15 20 25
# of Polishers
% A
vaila
bilit
y
1 hour
6 hours
12 hours
No. of Polishers vs. Tool AvailabilityEffect of Un-Scheduled Downtime
(Pad Life, Pad Change Duration and Scheduled Downtime are Fixed)
Philipossian
40NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Oxide Polisher Downtime Pareto Chart
Sch
edul
ed Q
ual
Tool
PM
Rep
air
OO
C
Oth
er
Uns
ched
uled
Qua
l
Faci
litie
s P
M
Nor
mal
ized
Tim
e
C+P
C+P+T
C+P+TC+P
C = ConsumablesP = ProcessT = Tool
Philipossian
41NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Oxide Polisher Downtime Pareto Chart
Sch
edul
ed Q
ual
Tool
PM
Rep
air
OO
C
Oth
er
Uns
ched
uled
Qua
l
Faci
litie
s P
M
Nor
mal
ized
Tim
e
average pad lifeaverage POU filter life
variability in pad and slurry properties (PSD)
average filter lifevariability in slurry properties (PSD)
Philipossian
42NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Effect of pH and Abrasive Content on ILD Removal Rate
Scherber et al., Proceedings of the Symposium on Planarization Technology: CMP, Semicon West (1994)
50
60
70
80
90
100
110
9.5 10.5 11.5pH
Rem
oval
Rat
e
9% 12% 15%
Philipossian
43NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Effect of Trace Metals on ILD Polish Performance
Slurry [Al] [Ca] [Cr] [Fe] [Ni] NormalizedDefect Density
F < 0.2 < 0.2 0.7 1 < 0.2 1
G 99 1.2 3 18 3.2 3 to 11
- All units in ppm- Slurries F & G are identical except for the metal content- Comparable removal rate and uniformity
Philipossian
44NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Effect of Hydrocarbons onILD Polish Performance
Slurry NormalizedHydrocarbon
Content
NormalizedDefectDensity
H 1 1
I 14 3 to 6
- Slurries H & I are identical except for the hydrocarbon content
- Hydrocarbon contained a polar group- Comparable removal rate and uniformity- Majority of defects were ‘scratches’
Philipossian
45NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Abrasive Geometry
Primary Particle
Aggregate
Philipossian
46NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Effect of Abrasive Geometryon ILD Polish Performance
Slurry Appx. PrimaryParticle
Size(nm)
Appx. MeanAggregate
Size(nm)
NormalizedMean
RemovalRate
NormalizedWIWNU
(3-sigma)
A 29 122 86 --B 29 110 100 100C 19 95 82 83D 20 110 79 154E 50 200 94 104
- Fumed silica abrasive- Constant pH and abrasive content- Comparable defect density and planarity
Philipossian
47NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Effect of Abrasive Geometry on ILD Removal Rate
70
80
90
100
110
0.15 0.2 0.25 0.3
PPS / MAS (unitless)
Rem
oval
Rat
e
Philipossian
48NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Section E: Industry - University Gaps
Philipossian
49NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Core Subject Funded UniversitiesPad synthesisPad deformation studies SUNY, Saitama Univ, RPI,
Nagoya Inst of TechBrush synthesisAdhesive developmentAbrasive powder synthesisAbrasive powder and slurry morphology, PSD,geometry and type
Univ of Minnesota, Univ ofCentral Florida
Abrasive powder metrologySlurry and pad fluid mechanics (empirical) Tufts, Georgia Inst of TechSlurry and pad fluid mechanics (modeling) TuftsSlurry consumption reduction TuftsConsumable - tool - process interactions Berkeley, MIT, Tufts, ASUElectrochemistry Univ of NM, Sandia, RPI,
Univ of ArizonaSlurry dispersion and mixingSlurry filtration IMEC
Development of Core Competencies(Industry - University Gaps)
Philipossian
50NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Core Subject Funded UniversitiesReaction kinetics RPI, Sandia, Clarkson,
Univ of NMCMP process development & modeling IMEC, MIT, Tohoku Univ,
Stevens InstituteSlurry, pad and brush shelf-life studiesAdditives to enhance or retard removal rates Clarkson, RPI, Tohoku
UnivAdditives to modulate removal rate selectivity RPI, ClarksonDispersion and colloidal stability Clarkson, Univ of ArizonaAnti-caking agent developmentSlurry reclaim and re-use Univ of ArizonaDissolution, passivation, adhesion and roughening Univ of Florida, ClarksonSurfactants Univ of Arizona, ClarksonPad and slurry interactions SUNYEnhanced Pourbaix diagrams
Development of Core Competencies(Industry - University Gaps)
Philipossian
51NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Section F: EHS Hierarchy and Considerations
Philipossian, Moinpour and Poliak, Proceedings of VMIC, Santa Clara, CA (1998)
Philipossian
52NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
EHS Hierarchy & Issues
• Environmental regulations are growing at an amazing rate:– Federal and local initiatives & regulations– International initiatives
• Recycling regulations are extremely complex and require detailed understanding and follow-through
• Many new materials are not designed with EHS in mind. In many cases, suppliers do not even know the potential EHS impact of these materials
• To find out late in the process that a material has a serious EHS impact can delay technology introduction or increase cost
• Most chemical suppliers have committed to ownership from cradle-to-grave, but follow-through is poor
Replace > Reduce > Re-use > Recycle > Abate
Philipossian
53NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
RA
IARHAA
CERFA EPAOPA
GCRAPPACAAA
SPAGCPAWQAEPCRA
SARAHSWANWPAAPA
CERCLAUORASWDAA
EAWANCPACWASWDARCRATSCAHMTA
SDWACZMAODA
EQIA CAANPAA NEPAAQA
NESA
WAWA
FIFRA
MVAPCA
WLFMLA
FCAPHSA
TGA RHA
FWCAWRA
FWPCA
1890 1900 1910 1920 1930 1940 1950 1960 1970 1980 1990 2000020
4060
8010
012
014
016
0
Year
Growth of US Environmental Legislation(Cumulative No. of Environmental Laws)
Technology & Environment,Washington DC, National AcademyPress, p. 101 (1989)
Philipossian
54NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
EHS in CMP(Level - I Considerations)
energy inputs
chemical inputs
EHSergonomics
chemical outputs
energy outputs
Philipossian
55NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
energy inputs
chemical inputs
ergonomics
chemical outputs
polish tool
post-polish tool
film type
IC type
slurry type
process recipe
pad type
post-polish consumable
IC density
wafer size
publicly owned treatment works
in-fab discharge treatment methodfab location
wafer starts per week
energy outputs
chemical blending & delivery system
UPW systemEHS
EHS in CMP(Level - II Considerations)
Philipossian
56NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
energy inputs
chemical inputs
ergonomics
chemical outputs
polish toolpost-polish tool
film typeIC type
slurry type
process recipe
pad type
post-polish consumable
IC density
wafer size
publicly owned treatment worksin-fab discharge treatment methodfab locationwafer starts per week
energy outputs
chemical blending & delivery systemUPW system
pHabrasive typeabrasive size
abrasive shapeabr. morphology
solids contentoxidizer typeadditive type
buffer typebase typeacid type
zeta potentialionic strength
viscositycolor
shelf lifepot life
dispersability
EHS in CMP(Level - III Considerations)
Philipossian
57NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
energy inputs
chemical inputs
ergonomics
chemical outputs
polish toolpost-polish tool
film typeIC type
slurry type
process recipe
pad type
post-polish consumable
IC density
wafer size
publicly owned treatment worksin-fab discharge treatment methodfab locationwafer starts per week
energy outputs
chemical blending & delivery systemUPW system
sizematerial
stackthickness
texturemorphology
hardnessspecific gravitycompressibility
hole patterngroove pattern
adhesive strengthlife
shelf life
EHS in CMP(Level - III Considerations)
Philipossian
58NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
energy inputs
chemical inputs
ergonomics
chemical outputspolish toolpost-polish tool
film typeIC type
slurry type
process recipe
pad type
post-polish consumable
IC density
wafer size
publicly owned treatment worksin-fab discharge treatment methodfab locationwafer starts per week
energy outputs
chemical blending & delivery systemUPW system
automationfootprint
conditionerendpoint detectionwater inj. schemeslurry inj. scheme
effluent segregationPOU filtration
flow dynamicsre-use compatibility
carrier designplaten design
ring designnumber of platens
rotation schemevent design
parts clean req.PPE req.
ease of maint.run rate
EHS in CMP(Level - III Considerations)
Philipossian
59NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
energy inputs
chemical inputs
ergonomics
chemical outputspolish tool
post-polish tool
film typeIC type
slurry type
process recipe
pad type
post-polish consumable
IC density
wafer size
publicly owned treatment worksin-fab discharge treatment method
fab locationwafer starts per week
energy outputs
chemical blending & delivery systemUPW system
water flow rateslurry flow rate
chemical flow ratedilution
flow overlapautomation
carrier speedplaten speed
down-forceback-pressure
number of platensconditioning recipe
EHS in CMP(Level - III Considerations)
Philipossian
60NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Section G: CMP Fluid Dynamics
Coppeta, Roger, Racz, Kaufman & Philipossian, Pad effects on slurry transport beneath a wafer during polishing,
CMP-MIC, Santa Clara (1998)
Philipossian
61NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Fluid Dynamics• Goal:
– Reduce slurry dispense volume– Increase slurry utilization efficiency– Entrain a uniform layer of new slurry beneath the wafer– Prevent polished material from being re-entrained beneath the wafer
• Key issues which need to be comprehended:– Chemical & mechanical factors which influence polishing– Slurry film thickness between wafer and the pad– Slurry transport mechanism, and factors that influence slurry
transport• Slurry injection scheme• Slurry flow rate• Pad type, conditioning and topography• Platen and carrier speed
Philipossian
62NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Dual-Emission Laser-Induced Fluorescence
Glass Wafer
Polish Platen
Pad
Camera Laser
Slurry with Fluorescence dye Slurry
Philipossian
63NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
http:\\www.tuftl.tufts.edu
Philipossian
64NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Slurry Transport
InterrogationRegion
Wafer
Post
Examining:- Mean slurry age- Residence time- Slurry Gradients
(flat pads)- Drag on wafer- Fluid thickness measurements
Pad
Philipossian
65NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Slurry Flow Rate
Flat Pad
Grooved Pad Manufacturer: RodelSlurry Flow Rate: x cc/minWafer Down Force: 4 psiPlaten Speed: 60 rpmX-Y Groove Depth: 20 mils
Time (sec)
Perc
ent N
ew S
lurr
y
Philipossian
66NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Platen Speed
Manufacturer: FreudenbergSlurry Flow Rate: 35 cc/minWafer Down Force: 4 psiPlaten Speed: x rpmX-Y Groove Depth: 20 mils
Flat Pad
Grooved Pad
Time (sec)
Perc
ent N
ew S
lurr
y
Philipossian
67NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Static Case
Pad deformation: (4 psi, 0 rpm)
Image of a single pad Thickness profile as determined by ratiometric technique
Philipossian
68NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Section H: Slurry Reuse
Kodama, A reclaim use of CMP slurry, 29th Symposium on ULSI Ultra Clean Technology, Tokyo, Japan (1996)
Philipossian
69NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Slurry Re-UseExperimental Setup
Secondary Platen Primary Platen
Slurry Capture Tub
Spent Slurry Reservoir
Pump & Filter
Philipossian
70NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
RR & WIWNU vs. Slurry Reclaim
750
1000
1250
1500
1750
2000
1 2 3 4 5 6No. of Reclaims
Rem
oval
Rat
e (A
/min
)
0
1
2
3
4
5
6
7
8
9
10
1 2 3 4 5 6No. of Reclaims
WIW
NU
(% 1
-sig
ma)
fumed 50 / 200 nmcolloidal 102 / 212 nm
Philipossian
71NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Surface Roughness & pH vs. Slurry Reclaim
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
1 6No. of Reclaims
Ra
(nm
)
1010.110.210.310.410.510.610.710.810.9
1111.111.211.311.411.5
1 6No. of Reclaims
pH
fumed 50 / 200 nm
colloidal 102 / 212 nm
Philipossian
72NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Mean Aggregate Size vs. Slurry Reclaim
180
185
190
195
200
205
210
215
220
1 6No. of Reclaims
Mea
n A
ggre
gate
Siz
e (n
m)
fumed 50 / 200 nmcolloidal 102 / 212 nm
Philipossian
73NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Section I: Post-CMP Cleaning
Moinpour & Burke, Keynote Address, CMP-MIC, Santa Clara (1998)
Jankovsky, 3rd CMP Workshop, Lake Placid, NY (1998)
Busnaina, 3rd CMP Workshop, Lake Placid, NY (1998)
Philipossian
74NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Post-CMP Clean
• Defects & Contamination:– Abrasive particle residues
(i.e. silica, alumina or ceria)– Chemicals on surface (i.e.
surfactants, or slurry additives)
– Alkali metal contaminants (i.e. K or Na)
– Heavy metals (i.e. Fe)– Pad residues– Pad conditioner (i.e.
diamond) residues
• Requirements:– Quick and repeatable– Cause do damage to devices
or films (i.e. change roughness or planarity)
– No residue or redeposition– Low cost of ownership
(COO)• Environment:
– Mechanical scrubbing (with & without chemistry or megasonics)
– Wet cleaning (with and without megasonics)
Philipossian
75NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Post-CMP Clean (Defect Reduction Strategies)
• Step - I … Reduce defects during the CMP process:– Use slurry additives
• Step - II … Reduce defects further by performing an additional buffing process:– Use chemicals on the
secondary platen• Step - III … Reduce defects
even further during the post-CMP cleaning process:– Use chemicals in the post-
CMP cleaning tool
Application Process Chemical
Oxide NH4OH & HFW NH4OH & HF
STI NH4OHpolysilicon APM & HCl
Copper ProprietaryChemicals
Philipossian
76NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Post-CMP Clean(A Sampling of Chemicals or Methods
Cited in the Literature)
0
3
6
9
12
15
18D
I Wat
er
NH
4OH
HF
Citr
ic A
cid
Meg
ason
ics
TMA
H
Surfa
ctan
t
Hot
DI W
ater
KO
H
APM H
Cl
H2O
2
NH
4F Ice
Prop
riete
ry
Philipossian
77NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
• 0.35 um, 200mm technology• Effect of post ILD CMP clean
chemistry on end-of-line yield• Process 1 and Process 2 are
identical polish processes• Process 2 uses a different
Post-CMP Clean chemistry• Improved consumable lifetime• No impact on overall run rate
Post-CMP Clean(Process Improvement)
0
0.2
0.4
0.6
0.8
1
Yield Impact
Cum
ulat
ive
Prob
abili
ty
Philipossian
78NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Cleaning Theory• Particles in liquids:
– Primary cause of adhesion is van der Walls forces (DLVO Theory)
– Secondary cause of adhesion is Electric Double Layer (EDL) forces (however, they are usually repulsive and can help in particle removal)
• Particles in solution become charged• Stern Layer + Diffuse Layer = EDL• Potential at shear plane = Zeta Potential• EDL thickness varies as inverse square root of the ionic strength
(i.e. 4X increase in ionic strength will reduce EDL thickness by 2X)
• EDL and the Zeta Potential are a function of pH
Philipossian
79NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Cleaning Theory
• ELECTRIC DOUBLE LAYER
Philipossian
80NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Cleaning Theory
• DLVO THEORY
Philipossian
81NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Post-CMP Cleaning
Al2O3 Pure
-6
-4
-2
0
2
4
6
2 4 6 8 10 12
pH
Mob
ility
(m2/
V/S
)
Mobility
Philipossian
82NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Brush Cleaning• Advantages:
– Most common cleaning methodology
– Double-side and edge cleaning capability
– High energy scrub capability– The contact mechanism can
help clean wafers with topography
– Simple integration with dry-in-dry-out processing
– Compatible with wet chemistry– Compatible with the recent
advances in ‘smart-brushes’ (zeta-potential engineering)
• Disadvantages:– Contact with wafers may be
harmful– Brush loading with particle
and re-deposition– Low throughput– High COO (chemicals, DI
water, consumables parts)– Static build-up which may
increase particle adhesion forces
– Tough for brushes to contact high aspect ratio topography
– Brush shedding– Brush break-in required
Philipossian
83NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Wet Chemical Cleaning• Advantages:
– More chemically intensive compared to brush cleaning
– Residues and foreign matter can be readily dissolved and removed from the surface
– Ability to manipulate zeta potential to remove particles
– Low COO– High throughput– Controlled cavitation (formation of gas
bubbles by ultrasound) and acoustic streaming (steady flow induced by sound field) can be used to detach and remove particles from the surface
– Formation of acoustic boundary layer
• Disadvantages:– Particle saturation in the
recirculating tank– Difficult to integrate
with dry-in-dry-out processing
– Cleaning process must be tailored to each device layer and material
– Uncontrolled cavitation may cause wafer surface damage
Recommended