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EE141 – Fall 2005Lecture 14
CMOS Design CMOS Design Optimization Optimization ––Logical EffortLogical Effort
EE141 2
Administrative Stuff
PROJECT 1 (Start early!)• You will not be able to finish in 1 week!
LABS• This week: Finish any remaining SW labs• Next week: Project help in labs
HOMEWORKS• Due date for Hw6 = Mon Oct 24 (EE142 Midterm)• No new homework this week
2
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Important Changes
NEW OH• Thursday, 1-3pm• Starting this week
BI-WEEKLY REVIEW• One hour sessions every other Thursday• Starts this week (Time & Location TBD)
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Schedule
Last lecture: • CMOS logic gates
Today: • Project launch• CMOS Design optimization• Logical effort
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Switch Delay Model
A
Req
A
Rp
A
Rp
A
Rn CL
A
CL
B
Rn
A
Rp
B
Rp
A
Rn Cint
B
Rp
A
Rp
A
Rn
B
Rn CL
Cint
NAND-2 Inverter NOR-2
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Input Pattern Effects on Delay
Delay is dependent on thepattern of inputs
Low-to-high transition• both inputs go low
− delay is 0.69 Rp/2 CL• one input goes low
− delay is 0.69 Rp CL
High-to-low transition• both inputs go high
− delay is 0.69 2Rn CL
CL
B
Rn
ARp
BRp
A
Rn Cint
4
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57B=1→0, A=1
76B=1, A=1→0
35A=B=1→0
50B= 0→1, A=1
62B=1, A=0→1
69A=B=0→1
Delay(ps)
Input DataPattern
NMOS = 0.5µm/0.25 µmPMOS = 0.75µm/0.25 µmCL = 100 fF
time [ps]
Vol
tage
[V]
int
B
VDD
A
M3 M4A
B
F
M2
M1
-0.5
0
0.5
1
1.5
2
2.5
3
0 100 200 300 400
A=B=1→0
B=1→0, A=1
B=1, A=1→0
Delay Dependence on Input Patterns
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Transistor Sizing
CL
B
Rn
A
Rp
B
Rp
A
Rn Cint
B
Rp
A
Rp
A
Rn
B
Rn CL
Cint
2
2
2 2
11
4
4
5
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OUT = D + A • (B + C)
DA
B C
D
AB
C
1
2
2 2
4
48
8
Sizing of a Complex CMOS Gate
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Fan-In Considerations
DCBA
D
C
B
A CL
C3
C2
C1
Distributed RC model(Elmore delay)
tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)
Propagation delay deteriorates rapidly as a function of fan-in –quadratically in the worst case.
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tp as a Function of Fan-In
t p(p
s)
fan-in
0
250
500
750
1000
1250
2 4 6 8 10 12 14 16
tpHL
quadratic
linear
tp
tpLH
t p(p
s)
fan-in
0
250
500
750
1000
1250
2 4 6 8 10 12 14 16
tpHL
quadratic
linear
tp
tpLH
NAND2
Gates with fan-in > 4 should be avoided
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tp as a Function of Fan-Out
t p(n
orm
.)
eff. fan-out2 4 6 8 10 12 14 16
tpNAND2tpNOR2
tpINV
1
2
3
4
5
t p(n
orm
.)
eff. fan-out2 4 6 8 10 12 14 16
tpNAND2tpNOR2
tpINV
1
2
3
4
5All gates have the same drive current
Slope is a function of “driving strength”
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Fan-in: quadratic due to increasing resistance and capacitance
Fan-out: each additional fan-out gate adds two gate capacitances to CL
tp = a1FI + a2FI2 + a3FO
tp as a Function of Fan-In and Fan-Out
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Progressive transistor sizing• as long as fan-out capacitance dominates
InN CL
C3
C2
C1In1
In2
In3
M1
M2
M3
MNDistributed RC line
M1 > M2 > M3 > … > MN(the FET closest to theoutput is the smallest)
Can reduce delay by more than 20%; Be careful: input loading, junction caps, decreasing gains as technology shrinks
Fast Complex Gates: Design Technique 1
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Transistor ordering
C2
C1In1
In2
In3
M1
M2
M3 CL
C2
C1In3
In2
In1
M1
M2
M3 CL
critical path critical path
charged1
0→1charged
charged1
delay determined by time to discharge CL, C1 and C2
delay determined by time to discharge CL
1
1
0→1 charged
discharged
discharged
Fast Complex Gates: Design Technique 2
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Alternative logic structures
F = ABCDEFGH
Fast Complex Gates: Design Technique 3
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Isolating fan-in from fan-out using buffer insertion
CLCL
Fast Complex Gates: Design Technique 4
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Reducing the voltage swing
• linear reduction in delay• also reduces power consumption
But the following gate is much slower!• can use of “sense amplifiers” on the receiving end to
restore the signal level (memory design)
tpHL = 0.69 (3/4 (CL VDD)/ IDSATn )= 0.69 (3/4 (CL Vswing)/ IDSATn )
Fast Complex Gates: Design Technique 5
10
Logical EffortLogical Effort
EE141
Chip designers face wide array of choices• What is the best circuit topology for a function?• How large should transistors be?• How many stages of logic give least delay?
Logical Effort is a method to answer these Qs• Uses simple delay model• Back of the envelope calculations
Who cares about LE?• Circuit designers who waste time in simulate/tweak loop• High-speed logic designers need to know where time is
going in their logic• CAD designers need to understand circuits to build
better tools
? ? ?
Introduction
Courtesy: D. Harris, HMC
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Logical Effort Formalism (1/4)
⋅
+⋅=
⋅
+⋅⋅⋅=in
outp
in
outrinsicdrive C
CtC
CCRDelayγγ
1169.0 0int
Gate delay we used up to now:
Another way to write this formula is:
+⋅=
+⋅⋅⋅=
in
outgate
in
outgatedrive C
CCCCRDelay γτγ69.0
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Logical Effort Formalism (2/4)
+⋅+
+⋅+
+⋅=
+
+
+
++
2
3
1
21
j
jNORNOR
j
jINVINV
j
jNANDNAND C
CCC
CC
Delay γτγτγτ
In this example, the total delay is:
+⋅+
+⋅+
+⋅=
+
+
+
++
2
3
1
21
j
jNOR
INV
NOR
j
jINV
INV
INV
j
jNAND
INV
NAND
INV CC
CC
CCDelay γ
ττγ
ττγ
ττ
τ
Normalized to the intrinsic time constant of INV:
Courtesy: B. Murmann, Stanford
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Logical Effort Formalism (3/4)
Since it is hard to fit on the back of an envelope, we define new symbols:
)()()( 21 NORjNORINVjINVNANDjNAND PFOLEPFOLEPFOLED +⋅++⋅++⋅= ++
+⋅+
+⋅+
+⋅=
+
+
+
++NOR
j
j
INV
NORINV
j
j
INV
INVNAND
j
j
INV
NAND
INV CC
CC
CCDelay γ
ττγ
ττγ
ττ
τ 2
3
1
21
LogicalEffort
Fanout“Electrical Effort”
ParasiticDelay
Courtesy: B. Murmann, Stanford
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Logical Effort Formalism (4/4)
More nomenclature:• Dgate = LE·FO + P = Effort Delay + Parasitic Delay
Some options to find LE of a logic gate:• Set Rdrive equal, then compare Cin• Set Cin equal, then compare Rdrive• Or simply compare R and C ratio from first principles:
( )( )INVindrive
gateindrive
INV
gategate CR
CRLE
⋅
⋅==
ττ
Courtesy: B. Murmann, Stanford
13
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DEF: Logical effort is the ratio of the input capacitance to the input capacitance of an inverter delivering the same output current
Calculating Logical Effort
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LE Catalog of Gates
Source: “Logical Effort,”I. Sutherland, B. Sproull, D. Harris (Morgan-Kaufmann 1999)
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EE141
1
2
3
4
5
6
1 2 3 4 5
parasitic delay
effortdelay
Electrical effort: FO = Cout/Cin
Nor
mal
ized
del
ay: D
2-inp
ut NAND
invert
er LE = P =D =
LE = P =D =
4/3
1 1FO + 1
2(4/3)FO + 2
LE and P from Simulation Data
Dgate = LE·FO + P = Effort Delay + Parasitic Delay
EE141
Estimate the frequency of an N-stage ring oscillator:
Logical Effort: LE =
Electrical Effort: FO =
Parasitic Delay: P =
Stage Delay: D =
OSC Frequency: FOSC =
1
Cout/Cin = 1
pinv = 1
LE·FO + P = 21
2ND=
14Nτ
Warm-up Example 1
D
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Estimate the delay of a fanout-of-4 (FO4) inverter:
Logical Effort: LE =
Electrical Effort: FO =
Parasitic Delay: P =
Stage Delay: D =
1
Cout/Cin = 4
pinv = 1
LE·FO + P = 5
D
Warm-up Example 2
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Multistage Networks
Stage effort: SEi = LEi·FOi
Path electrical effort: FOpath = Cout /Cin
Path logical effort: LEpath = LE1LE2…LEN
Branching effort: Bpath = b1b2…bN
Path effort = LEpath·FOpath·Bpath
Path delay D = ΣDi = ΣPi + ΣFOi·LEi
( )∑=
⋅+=N
iiii FOLEPDelay
1
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Optimum Effort per Stage
PathEffortFOLESE N =⋅=∏When each stage bears the same effort:
N PathEffortSE =*
( ) PSENPFOLED iii +⋅=+⋅=∑ *min
Minimum path delay
Effective fanout of each stage: ii LESEFO *=
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Gate Sizing Problem
We will use the LE of the gate to help find the correct sizes• We know that the LE·FO for each gate should be the same
Before we do the math, we need to set a convention:• What does a gate size of “2” mean?• For an inverter, it is simple
− It has twice the C and ½ the R of an inverter of size “1”• For a gate, you have two options:
− Can define it to mean it has twice the C of an inverterOR
− Can define it to mean it has ½ the R
We assume the size is a measure of the input capacitance• A size 2 gate has twice the Cin of the inverter
Courtesy: B. Murmann, Stanford
17
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Gate Sizing Example (1/3)
FO
From: David Harris
First Compute Path Effort
∏ ⋅= FOLEPathEffort
9400201
34
35
101 =
×
×
×
=
zyz
xyx
The optimal stage effort is:
45.19
400*4/1
=
=⋅= FOLESE
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Gate Sizing Example (2/3)
FOWe can now size the gates, since for all of them:
We have:*SE
CLEC outin ⋅=
8.1345.1
201 =⋅=z
7.1245.13
4=⋅=
zy
5.1445.13
5=⋅=
yx
1045.1
1 =⋅=xCin
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Gate Sizing Example (2/3)
FO
The total normalized delay is (assuming Pinv=1):
8.11)1221(45.14*4 =++++⋅=+= ∑PSED
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Add Branching Effort
Branching effort:
pathon
pathoffpathonC
CCb
−
−− +=
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515
15
90
90
LE =FO =PE =SE1 =SE2 =PE =
190/5 = 1818 (wrong!)(15+15)/5 = 690/15 = 636, not 18!
Introduce new kind of effort to account for branching:
• Branching Effort:
• Path Branching Effort:
Con-path + Coff-path
Con-pathb =
Π biB =
Now we can compute the path effort:• Path Effort: PE = ∏LE·FO·B
Branching Example 1
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Select gate sizes y and z to minimize delay from A to B
Logical Effort: LE =
Electrical Effort: FO =
Branching Effort: B =
Path Effort: PE =
Best Stage Effort: SE =
Delay: D =
(4/3)3
Cout/Cin = 9
2•3 = 6
∏LE·FO·B= 128
PE1/3 ≈ 5
3•5 + 3•2 = 21
Work backward for sizes:
5z =9C•(4/3)
= 2.4C
5y =3z•(4/3)
= 1.9C
Branching Example 2
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Multi-level Logic: What is Best?
LE = 10/3(3.33)
LE = 10/3(3.33)
LE = 80/27(2.96)
10/3
1
2
5/3
10/35/3
4/3 1
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Handling Wires & Fixed Loads
CL
Cw
( )∑=
+⋅+=N
iiiii WFOLEPDelay
1)(
21
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Logical Effort “Design Flow”
Compute the path effort: Path Effort = ∏ LE·FO·B
Find the best number of stages: N* ~ log4(PathEffort)
Compute the stage effort: SE* = (PathEffort)1/N
Working from either end, determine gate sizes:
Reference: Sutherland, Sproull, Harris, “Logical Effort,” (Morgan-Kaufmann 1999)
*SECBLEC out
in ⋅⋅=
EE141 42
Next Lecture
Ratioed Logic
Pass-Transistor Logic
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