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EE141
1
EE141EECS141 1Lecture #61
EE141-Fall 2011
Digital Integrated
Circuits
Lecture 9
Inverter Delay Optimization
and CMOS Power
EE141EECS141 2Lecture #62
Administrative Stuff
Sw lab #4 next week
Homework #4 due today
Homework #5 due next Thursday
Midterm #1 on October 5, evening
EE141
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EE141EECS141 3Lecture #63
Last Lecture
Last lecture
Finish MOS capacitor
Inverter delay
Today’s lecture
Device sizing
Buffer sizing
Power
Reading (5.4-5.5; 4.1-4.3)
EE141EECS141 4Lecture #64
Device Sizing
EE141
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EE141EECS141 5Lecture #65
2 4 6 8 10 12 142
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8x 10
-11
S
t p(s
ec)
Device Sizing
(for fixed load)
Self-loading effect:Intrinsic capacitancesdominate
EE141EECS141 6Lecture #66
1 1.5 2 2.5 3 3.5 4 4.5 53
3.5
4
4.5
5x 10
-11
b
t p(s
ec)
NMOS/PMOS ratio
tpLH tpHL
tp b = Wp/Wn
EE141
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EE141EECS141 7Lecture #67
Inverter Delay
Optimization
EE141EECS141 8Lecture #68
Inverter Chain
CL
In Out
For some given CL:
How many stages are needed to minimize delay?
How to size the inverters?
Anyone want to guess the solution?
EE141
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EE141EECS141 9Lecture #69
Careful about Optimization
Problems
Get fastest delay if build one very big
inverter
So big that delay is set only by self-loading
Likely not the problem you’re interested in
Someone has to drive this inverter…
Cload
EE141EECS141 10Lecture #610
Engineering Optimization
Problems in GeneralNeed to have a set of constraints
Constraints key to:
Making the result useful
Making the problem have a ‘clean’ solution
For sizing problem:
Need to constrain size of first inverter
EE141
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EE141EECS141 11Lecture #611
Delay Optimization Problem #1
You are given:
A fixed number of inverters
The size of the first inverter
The size of the load that needs to be driven
Your goal:
Minimize the delay of the inverter chain
Need model for inverter delay vs. size
EE141EECS141 12Lecture #612
, ,P sq p N sq n W
P N
L LR R R R R
W W
tpHL = (ln 2) RNCtot = tpLH = (ln 2) RpCtotDelay:
2W
W
3in g
C W CLoading on the previous stage:
Inverter Delay Minimum length devices, L = 0.09mm
Assume that for WP = 2WN = 2W
approximately equal resistances, RN = RP
approx. equal rise and fall delays, tpHL = tpLH
Analyze as an RC network:
EE141
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EE141EECS141 13Lecture #613
Cint CL
Replace ln(2) with k (a constant):
Delay = kRWCint + kRWCL
Delay = kRsq,n(L/W)(3WCd) + kRsq,n(L/W)CL
CN = WCg
CP = 2WCg
2W
W
Inverter Delay
int3
dC WC
,W sq n
LR R
W
3in g
C W C
EE141EECS141 14Lecture #614
Load
Delay
Cint CL
Delay = kRW Cin(Cint/Cin+ CL /Cin)
= 3kLRsq,nCg[Cd/Cg + CL/(3WCg)]
= Delay (Internal) + Delay (Load)
CN = WCg
CP = 2WCg
2W
W
Inverter with Load
EE141
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EE141EECS141 15Lecture #615
in int
~
/
W int L
p W in L in inv
D elay R C C
t kR C C C C C t f
Cint = Cin ( 1 for inverter)
f = CL/Cin – electrical fanout
RW = Rsq(L /W) ; Cin =3WCg
tinv = 3∙ln(2)∙L∙RsqCg
Delay Formula
tinv is independent of sizing of the gate!!!
EE141EECS141 16Lecture #616
CL
In Out
1 2 N
tp = tp1 + tp2 + …+ tpN
, 1
,
in j
pj inv
in j
Ct t
C
, 1
, , 1
1 1 ,
,
N Nin j
p p j inv in N L
j i in j
Ct t t C C
C
Apply to Inverter Chain
EE141
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EE141EECS141 17Lecture #617
Optimal Tapering for Given N
, 1
2
, , 1 ,
10
p in j
inv inv
in j in j in j
dt Ct t
dC C C
Delay equation has N-1 unknowns, Cin,2 … Cin,N
To minimize the delay, find N-1 partial derivatives:
, , 1
, 1 ,
... ...in j in j
p inv inv
in j in j
C Ct t t
C C
EE141EECS141 18Lecture #618
, , 1 , 1in j in j in jC C C
Optimal Tapering for Given N (cont’d)
Result: every stage has equal fanout:
In other words, size of each stage is geometric
mean of two neighbors:
Equal fanout every stage will have same delay
, , 1
, 1 ,
in j in j
in j in j
C C
C C
EE141
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EE141EECS141 19Lecture #619
,1/
N
L inf F C C
NFf
N
p invt N t F
Optimum Delay and Number of Stages
When each stage has same fanout f :
Effective fanout of each stage:
Minimum path delay:
EE141EECS141 20Lecture #620
Example
CL= 8 C1
In Out
C11 f f 2
283
f
CL/C1 has to be evenly distributed across N = 3 stages:
EE141
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EE141EECS141 21Lecture #621
Delay Optimization Problem #2
You are given: The size of the first inverter
The size of the load that needs to be driven
Your goal: Minimize delay by finding optimal number and
sizes of gates
So, need to find N that minimizes:
Np inv L in
t Nt C C
EE141EECS141 22Lecture #622
1/
lnln
N
p inv L in inv L in
ft Nt C C t C C
f
2
ln 1ln 0
ln
p
inv L in
t f ft C C
f f
For = 0, f = e, N = ln (CL/Cin)
ln
ln
L inN
L in
C Cf C C N
f
ff 1exp
Solving the Optimization Rewrite N in terms of fanout/stage f:
EE141
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EE141EECS141 23Lecture #623
Optimum Effective Fanout f
ff 1exp
Optimum f for given process defined by
0 0.5 1 1.5 2 2.5 32.5
3
3.5
4
4.5
5
f op
t
fopt = 3.6
for = 1
e
Intuition: why does f go up with ?
EE141EECS141 24Lecture #624
In Practice: Plot of Total Delay
Curves very flat for f > 2
Simplest/most common choice: f = 4
[Hodges, p.281]
EE141
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EE141EECS141 25Lecture #625
,N
p inv L int Nt F F C C
Normalized Delay As a Function of F
Textbook: page 210
( = 1)
EE141EECS141 26Lecture #626
Buffer Design
1
1
1
1
8
64
64
64
64
4
2.8 8
16
22.6
N f tp
1 64 65
2 8 18
3 4 15
4 2.8 15.3
EE141
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EE141EECS141 27Lecture #627
What About Energy (and Area)?
Ignoring diffusion capacitance:
Ctot = Cin + f·Cin + … + fN·Cin
= Cin·(1 + f + … + fN)
= Cin + Cin·fN + Cin·f·(1 + f + … + fN-2)
Overhead !!! f(fN-1-1) / (f-1)
Example (=0): CL = 20pF; Ci = 50fF → N = 6
Fixed: 20pF
Overhead: 11.66pF !!!
Cin fCin f2Cin f
3Cin
f4Cin
EE141EECS141 28Lecture #628
Example Overhead Numbers
Example: CL = 20pF; Cin = 50fF
2 3 4 5 6 7 8 9 100
5
10
15
20
25
2 3 4 5 6 7 8 9 100
5
10
15
20
25
Ove
rhea
d C
ap
ac
ita
nc
e (
pF
)
2 3 4 5 6 7 8 9 1015
20
25
30
35
40
Dela
y (
t inv)
Number of Stages
EE141
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EE141EECS141 29Lecture #629
CMOS Power
Dissipation
EE141EECS141 30Lecture #630
Where Does Power Go in CMOS?
Switching power
Charging/discharging capacitors
Leakage power
Transistors are imperfect switches
Short-circuit power
Both pull-up and pull-down on during
transition
Static currents
Biasing currents, in e.g. analog, memory
EE141
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EE141EECS141 31Lecture #631
Dynamic Power Consumption
One half of the energy from the supply is consumed in the pull-up network, one half is stored on CL
Energy from CL is dumped during the 10 transition
2
10 DDLVCE
2
2
1DDLR
VCE iL
Vin Vout
CL
VDD
2
2
1DDLC
VCE
EE141EECS141 32Lecture #632
Dynamic Power ConsumptionPower = Energy/transition • (Transition rate/2)
= Energy/transition • (Rising transition rate)
= CLVDD2 • f01
= CLVDD2 • f • P01
= CswitchedVDD2 • f
Power dissipation is data dependent – depends on the switching probability
Switched capacitance Cswitched = CL • P01
EE141
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EE141EECS141 33Lecture #633
Transition Activity and Power
Energy consumed in N cycles, EN:
EN = CL • VDD2 • n01
n01 – number of 01 transitions in N cycles
fVCN
nf
N
EP
DDLN
N
Navg
210limlim
0 1
0 1limN
n
N
fVCPDDLavg
2
10
EE141EECS141 34Lecture #634
Short Circuit Current
Short circuit current usually well controlled
Large load Small load
EE141
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EE141EECS141 35Lecture #635
Transistor Leakage
Transistors that are supposed to be off
actually leak
Input at VDD Input at 0
VDD 0V
VDD
ILeak
VDD0V
VDD
ILeak
EE141EECS141 36Lecture #636
JS = 10-100 pA/mm2 at 25 deg C for 0.25mm CMOS
JS doubles for every 9 deg C!
Much smaller than transistor leakage in deep submicron
Diode Leakage
IDL = JS ´ A
EE141
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EE141EECS141 37Lecture #637
Transistor Leakage
-9
-8
-7
-6
-5
-4
-3
0 0.2 0.4 0.6 0.8 1 1.2
V G S [V ]
log
ID
S [
log
A]
Drain leakage current is exponential with VGS-VT
VDS = 1.2V
G
S D
Sub
Ci
Cd
EE141EECS141 38Lecture #638
Sub-Threshold Conduction
0 0.5 1 1.5 2 2.510
-12
10-10
10-8
10-6
10-4
10-2
VGS
(V)
I D(A
)
VT
Linear
Exponential
Quadratic
Typical values for S-1:60 .. 100 mV/decade
Inverse Subthreshold Slope:
0~ , 1
G S Tq V V
DnkT
D
ox
CI I e n
C
S-1 is DVGS for ID2/ID1 =10
-1
EE141
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EE141EECS141 39Lecture #639
Transistor Leakage vs. VDS
Two effects:
• diffusion current (like a bipolar transistor)
• exponential increase with VDS (h: DIBL)
3-10x in
current
technologies
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4
V dS [V]
I DS
[nA
]
01
G S T D S D Sq V V V qV
nkT kT
D
WI I e e
L
h
EE141EECS141 40Lecture #640
Next Lecture
Wires