Classification of Digital Circuits

Combinational.Output depends only on current input values.

Sequential.Output depends on current input values and present state of the circuit, where the present state of the circuit is the current value of the devices’ memory.Also called finite state machines.

State of a CircuitThe contents of storage elements.A collection of know internal signal values that contain information about the past necessary to account the future behavior of the circuit.

ClockSignal that determines the change of state in most sequential circuits.

tLtHtper

state changes occur here(a)

state changes occur here

duty cycle = tH / tper

frequency = 1 / tper

period = tper

duty cycle = tL / tper

Bi-stable ElementsThe simplest sequential circuit.It consist of a pair of inverters connected as shown below. Notice the feedback loop.

Vin1 Vout1

Vout2Vin2

Digital AnalysisTwo stable states.If Q is HIGH then the lower inverter has a HIGH at its input and a LOW at its output. This in turn forces the upper inverter’s input to be LOW and its output to be HIGH.If Q is LOW then the lower inverter has a LOW at its input and a HIGH at its output. This in turn forces the upper inverter’s input to be HIGH and its output to be LOW.

Analog AnalysisConsidering the steady state behavior of the bistable element.

Vin1 = Vout2

Vin1 = T(Vin2)Vin1 = T(Vout1)Vin1 = T(T(Vin1))

= Vout2Vin1

= V in2

stable

metastable

stable

Transfer function:

Vout1 = T(Vin1)

Vout2 = T(Vin2)

Analog AnalysisMetastable behavior:

Consider the middle intersecting point in the diagram shown below.What would happen if a small amount of noise varies either input voltage.

= Vout2Vin1

= V in2

stable

metastable

stable

Analog AnalysisThe drawing on this slide shows a very good analogy to the stable and metastable behavior of a bi-stable element.

stable stable

metastable

Latches and Flip-FlopsBinary cells capable of storing 1 bit of information.Generates one of two possible stable states.Two outputs labeled Q and Q’.One or more inputs.

Latches and Flip-FlopsThese sequential devices differ in the way their outputs are changed:

The output of a latch changes independent of a clocking signal.The output of a flip–flop changes at specific times determined by a clocking signal.

S-R LatchR

last Q

(a) (b)

last QN

SR latch based on NOR gates.The S input sets the Q output to 1 while R reset it to 0.

S-R LatchR

last Q

(a) (b)

last QN

When R=S=0 then the output keeps the previous value.When R=S=1 then Q=Q’=0, and the latch may go to an unpredictable next state.

S-R Latch

Double negation is not a good idea. It is confusing and it creates problems.

(b) (c)(a)

S-R LatchS

tpHL(RQ)tpLH(SQ)

tpw(min)

(a) (b)

S’-R’ Latch

1 01 1 last Q

(a) (b) (c)

last QN

QNor S

S_L R_L

S’R’ latch based on NAND gates.The S’ input sets the Q output to 1 while R’ reset it to 0.

S’-R’ Latch

When R’=S’=1 then the output keeps the previous value.When R’=S’=0 then Q=Q’=1, and the latch may go to an unpredictable next state.

1 01 1 last Q

(a) (b) (c)

last QN

QNor S

S_L R_L

S-R Latch With EnableThe outputs change only when the enable input C is asserted.

0 0 1 last Q

xx 0 last Q

(b) (c)(a)

last QN

last QNQN

S-R Latch With EnableS

Ignored since C is 0. Ignored until C is 1.

Notice that the outputs only change when the input C is asserted.

D LatchThis latch eliminates the problem that occurs in the S’R’ latch when R=S=0.C is an enable input:

When C=1 then the output follows the input D and the latch is said to be open. Due to this fact this latch is also called transparent latch.When C=0 then the output retains its last value and the latch is said to be closed.

(b) (c)(a)

x0 last Q

last QN

D Latch

(b) (c)(a)

x0 last Q

last QN

D Latch

For proper operation the D input must not change during a time interval around the falling edge of C.This time interval is defined by the setup time – tsetup and the hold time –thold .

tholdtsetuptpLH(DQ)tpLH(DQ)

tpHL(DQ)tpLH(CQ)

tpHL(CQ)

(1) (2) (3) (5)(4)

Edge Triggered D Flip-FlopThis flip-flop is made out of two D latches. The first latch is the master, and the second the slave.When CLK_L = 1 the master is open (on) and the slave is closed (off). Qmand Ds follow Dm .

(b) (c)(a)

0x last Q

1x last Q

last QN

Edge Triggered D Flip-FlopWhen CLK_L = 0 the master is closed, the slave is open and Qm is transferred to Qs . Note that Qs does not change if Dm changes because the master latch is closed leaving Qmfixed.

(b) (c)(a)

0x last Q

1x last Q

last QN

Edge Triggered D Flip-Flop

Positive edge-triggered D flip-flop.Q* = D

(b) (c)(a)

0x last Q

1x last Q

last QN

If the set-up and hold times are not met the flip-flop’s output will go to a stable, though unpredictable, state.

tholdtsetuptpHL(CQ)tpLH(CQ)

Asynchronous inputs are used to force the output of the flip-flop to a particular state.PR (preset) – Q = 1.CLR (clear) – Q = 0.

CLR_L Q

Edge Triggered D Flip-FlopEdge triggered D flip-flop with enable.

(b) (c)(a)

0x last Q

1x last Q

QCLKQN

last QN

x 0 last Q last QN

Scan Flip-FlopThis flip-flop allows its inputs to be driven from alternate sources, which can be very useful during device testing.

(b) (c)(a)

0x last Q

1x last Q

last QN

ASICexternal

Master/Slave S-R Flip-FlopThe postponed output indicator shows that the output signal does not change until the enable C input is negated.Flip-flops with this kind of behavior are called pulse-triggered flip-flops.Q* = S+R’QSR = 0

(b) (c)(a)

last Q last QN

x 0 last Q last QNx

1 0 10

0 1 01

1 undef. undef.1

Master/Slave S-R Flip-Flop

Ignored since C is 0. Ignored until C is 1. Ignored until C is 1.

Master/Slave J-K Flip-FlopThe J and the K inputs of the J-K flip-flop are analogous to the S and R inputs of the S-R flip-flop, except in the case where J=K=1. In this case the outputs of the J-K flip-flop will toggle to the opposite state.

(b) (c)(a)

last Q last QN

x 0 last Q last QNx

1 0 10

0 1 01

1 last QN last Q1

Master/Slave J-K Flip-FlopQ* = JQ’+K’Q

Ignoredsince QN is 0.

Ignoredsince C is 0.

Ignoredsince QN is 0.

Ignoredsince Q is 0.

Ignoredsince C is now 0.

(b) (c)(a)

last Q last QN

x 0 last Q last QNx

1 0 10

0 1 01

1 last QN last Q1

Edge Triggered J-K Flip-FlopQ* = JQ’+K’Q

(b)(a) (c)CLK

last Q last QN

x 1 last Q last QNx

x 0 last Q last QNx

1 0 10

0 1 01

1 last QN last Q1

Edge Triggered J-K Flip-Flop74LS109

CLR_L Q

T Flip-FlopFlip-flop changes state every tick of the clock.Q* = Q’

(a) (b)

T Flip-Flop With EnableFlip-flop changes state every tick of the clock when enable is asserted.Q* = ENQ’+EN’Q

(a) (b)

Clocked SynchronousState-Machine Analysis

State machine – Another term for a sequential circuit.Clocked – Refers to the fact that their flip-flops employ a clock input.Synchronous – Same clock signal is used by all flip-flops.A state machine with n flip-flops can have up to 2n distinct states.

State Machine StructureState memory – a set of n flip-flops.Next-state logic – combinational logic circuit which determines the next state.

Next-state = F(current state,input)Output logic – combinational logic circuit which determines the output.There are two models for the output logic:

Mealy Model.Moore Model.

Mealy ModelThe output is based on both current state and input.

Output = G(current state,input)

StateMemory

clock input

Next-stateLogic

OutputLogic

excitation current stateinputs

clocksignal

outputs

Moore ModelThe output is based on current state only.

Output = G(current state)

In high speed circuits the output circuit may be absent and the output is generated directly from the flip-flop’s outputs. This is called output coded state assignment.

StateMemory

clock input

Next-stateLogic

OutputLogic

clocksignal

outputs

Mealy ModelPipelined outputs – a design approach that ensures the output of a Mealy model circuit only changes with the clock.

StateMemory

clock input

Next-stateLogic

OutputLogic

clocksignal

pipelinedoutputs

OutputPipelineMemory

clock input

AnalysisDetermine the next-state and output functions F and G.Use F and G to construct a state/output table that completely specifies the next state and output of the circuit for every possible combination of current state and input.Draw a state diagram.

State Machines With D Flip-FlopsD0 = Q0 · EN’ + Q0’ · END1 = Q1 · EN’ + Q1’ · Q0 · EN + Q1 · Q0’ · EN

current state

excitation

output

clock signal

Next-state Logic F State Memory Output Logic G

State Machines With D Flip-FlopsQ0* = D0Q1* = D1

Q0* = Q0 · EN’ + Q0’ · ENQ1* = Q1 · EN’ + Q1’ · Q0 · EN + Q1 · Q0’ · EN

current state

excitation

output

clock signal

State Machines With D Flip-FlopsMAX = Q1 · Q0 · EN

current state

excitation

output

clock signal

State Machines With D Flip-FlopsQ0* = Q0 · EN’ + Q0’ · ENQ1* = Q1 · EN’ + Q1’ · Q0 · EN + Q1 · Q0’ ·ENMAX = Q1 · Q0 · EN

Present State Input Next State OutputS EN S* MAXA 0 A 0A 1 B 0B 0 B 0B 1 C 0C 0 C 0C 1 D 0D 0 D 0D 1 A 1

Input OutputQ1 Q0 EN Q1* Q0* MAX0 0 0 0 0 00 0 1 0 1 00 1 0 0 1 00 1 1 1 0 01 0 0 1 0 01 0 1 1 1 01 1 0 1 1 01 1 1 0 0 1

Present State Next State

State Machines With D Flip-Flops

(a) EN (b) EN (c) EN Table 7-2Transition, state, and state/output tables for the state machine in Figure 7-38.

Q1 Q0 0 1 S 0 1 S 0 1

00 00 01 A A B A A, 0 B, 0

01 01 10 B B C B B, 0 C, 0

10 10 11 C C D C C, 0 D, 0

11 11 00 D D A D D, 0 A, 1

Q1∗ Q0∗ S∗ S∗, MAX

(a) EN (b) EN (c) EN Table 7-2Transition, state, and state/output tables for the state machine in Figure 7-38.

Q1 Q0 0 1 S 0 1 S 0 1

00 00 01 A A B A A, 0 B, 0

01 01 10 B B C B B, 0 C, 0

10 10 11 C C D C C, 0 D, 0

11 11 00 D D A D D, 0 A, 1

Q1∗ Q0∗ S∗ S∗, MAX

EN = 1

(MAX = 0)

EN = 1

(MAX = 0)

EN = 1

(MAX = 0)

EN = 0

(MAX = 0)

EN = 0

(MAX = 0)

EN = 0

(MAX = 0)

EN = 0

(MAX = 0)

EN = 1

(MAX = 1)

EN = 1

(MAX = 0)

EN = 1

(MAX = 0)

EN = 1

(MAX = 0)

EN = 0

(MAX = 0)

EN = 0

(MAX = 0)

EN = 0

(MAX = 0)

EN = 0

(MAX = 0)

EN = 1

(MAX = 1)

STATE D A AC D DA A B C C

State Machines With J-K Flip-Flops

Clocked Synchronous State Machine Design

Derive a state/output table from the problem specification.Minimize the number of states in the state/output table by eliminating equivalent states.Choose a set of state variables. Assign to each state a unique combination from the set derived above.Create a transition/output table.Choose a flip-flop type and derive its excitation table.Using the excitation table fill the values for the input excitation function columns on the transition/output table.Derive the excitation and output equations.Draw logic diagram.

Design a sequential circuit with one input ( I ) and one output ( Z )The output is asserted when the input sequence 0-1-1 is received.See state/output table below.

Input OutputI Z0 S 0 01 Init 00 S 0 01 S 01 00 S 0 01 S 011 00 S 011 11 S 011 1

Present State Next stateInit

Set of state variables and their unique assignment to the different states.

State Q1 Q0Init 0 0S 0 0 1S 01 1 1S 011 1 0

Transition/output table

Input OutputQ 1 Q 0 I Q 1 * Q 0 * Z

0 0 0 0 1 00 0 1 0 0 00 1 0 0 1 00 1 1 1 1 01 0 0 1 0 11 0 1 1 0 11 1 0 0 1 01 1 1 1 0 0

Present State Next state

Excitation table.

D J K T0 0 0 0 X 00 1 1 1 X 11 0 0 X 1 11 1 1 X 0 0

Present State Next StateRequired inputs

Equations derived from the table above:J1 = IQ0

K1 = I’Q0

J0 = I’Q1‘K0 = IQ1

Z = Q1Q0’

Input OutputQ 1 Q 0 I Q 1 * Q 0 * Z J 1 K 1 J 0 K 0

0 0 0 0 1 0 0 X 1 X0 0 1 0 0 0 0 X 0 X0 1 0 0 1 0 0 X X 00 1 1 1 1 0 1 X X 01 0 0 1 0 1 X 0 0 X1 0 1 1 0 1 X 0 0 X1 1 0 0 1 0 X 1 X 01 1 1 1 0 0 X 0 X 1

Present State Next state Input Excitation

Logic diagram.J1 = IQ0

K1 = I’Q0

J0 = I’Q1‘K0 = IQ1

Z = Q1Q0’

Classification of Digital Circuits - LSU Set 1.pdf · Classification of Digital Circuits...

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