Class 1 Semiconductors

College of Nanoscale Science and Engineering

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CNSE College of Nanoscale Science and Engineering

D. Coolbaugh 1

CNSE

Electronic Packagaing Fundamentals

Section 1 – Semiconductor Overview

Dr. Douglas Coolbaugh

Albany CNSE Use ONLY - Packaging Fundamentals ClassCourse Material – Not for distribution

All References given on last page

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What is packaging – Provide wiring from chip to external electronics

0 Level Package Chip Wiring / Far BEOLFar BEOL – Al Pads forWirebond or Solder Bump

1st Level packageSingle or multiple chipsOn chip Carrier

Al Wirebond or Solder Bump Pads Wirebond

BGA

PLCC

PGA

Chip on Ceramic Carrier

2nd Level Pkg – Assemble components on PCBThru-Hole Attach

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Levels of Packaging

Level Type

0 Chip Level Wiring / Metal Contacts

1, 1.5 Single / Multi -Chip Pkg

Chip to Package

2 Chip Pkg on PWB Chip on board

3 Multiple PWB / Full Machine Assembly

Wiring of PWBsCables etc

Ref 4 - Text

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ICs and Packaging

Performance Driven Markets•Computers – Cost Performance•Hi-end Computers•Military•Medical•ASICs

•Hi Reliability•Space•Automotive•Sensors•Memory

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ICs and Packaging

• Cost / Size Driven Market• Low Cost Hi Volume• Cell Phones• Camcorders• Laptops• Digital Cameras • PDAs

• These markets may require different levels of IC Technologies –Performance Driven or Cost Driven (Low Power

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IO drives packaging complexity and cost

Ref 6

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IOs

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IC fabrication and basics

• ICs have evolved rapidly since 1950

• Ge was 1st transistor produced in 1950s

• Si replaced Ge due to quality and stability of SiO2

• Major take-off of Semiconductors in 60s• Fairchild / Intel / IBM others

• Microprocessors – Intel 1971

• DRAM – Dynamic Access Memory – 1970s

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Derivatives R&D at CNSE - Ref 7

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ITRS Raodmap for Hi-Performance CMOS – Ref 1

Node units 250 180 % Scale

130 % scale

90 % Scale

65 %Scale

Lgate nm 180 130 73% 92 71 63 68 43 68%

Tinv nm 6.2 4.45 72% 3.12 70% 2.2 70% 1.95 89%

Vdd V 2.5 1.8 72% 1.5 83% 1.2 80% 1 83%

MxPitch

0.8 0.56 70% 0.4 71% 0.28 70% 0.20 71%

Data from J. Pekarik IBM CMOS Node Scaling

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Gate Scaling – Contacted Pitch - IBM

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PC Contacted Pitch – IBM – Ref 9

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Contact / Spacer / Gate Scaling – IBM – Ref 9

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Scaling for Logic Applications – Ref 9

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IC Drivers

• Overall IC Drivers• Performance• Cost• Complexity• Size

• Critical Features that are used to determine scaling density

• Shallow Trench Isolation Pitch• Gate Length • Dielectric Thickness / Leakage• Contact Size• Metal 1 Pitch

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Key Semiconductor Features

• Feature size is driven by Lithography and Etch

• Key Features

• RX – Shallow Trench • PC – Gate Length• CA – Contact size• M1 – Metal 1

• Pitch used to measure feature size

• Pitch is the width of a line and space

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Pitch

RX Pitch – in 45 nm this is 140 nm (70 line / 70 space)

Sometimes Pitch is thought of ½ line / space / ½ lineIn both cases it is the same number

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Key feature sizes

• Key Features

• RX Pitch

• Lpoly – PC minimum gate length – Ldrawn – Lpoly is the electrical measurement

• CA CD – this is the size of the contact to the gate / diffusions at the topfor 45 nm it is 65 nm CD. CD means critical dimension

• M1 Pitch – this is cirtical for wiring

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CMOS Integration

TrenchIsolation

WellImplants

Gate OxGate polySpacer 0/1

Pwell Nwell

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Litho Exposure Wavelengths

MUV

EUV – 13.5

Wikipedia

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Lithography Scaling and ITRS Roadmap – Ref 9

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Basic Lithography Process

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CMOS Integration

Pwell Nwell

ImplantExt/HaloCMOS

Pwell Nwell

NFET PFET

Spacer IIN/P SDOPSilicide

N+P+

Pwell Nwell

N+P+

Barrier Nitride

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CMOS Integration

Pwell Nwell

N+P+

CA Oxide

Pwell Nwell

N+P+CA ContactsM1 Oxide - Etch

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CMOS Integration

Pwell NwellGe

N+P+

Pwell NwellGe

N+P+

FinalMetallizationTo Mx,etc

ILD For V1/M2

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HiK MG – Intel – Replacement Metal Gate – Ref 3

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Gate First vs Replacement MG – Note FUSI Gate does not work

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2 types of MG integration – gate first versus replacement gate

Ref 3

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Intel Process Flow – HK MG

Intel 45 nm HiKRef 3

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HK – Higher Ion due to increase in Capacitance

Metal Gate adds No depletion like Poly Gate

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45 nm HiK-MG vs Poly Gate / SiON - Intel

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References1. Pekarik, John, “Scaled CMOS Technology and Models to Support Wireless Applications,” IBM Corp., 2008.2. Horowittz, Mark, Packaging and IO, Stanford University, 2010.3. Mistry, K. et al. “ A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers,

193nm Dry Patterning, and 100% Pb-free Packaging,” Intel Corp.4. Greig, William J.,”Integrated Circuit Packaging, Assembly and Interconnections, “2007 Springer Science and Business.5. Tarter, Thomas S., “Design of High Density Packaging: Tools and Knowledge, Packaging Science Services, 2010.6. Leonardo, System in a Package, Single Chip Packaging, 2004.7. Stork, Hans, Nanotechnology in the Semiconductor Industry, Applied Materials, 2010.8. Morris, James, E., Electronics Packaging, Fall 2007, Portland State University.9. M. Guillorn, J. Chang and W. Haensch, FinFETS for 22 nm node, IBM Research, 2007.