Chapter 5 Digital Design, 5ed. Mano & Ciletti. · Combinational vs. Sequential Combinational...

Synchronous Sequential Logic

Chapter 5Digital Design, 5ed.

Mano & Ciletti.

Module Outline

● Introduction● Sequential Circuits

– Latches, and Flip‐Flops

● Analysis of Clocked Sequential Circuits● Synthesizable HDL Models of Sequential Circuits

– Verilog

● State Reduction and Assignment● Design Procedure

– Thought process

Outline

● Clock signal ● Sequential Circuits● Synchronous vs. Asynchronous circuits● Flip-Flops, Latches

Clock Cycle● Clock is a special signal to hardware● A well defined indication for event start and

complete.

Time (ns) 1.0 2.01.5 2.5

Clock Cycle● Clock is a special signal to hardware● A well defined indication for event start and

complete.

Time (ns)

Clock

1.0 2.01.5 2.5

Clock Cycle● Clock is a special signal to hardware● A well defined indication for event start and

complete.

Time (ns)

Clock

1.0 2.01.5 2.5

Rising Edge Falling edge

Clock Cycle● Clock is a special signal to hardware● A well defined indication for event start and

complete.

Time (ns)

Clock

1.0 2.01.5 2.5

Rising Edge Falling edge

Levels

Clock Cycle● Clock is a special signal to hardware● A well defined indication for event start and

complete.

Time (ns)

Clock

1.0 2.01.5 2.5

Addition ADDITION COMPLETES INTHIS DURATION

ANOTHER BLOCK

Clock Cycle● Clock is a special signal to hardware● A well defined indication for event start and

complete.

Time (ns)

Clock

1.0 2.01.5 2.5

Addition ADDITION COMPLETES INTHIS DURATION

Both operands are ready.

The result is ready.

ANOTHER BLOCK

Clock Cycle● Clock is a special signal to hardware● A well defined indication for event start and

complete.

Time (ns)

Clock

1.0 2.01.5 2.5

Addition ADDITION COMPLETES INTHIS DURATION

Both operands are ready.

The result is ready.

The result is consumed by another block.

ANOTHER BLOCK

Clock Cycle● Clock is a special signal to hardware● A well defined indication for event start and

complete.

Time (ns)

Clock

1.0 2.01.5 2.5

Addition ADDITION COMPLETES INTHIS DURATION

ANOTHER BLOCK

Clock Cycle● Clock is a special signal to hardware● A well defined indication for event start and

complete.

Time (ns)

Clock

1.0 2.01.5 2.5

Addition ADDITION COMPLETES INTHIS DURATION

ANOTHER BLOCK

Posedge occured.Copy inputsto outputs.

Posedge occured.Copy inputsto outputs.

Sequential Circuits

● We’ll build a few of these

Combinational Circuits vs. Sequential Circuits

● Combinational Circuits–

● Sequential circuits–

Combinational vs. Sequential

● Combinational Circuits: Output depends only and immediately on their inputs– No memory

– No dependence on past input values

Combinational vs. Sequential

● Combinational Circuits: Output depends only and immediately on their inputs

● Sequential circuits: Have memory– Storage elements

– Can store, retain, and then retrieve information when needed at a later time

Combinational vs. Sequential

● Combinational Circuits: Output depends only and immediately on their inputs

● Sequential circuits: Have memory– Storage elements

– Can store, retain, and then retrieve information when needed at a later time

– Used to stabilize inputs to combinational circuits● Eg. RF feeds Adder

Sequential Circuit

Sequential Circuit

Sequential Circuit

● Information stored defines state of sequential circuit

●

Sequential Circuit

● Information stored defines state of sequential circuit

● Output depends on inputs + present state of the storage elements

Sequential Circuit

● Information stored defines state of sequential circuit

● Output depends on inputs + present state of the storage elements– Output Transition

A System with States, Transitions

A System with States, Transitions

●

– Nothing happens

● On a Coin insert, system transitions to “Unlocked” state● When in “Unlocked” state, adding more coins does not

change the state● “Push” changes state back to “Locked”

●

●

Sequential Circuits

● Synchronous●

● Asynchronous●

Sequential Circuits

● Synchronous– Behavior defined at discrete instants of time

– Eg. at the rising edge of a clock signal: copy input to output.

● Asynchronous

Sequential Circuits

● Synchronous– Behavior defined at discrete instants of time

– Eg. at the rising edge of a clock signal: copy input to output.

● Asynchronous– No clock signal to mark time

– Uses signals to indicate completion of tasks

– Eg. a. Send data, and signal that data is being sent. b. Reset signals

Clock Signal

● Sequential circuits respond at discrete instants of time

● Clock signal identifies these discrete instants– Discrete vs. Continuous: Speech is continuous,

Recording is discrete

Clock Signal

● Sequential circuits respond at discrete instants of time

● Clock signal identifies these discrete instants– Discrete vs. Continuous: Speech is continuous,

Recording is discrete

Clock Signal

● A periodic train of clock pulses– clock/clk

clock

Clock Signal

● A periodic train of clock pulses– clock/clk

● Clock pulse determines when computational activity will occur within the circuit– When computation should begin/end

clock

Clock Signal

● A periodic train of clock pulses– clock/clk

● Clock pulse determines when computational activity will occur within the circuit– When computation should begin/end

● Eg. Adders compute their sum at the occurrence of a clock pulse

clock

Synchronous Clocked Sequential Circuits

Flip-Flop input output

clock

Flip-Flop

● Stores 1-bit– In stable state, the output of a FF is either 0 or 1

●

input output

clock

Flip-Flop

● Stores 1-bit– In stable state, the output of a FF is either 0 or 1

● FF state changes only at clock pulse transition– Eg. at a rising edge (clock signal changes from 0 to

1)

input output

clock

Flip-Flop

● Stores 1-bit– In stable state, the output of a FF is either 0 or 1

● FF state changes only at clock pulse transition– Eg. at a rising edge (clock signal changes from 0 to

1)

● At all other instants, value at input is effectively ignored– Output cannot change even if inputs change

input output

clock

Flip-Flop

● Inputs to FF are generated by a preceding Combinational Circuit– Eg. Adder

input output

clock

CC1CC1 CC2CC2

Flip-Flop

● Inputs to FF are generated by a preceding Combinational Circuit– Eg. Adder

input output

clock

CC1CC1

Flip-Flop

● Inputs to FF are generated by a preceding Combinational Circuit– Eg. Adder

input output

clock

CC1CC1

at Rising edge of clock:    output = f(input,old output); # create new state

at all other time instants: output = output; # replay output value from prev Rising edge

at Rising edge of clock:    output = f(input,old output); # create new state

at all other time instants: output = output; # replay output value from prev Rising edge

Flip-Flop

● Inputs to FF are generated by a preceding Combinational Circuit– Eg. Adder

input output

clock

CC1CC1

at Rising edge of clock:   output = input; # create new state

at all other time instants: output = output; # replay output value from prev Rising edge

at Rising edge of clock:   output = input; # create new state

at all other time instants: output = output; # replay output value from prev Rising edge

ExampleExample

Flip-Flop

● Inputs to FF are generated by a preceding Combinational Circuit– Eg. Adder

input output

clock

CC1CC1

at Rising edge of clock:   output = (input)?old output:!(old output);at all other time instants: output = output; # replay output value from prev Rising edge

at Rising edge of clock:   output = (input)?old output:!(old output);at all other time instants: output = output; # replay output value from prev Rising edge

ExampleExample

Flip-Flop

● Output of CC1 should be ready and stable well before the clock edge arrives

● Output of CC1 should be stable until the FF captures the input correctly

input output

clock

CC1CC1

Flip-Flop

● Output of CC1 should be ready and stable well before the clock edge arrives

● Output of CC1 should be stable until the FF captures the input correctly

input output

clock

CC1CC1

InputReady

InputStable

Flip-Flop

● Output of CC1 should be ready and stable well before the clock edge arrives

● Output of CC1 should be stable until the FF captures the input correctly

input output

clock

CC1CC1

Setup timeSetup time Hold timeHold time

Clock Cycle

● Propagation delays in CC1 determine the minimum interval between clock pulses that will allow the circuit to operate correctly.

input output

clock

CC1CC1

input output

clock

CC1CC1

clock

Flip-Flops vs. Latches

● FFs are edge sensitive– Only change state at clock edge

● Latch is a level sensitive sequential circuit

Flip-Flops vs. Latches

● FFs are edge sensitive– Only change state at clock edge

● Latch is a level sensitive sequential circuit

Flip-Flops vs. Latches

● FFs are edge sensitive– Only change state at clock edge

● Latch is a level sensitive sequential circuit

D

FF-

Flip-Flops vs. Latches

● FFs are edge sensitive– Only change state at clock edge

● Latch is a level sensitive sequential circuit

D

FF-

Latch-Q

Flip-Flops vs. Latches

● Latch is a level sensitive sequential circuit

D

FF-

Latch-Q

at Level-High of clock:    output = f(input,old output); # create new state

at all other time instants: output = output; # replay output value from prev Rising edge

at Level-High of clock:    output = f(input,old output); # create new state

at all other time instants: output = output; # replay output value from prev Rising edge

Latch

● Latches are building blocks for flip-flops● Back-to-back latches form a FF

Sequential Circuits – Summary

● Information stored defines state of Sequential Circuit

● Output depends on inputs + present state of the storage elements

● Inputs can change/retain state● Specified by a time sequence of inputs,

outputs, and internal states

Summary

● Clock signal ● Sequential Circuits● Synchronous vs. Asynchronous circuits● Flip-Flops, Latches

Appendix

Flip-Flops vs. Latches

● FFs are edge sensitive– Only change state at clock edge

● Latch is a level sensitive sequential circuit

D

FF-

Latch-Q

Set-Reset Latch (SR Latch)

S

R

Q

Q

at Level-High of clock:

  If( (S == 1) && (R == 0)): then

    Q = 1; Q’ = 0;

  Else if( (S == 0) && (R == 1)): then

    Q = 0; Q’ = 1;

  Else if( (S == 0) && (R == 0)): then

    Q = Q; Q’ = Q’;

  Else if( (S == 1) && (R == 1)): then

    Q = Q; Q’ = Q’;

at all other time instants:

output = output; # replay output value from prev Rising edge

at Level-High of clock:

  If( (S == 1) && (R == 0)): then

    Q = 1; Q’ = 0;

  Else if( (S == 0) && (R == 1)): then

    Q = 0; Q’ = 1;

  Else if( (S == 0) && (R == 0)): then

    Q = Q; Q’ = Q’;

  Else if( (S == 1) && (R == 1)): then

    Q = Q; Q’ = Q’;

at all other time instants:

output = output; # replay output value from prev Rising edge