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YonseiYonsei UniversityUniversity
Chapter 14Chapter 14
Control Unit Operation
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ContentsContents
• Micro-Operation• Control of the Processor• Hardwired Implementation
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MicroMicro--OperationsOperations
• Micro refers to the fact that each step is very simple and accomplishes very little
• The execution of a program consists of the sequential execution of instructions
• Each instruction is executed during an instruction cycle made up of shorter subcycles
• The performance of each subcycleinvolves one or more shorter operations, that is, micro-operations
Micro-Operations
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Constituent ElementConstituent Element Micro-Operations
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The Fetch CycleThe Fetch Cycle
• Four involved registers.– Memory address register (MAR) :
• Is connected to the address lines of the system bus• It specifies the address in memory for a read or write
operation
– Memory buffer register (MBR) : • Is connected to the data lines of the system bus• It contains the value to be stored in memory or the last
value read from memory
– Program counter (PC) : • Holds the address of the next instruction to be fetched
– Instruction register (IR) : • Holds the last instruction fetched
Micro-Operations
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Sequence of Events, Fetch CycleSequence of Events, Fetch Cycle
(a) Beginning
Micro-Operations
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Sequence of Events, Fetch CycleSequence of Events, Fetch Cycle
(b) First Step
Micro-Operations
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Sequence of Events, Fetch CycleSequence of Events, Fetch Cycle
(c) Second Step
Micro-Operations
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Sequence of Events, Fetch CycleSequence of Events, Fetch Cycle
(d) Third Step
Micro-Operations
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The Fetch CycleThe Fetch Cycle –– SequenceSequence
(a) Beginning : the address of the next instruction to be executed is in the PC
(b) First step : move that address to the MAR
(c) Second step : bring in the instruction The desired address is placed on the address bus, the control unit issues a READ command on the control bus, and the result appears on the data bus and is copied into the MBR
(d) Third step : move the contents of the MBR to the IR
This free up the MBR for use during a possible indirect cycle
Micro-Operations
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The Fetch CycleThe Fetch Cycle –– SequenceSequence
•Symbolic presentationt1: MAR ? (PC)t2: MBR ? Memory
PC ? (PC) + It3: IR ? (MBR)
•Micro-operation grouping rules1. The proper sequence of events must be followed2. Conflicts must be avoided
•Micro-operation involve an addition- This addition could be performed by the ALU- The use of the ALU may involve additional
micro-operations
Micro-Operations
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The Indirect CycleThe Indirect Cycle
• Indirect addressing
t1: MAR ? (IR(Address))t2: MBR ? Memoryt3: IR(Address) ? (MBR(Address))
Micro-Operations
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The Interrupt CycleThe Interrupt Cycle
t1: MBR ? (PC)t2: MAR ? Save_Address
PC ? Routine_Addresst3: Memory ? (MBR)
Micro-Operations
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The Execute CycleThe Execute Cycle
• ADD R1, Xt1: MAR ? (IR(address))t2: MBR ? Memoryt3: R1 ? (R1) + (MBR)
• ISZ X (increment and skip if zero)t1: MAR ? (IR(address))t2: MBR ? Memoryt3: MBR ? (MBR) + 1t4: Memory ? (MBR)
If((MBR) = 0) then (PC ? (PC) +I)
Micro-Operations
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The Execute CycleThe Execute Cycle
• BSA X (branch and save address)
t1: MAR ? (IR(address))MBR ? (PC)
t2: PC ? (IR(address))Memory ? MBR
t3: PC ? (PC) + I
Micro-Operations
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The Instruction CycleThe Instruction Cycle
• There is one sequence each for the fetch, indirect, and interrupt cycle, and, for the execute cycle, there is one sequence of micro-operation for each opcode
• Instruction cycle code(ICC)00: Fetch01: Indirect10: Execute11: Interrupt
Micro-Operations
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Flowchart for Instruction CycleFlowchart for Instruction CycleMicro-Operations
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Functional RequirementsFunctional Requirements
• The following three-step process leads to a characterization of the control unit:– Define the basic elements of the processor– Describe the micro-operations that the processor
performs– Determine the functions that the control unit must
perform to cause the micro operations to be performed
• Basic functional elements– ALU– Register– Internal data paths– External data paths– Control unit
Control Of The Processor
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Functional RequirementsFunctional Requirements
• The reader should see that all micro-operations fall into the following categories– Transfer data from one register to another– Transfer data from a register to an external interface– Transfer data from an external interface to a register– Perform an arithmetic or logic operation, using
registers for input and output
• The control unit perform two basic tasks– Sequencing– Execution
Control Of The Processor
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Control SignalsControl Signals
• Inputs– Clock – Instruction register– Flags
• Outputs– Control signals within the processor– Control signals to control bus
Control Of The Processor
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Model of Control UnitModel of Control Unit Control Of The Processor
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Model of Control UnitModel of Control Unit Control Of The Processor
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Control SignalsControl Signals
• A control signal that opens gates, allowing the contents of the MAR onto the address bus
• A memory read control signal on the control bus
• A control signal that opens the gates, allowing the contents of the data bus to be stored in the MBR
• Control signals to logic that add 1 to the contents of the PC and store the result back to the PC
Control Of The Processor
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A Control Signals ExampleA Control Signals Example
• Control signals go to three separate destinations– Data paths– ALU– System bus
Control Of The Processor
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Data Paths and Control SignalsData Paths and Control Signals Control Of The Processor
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MicroMicro--operation and Control Signalsoperation and Control Signals Control Of The Processor
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Internal Processor OrganizationInternal Processor Organization
• The ALU and all processor registers are connected by a single internal bus
• Gates and control signals are provided for movement of data onto and off the bus from each register
• Two new registers,labeled Y and Z, have been added to the organization
Control Of The Processor
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CPU with Internal BusCPU with Internal Bus Control Of The Processor
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Internal Processor OrganizationInternal Processor Organization
• An operation to add a value from memory to the AC would have the following steps:
t1: MAR<-(IR(address))t2: MBR<-Memory t3: Y<-(MBR)t4: Z<-(AC) + (Y)t5:AC<-(Z)
• Register Y provide temporary storage for the other input
• Register Z provide temporary output storage
Control Of The Processor
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The Intel 8085The Intel 8085
• Incrementer/decrementer address latch– Logic that can add 1 to or subtract 1 from the
contents of the stack pointer or program counter
• Interrupt control– This module handles multiple levels of interrupt
signals
• Serial I/O control– This module interfaces to devices that
communicate 1 bit at a time
Control Of The Processor
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Intel 8085 CPU Block DiagramIntel 8085 CPU Block Diagram Control Of The Processor
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Intel8085 External SignalsIntel8085 External Signals Control Of The Processor
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Intel 8085 External SignalsIntel 8085 External Signals Control Of The Processor
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Intel 8085 Pin ConfigurationIntel 8085 Pin Configuration Control Of The Processor
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• The control unit is identified as having two components labeled
(1) instruction decoder and machine cycle encoding(2) Timing and control
• Timing and control– accepts as inputs clock, current instruction and some
external control signal
• Each instruction cycle is divided into from one to five machine cycles
• The number of machine cycles is fixed for a given instruction but varies from one instruction to another
Control Of The Processor
Timing and controlTiming and control
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Timing DiagramTiming Diagram Control Of The Processor
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Hardwired ImplementationHardwired Implementation• Control unit implementation
– Hardwired implementation– Microprogrammed implementation
Hardwired Implementation
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Control Unit InputsControl Unit Inputs• The key inputs are the instruction register,
the clock, flags, and control bus signals• To simplify the control unit logic, there
should be a unique logic input for each opcode
• Decoder– Takes an encoded input and produces a single
output
• The clock portion of the control unit issues a repetitive sequence of pulses
Hardwired Implementation
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DecoderDecoder Hardwired Implementation
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Control Unit with Decoded InputsControl Unit with Decoded Inputs Hardwired Implementation
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Control Unit LogicControl Unit Logic• Derive a Boolean expression of that signal
as a function of the inputs• Define two new control signal, P and Q
PQ = 00 Fetch CyclePQ = 01 Indirect CyclePQ = 10 Execute CyclePQ = 11 Interrupt Cycle
Hardwired Implementation
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Control Unit LogicControl Unit Logic
• The task of implementing a combinatorial circuit that satisfies all of these equations becomes extremely difficult
• The results is that a far simpler approach– Microprogramming
Hardwired Implementation
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