Beam Secondary Shower Acquisition System: Analogue FE installation schedule and Digital FE Status...
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- Beam Secondary Shower Acquisition System: Analogue FE
installation schedule and Digital FE Status BE-BI-BL Jose Luis
Sirvent Blasco (jsirvent@cern.ch) 2 Jose Luis Sirvent Blasco PhD.
Student STUDENT MEETING 16/03/2015
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- 1. Analogue Front-End: Installation for testing purposes
Location : SPS 51740 (BA50 / RA1705) SPS Schedule: Technical Stop
19/03/2015 Trip for Observation Technical Stop 08/04/2015 Analogue
Front-End installation Technical Stop 26/09/2015 Digital Front-End
installation ?? BE-BI-BL Jose Luis Sirvent Blasco
(jsirvent@cern.ch) 3 BWSD51731 Linear Wire Scanner S Start: 5154.8m
BWSRE51740: Rotative WS Prototype S Start: 5161.5m 6.7m SLAC
Collimator 51738 Potential location??
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- BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 4 1.
Analogue Front-End: The pCVD Front-End (BLM Like): cables needed
Power + 12V (BNC-CB50) Power - 12V (BNC-CB50) HG Signal (Type N -
CK50) LG Signal (Type N - CK50) pCVD High Voltage (HVPF-CBH50)
Pieces and Equipment provided by Ewald Effinger
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- BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 5 1.
Analogue Front-End: Are these cables on the BWSRE51740 location??
Id say yes, and 5m seems enough to reach the potential
location
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- Adaptation of: EDA-01716 HPA-High Frequency PMT Amplifier
BoxEDA-01716 HPA-High Frequency PMT Amplifier Box By J. Koopman
08/10/2007 Used on BWS PMT as far as I know there have not been
major issues with this amplif and radiation. BE-BI-BL Jose Luis
Sirvent Blasco (jsirvent@cern.ch) 6 2. The pCVD amplifier: A look
in detail Input Protection Limited output voltage Stability and Low
pass filter Relay for Test Lamp
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- Something extremely simple 1x THS3001 1x Resistor 1 K ohm 2x
Resistor 51 ohm 2x Decoupling Caps 100nF 2x Decoupling Caps 1uF 2x
SMA Connectors (In/Out) 2x LEMO Connectors (Power +/- 12V)
Impedance matched In/Out Inverter configuration May be a good idea
to use non-inverter configuration HG and LG channels with same
polarity BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 7 2.
The pCVD amplifier: What is inside then?
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- BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 8 2. The
pCVD amplifier: What is inside then?
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- BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 9 2. The
pCVD amplifier: Some performance tests (1. Square wave 20Mhz) INPUT
OUTPUT
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- BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 10 2. The
pCVD amplifier: Some performance tests (2. Short Pulses 5ns width)
INPUT OUTPUT
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- BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 11 2. The
pCVD amplifier: Some performance tests (3. Charge Signal: AC
coupled Square 10pF) INPUT OUTPUT Reflections due to decoupling cap
(Impedance mismatching) Which are present also in the input: not
amplifiers fault
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- BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 12 3.
Expected charge on pCVD for BWSRE51740 : Rough calculations based
on A.Lecker simulations (@ 2m from IP) # of interacting particles
Dose @ 2m (Gy) Charge in detector (C) Generated Current (A)
Estimated signal magnitude (@ 2m): *Roughly these values are
divided by 2 @ 5m
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- BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 13 3.
Expected charge on pCVD for BWSRE51740 : Rough calculations based
on A.Lecker simulations (@ 2m from IP) # of interacting particles
Dose @ 2m (Gy) Charge in detector (C) Generated Current (A)
Estimated signal magnitude (@ 2m): *Roughly these values are
divided by 2 @ 5m To sum up with the analogue FE Front-End
construction Finished Amplifier characterization OK (minor
modifications to do) Potential sensor location identified Cables
availability guaranteed (but weve to take a look anyway) Cables
length seems to be fine Signal amplitude estimated ( 50 100mV
amplitude)
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- BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 14 4.
Digital Front-End Status Test Set-Up: Emulating the system
architecture Back-End System Front-End System Diamond Detector 3 x
LHC Clock Tunnel Surface SMF 9/125um Message for the cleaning
lady
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- Link States: 1. Start-up at Test-Mode : Known pattern to check
synch. 2. Latency calculation : FE loops data 3. Link on Normal
mode 4. Remote QIE10 Initialization 5. Trigger signal for data
acquisition 6. Data capture : Stored on BE SDRAM memory 7. Stop
Acquisition 8. Post-mortem data transmission SDRAM PC BE-BI-BL Jose
Luis Sirvent Blasco (jsirvent@cern.ch) 15 4. Digital Front-End
Status Status of the TO-DO list for complete system operation
BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 15
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- BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 16 4.
Digital Front-End Status First QIE10 acquisitions with function
generator
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- BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 17 4.
Digital Front-End Status Preparing synchronous acquisitions The
idea: To use a system CLK 40Mhz for Igloo2 REFCLK and to trigger
F.Generator Pulses on synch with 40MHz System CLK propagated to FE
Latency/Phase deterministic system Synchronous acquisitions on FE
The objective: Test jitter performance Check TDC functionality
Check ADC linearity System CLK Synchronous Pulses (Charge) Back-End
TX CLK Front-End RX CLK
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- BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 19
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- Write Operation BE-BI-BL Jose Luis Sirvent Blasco
(jsirvent@cern.ch) 20
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- Continuous Write Operation BE-BI-BL Jose Luis Sirvent Blasco
(jsirvent@cern.ch) 21
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- Console Application BE-BI-BL Jose Luis Sirvent Blasco
(jsirvent@cern.ch) 22
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- Counter TESTS (coreUART 115200 baud) BE-BI-BL Jose Luis Sirvent
Blasco (jsirvent@cern.ch) 23 1:18 min
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- BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 24
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- 1. The BWS Readout Upgraded System 1.1 Architecture BE-BI-BL
Jose Luis Sirvent Blasco (jsirvent@cern.ch) 25 Usage of the GBT
link for Data, Control and Timing transmission FE BE GBT Protocol @
4.8Gbps Beam Synchronous measurements Two serious candidates as
readout ASIC for pCVD diamond Detector: ICECAL (LHCb) QIE10 (CMS)
Well design for tunnel radiation levels: 100Gy/year up to 1KGy (10
years)
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- BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 26 1. The
BWS Readout Upgraded System 1.2 Front-End Board (QIE10 Acquisiton)
Igloo2 UMd Mezzanine Board Experiment CMS: T.Grassi & T. OBanon
Usage: GBT Link for ngCCM QIE10 Mezzanine Board Experiment BI BWS:
J.L. Sirvent Usage: Digitalization pCVD Diamond Detector SMA VTRx
Power Vcc = 6v SMF 9/125 Control/Debug System seen as a Black
Box
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- BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 27 1. The
BWS Readout Upgraded System 1.2 Front-End Board (Assembly
tests)
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- 2. Planning laboratory tests 2.1 Test schematic: BE-BI-BL Jose
Luis Sirvent Blasco (jsirvent@cern.ch) 28 Link States: 1. Start-up
at Test-Mode : Known pattern to check synch. 2. Latency calculation
: FE loops data 3. Link on Normal mode 4. Remote QIE10
Initialization 5. Trigger signal for data acquisition 6. Data
capture : Stored on BE SDRAM memory 7. Stop Acquisition 8.
Post-mortem data transmission SDRAM PC
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- 2. Planning laboratory tests 2.1 Test schematic: BE-BI-BL Jose
Luis Sirvent Blasco (jsirvent@cern.ch) 29 Link States: 1. Start-up
at Test-Mode : Known pattern to check synch. 2. Latency calculation
: FE loops data 3. Link on Normal mode 4. Remote QIE10
Initialization 5. Trigger signal for data acquisition 6. Data
capture : Stored on BE SDRAM memory 7. Stop Acquisition 8.
Post-mortem data transmission SDRAM PC
- Slide 30
- 2. Planning laboratory tests 2.1 Test schematic: BE-BI-BL Jose
Luis Sirvent Blasco (jsirvent@cern.ch) 30 Link States: 1. Start-up
at Test-Mode : Known pattern to check synch. 2. Latency calculation
: FE loops data 3. Link on Normal mode 4. Remote QIE10
Initialization 5. Trigger signal for data acquisition 6. Data
capture : Stored on BE SDRAM memory 7. Stop Acquisition 8.
Post-mortem data transmission SDRAM PC High Speed lines Looped