View
243
Download
0
Category
Preview:
Citation preview
8/4/2019 ASM session1
1/32
ARM assembly language programming
8/4/2019 ASM session1
2/32
General Layout of an Assembly Program
label opcode operands ; comment
Example
start MOVr0,#15 ; put 15 into reg. r0
Each field must be separated by one or more (suchas a space or a tab).
Actual instructions never start in the first column, since theymust be preceded by whitespace, even if there is no label.
All three sections are optional
8/4/2019 ASM session1
3/32
Asm program
AREA ARMex, CODE, READONLY
ENTRY
start : MOV r0, #10
MOV r1, #0x20
ADD r0, r0, r1
stop: B stop
END
/* Name this block of code ARMex*/
/* Mark first instruction to execute *//* Set up parameters */
/* r0 = r0 + r1 */
/* Mark end of fi le */
8/4/2019 ASM session1
4/32
AREA, ENTRY & END Assembly Directives
Directives are instructions to the assembler program, NOT to
the microprocessors
AREA Directive - specifies chunks of data or code that aremanipulated by the linker. The example above consists of a single area which contains code and
is marked as being read-only. A single CODE area is the minimumrequired to produce an application.
A complete application can consist of one or more areas.
ENTRY Directive - marks the first instruction to be executed
within an applicationAn application can contain only a single entry point and so in a multi-
source-module application, only a single module will contain an ENTRYdirective.
END directive - marks the end of the module Instructs the assembler to stop processing this source file
8/4/2019 ASM session1
5/32
Assembly Directives
Labels Labels are symbols that represent addresses. The address given by a label
is calculated during assembly.
The assembler calculates the address of a label relative to the origin ofthe section where the label is defined. A reference to a label within thesame section can use the PC plus or minus an offset. This is calledprogram-relative addressing.
8/4/2019 ASM session1
6/32
Call ing subroutinesAdds the values of two parameters and returns a result in r0.
AREA subrout, CODE, READONLY
ENTRY
start: MOV r0, #10
MOV r1, #20BL doadd
stop:B stop
doadd: ADD r0, r0, r1
MOV PC, LR
END
subroutine doadd is called by using abranch with link instruction (BL branchaddress).
It then returns by simply restoring theprogram counter to the address which was
stored in the l ink register (r14) on entry.
BL copies the address of the next
instruction into r14 (lr=link register), thenfills PC=branch address (go to branchaddress).
8/4/2019 ASM session1
7/32
Description of ex1
The main routine of the program (labelled start) loads the values 10 and20 into registers 0 and 1.
It calls the subroutine doadd by using a branch with link instruction (BLbranch address). BL copies the address of the next instruction into r14(lr=link register), then fills PC=branch address (go to branch address).
The subroutine adds together the two parameters it has received andplaces the result back into r0.
It then returns by simply restoring the program counter to the addresswhich was stored in the l ink register (r14) on entry.
8/4/2019 ASM session1
8/32
The S suffix
Data processing instructions of ARM will not modify thecondition flags in CPSR.
But we can modify the condition flags by appending S bit to theinstruction.
Example
MOV r3, #00 .. This instruction will not update zero flag. MOVS r3, #00 This instruction will update the zero flag.
8/4/2019 ASM session1
9/32
Program Status Register
Condition code flags N = Negative result from ALU is set to bit 31 of result Z = Zero result from ALU C = ALU operation Carried out V = ALU operation Overflowed
Interrupt disable bits (I & F) I bit When set to 1 disables IRQ interrupts F bit When set to 1 disables FIQ interrupts
T Bit(Architecture xT only) T = 0: Processor in ARM state T = 1: Processor in Thumb state
M0, M1,M2, M3, M4 are mode bits. These determine the mode in whichprocessor operates. (Tells operating mode of processor)
N Z C V I F T M4 M3 M2 M1 M031 30 29 28 7 6 5 4 3 2 1 0
8/4/2019 ASM session1
10/32
The S suffix
Result of addition is zero but Zero flag will not be set
#AREA ARMex, CODE, READONLY#ENTRY
start: MOV r0, #-3MOV r1, #3ADD r0, r0, r1
stop: B stop
#END
8/4/2019 ASM session1
11/32
The S suffix
This example conditional flags of CPSR will be modified becausethe S suffix is added to ADD instruction
#AREA ARMex, CODE, READONLY#ENTRY
start: MOV r0, #-3MOV r1, #3ADDS r0, r0, r1
stop: B stop
#END
8/4/2019 ASM session1
12/32
Loop
Write a program that adds value 3 to the register ten times
mov r0,#10mov r1,#0again: add r1,r1,#3sub r0, r0,#1
Branch if Z-flag is not set to again
C statementsfor (i=10; i>0;i--)------
mov r0,#10mov r1,#0
again: add r1,r1,#3subs r0, r0,#1Branch if Z-flag is not set to again
8/4/2019 ASM session1
13/32
ARM instructions
8/4/2019 ASM session1
14/32
Main features of the ARM Instruction Set
All instructions are 32 bits long.
Most instructions execute in a single cycle. Every instruction can be conditionally executed.A load/store architecture
Data processing instructions act only on registers Three operand format Combined ALU and shifter for high speed bit manipulation
Specific memory access instructions with powerful auto-indexingaddressing modes. 32 bit and 8 bit data types and also 16 bit data types on ARMArchitecture v4.
Flexible multiple register load and store instructions
3-address instruction format 2 address instruction format
Instruction set extension via coprocessors
8/4/2019 ASM session1
15/32
ARM instructions
Data processing instructions
Load and store instructions
Semaphore instructions
Multiply instructions
Exception generating instruction
Branch instructions
Coprocessor instruction
8/4/2019 ASM session1
16/32
Data processing Instructions
Data movement MOV MVN Logical AND ORR EOR BIC
Arithmetic ADD ADC SUB SBC RSB RSC
Comparisons CMP CMN TST TEQ
These instructions only work on registers, NOT memory.
Syntax: 3 operands - 2 for inputs and 1 for result
{}{S} Rd, Rn, Operand2
All operands are 32 bits, come either from registers or arespecified as constants (called literals) in the instruction itself
8/4/2019 ASM session1
17/32
Data Movement Operations are:
MOV operand2 MVN NOT operand2
Note that these make no use of operand1 Examples:
MOVS r2, #10
Syntax:{}{S} Rd, Operand2
8/4/2019 ASM session1
18/32
Barrel shifter
One of the operand of ALU always comes from barrel shifter.
This unique & powerful feature allows 32 bit binary pattern ofthe source register to be shifted left or right before it enters
ALU.
8/4/2019 ASM session1
19/32
Barrel shifter
MOV R7, R5, LSL #2 If R5=10 the what is value of R7
C statement:int i=10, j;j = I
8/4/2019 ASM session1
20/32
Barrel shifter operations
LSL logical shift leftLSR logical shift rightASR arithmetic right shiftROR rotate right
ADD R0, R1, R1, LSL#1
ADD R0, R0, R0, LSL#N (R0=R0+R0
8/4/2019 ASM session1
21/32
Logical Operations
Examples:AND r0, r1, r2
BIC r2, r3, #7 EORS r1,r3,r0
Syntax:{}{S} Rd, Rn, N
AND bitwise AND of two 32-bit values Rd = Rn & N
ORR bitwise OR of two 32-bit values Rd = Rn | N
EOR bitwise XOR of two 32-bit values Rd = Rn N
BIC Logical bit clear Rd = Rn & N
8/4/2019 ASM session1
22/32
Arithmetic Operations
Operations are:ADD operand1 + operand2ADC operand1 + operand2 + carry SUB operand1 - operand2 SBC operand1 - operand2 - !(carry flag) RSB operand2 - operand1 RSC operand2 - operand1 - !(carry flag)
Examples:ADDC r0, r1, r2 r0 := r1+ r2 SBC R0, R1, R2 r0 := r1 r2 - !(carry) RSB r0, r1, r2 r0 := r2 r1
Syntax:{}{S} Rd, Rn, Operand2
8/4/2019 ASM session1
23/32
Comparisons The only effect of the comparisons is to UPDATE THE
CONDITION FLAGS. Operations are:
CMP operand1 - operand2 but result not written CMN operand1 + operand2 but result not written TST operand1 AND operand2 but result not written TEQ operand1 EOR operand2 but result not written
Corresponding operation is carried out conditional flags areupdated depending on the result so that subsequent instructioncan be conditionally executed
Examples:CMP r1 , r2 r1 r2
CMN r1, r2 r1 + r2
TST r1, r2 r1 and r2
TEQ r1,r2 r1 xor r2
8/4/2019 ASM session1
24/32
Comparisons
TEQ is useful To test whether two values are equal without
When TEQ is executed, N flag is logical exor of the sign bits oftwo operands hence we can check whether two values have thesame sign.
TST is used to check if register bits include at least one bit set.A common use of TST is to test if single bit is set or clear
8/4/2019 ASM session1
25/32
Conditional execution
Most ISAs only allow branches to be executed conditionally.
But ARM ISA has a unique and clever way of dealing withconditional branches.
Instead of having special conditional branch instructions,
ARM ISA implements a feature ofexecuting ALL instructionsconditionally. For this every instruction contains a conditional field which determines
whether the instruction will be executed or ignored. Thus CPU will execute the instruction only if the condition is satisfied.
Conditional execution depends on two components Conditional field/code (.............located in instruction) Condition flags (.............located in CPSR)
8/4/2019 ASM session1
26/32
Conditional execution
To execute an instruction conditionally, simply postfix it with appropriate
condition code: For example an add instruction takes the form:
ADD r0,r1,r2 ; r0 = r1 + r2
To execute this only if the zero flag is set: ADDEQ r0,r1,r2 ; If zero flag set then .. r0 = r1 + r2
If is omitted then it is executed always Almost all ARM instructions can be conditionally executed
Instruction will be executed only if N,Z,C & V satisfy the condition specified ininstruction.
If flags do not satisfy the condition instruction acts as NOP & execution advances tonext instruction.
8/4/2019 ASM session1
27/32
Condition Codes
The possible condition codes are listed below:
Not equal
Unsigned higher or same
Unsigned lower
Minus
Equal
Overflow
No overflow
Unsigned higher
Unsigned lower or same
Positive or Zero
Less than
Greater than
Less than or equal
Always
Greater or equal
EQNECS/HSCC/LOPLVSHILSGELTGTLEAL
MI
VC
Suffix Description
Z=0C=1C=0
Z=1Flags tested
N=1N=0V=1V=0C=1 & Z=0C=0 or Z=1N=VN!=VZ=0 & N=VZ=1 or N=!V
8/4/2019 ASM session1
28/32
Conditional execution: example
This improves code density and performance by reducing the number offorward branch instructions.
CMP r3,#0 CMP r3,#0BEQ skip ADDNE r0,r1,r2ADD r0,r1,r2skip
Conditional execution reduces number of branches that reduces numberof pipeline flushes and thus improves the performance.
8/4/2019 ASM session1
29/32
Conditional execution
Conditional execution can replace branch instructions Example
CMP r0, #5 ;
BEQ BYPASS ; if (r0!=5) r1:=r1+r0-r2
ADD r1, r1, r0
SUB r1, r1, r2
BYPASS: ...
With conditional execution
CMP r0, #5 ;
ADDNE r1, r1, r0 ;
SUBNE r1, r1, r2 ;
8/4/2019 ASM session1
30/32
Conditional execution Use a sequence of several conditional instructions
Set the flags, then use various condition codes
if (a==0) x=0;if (a>0) x=1;
CMP r0,#0
MOVEQ r1,#0
MOVGT r1,#1
if (a==0)
{
count =count+1;
flag = 1;
}
CMP r0,#0
ADDEQ r1,r1,#1
MOVEQ r3, #1
8/4/2019 ASM session1
31/32
Conditional execution examples
MOVEQ r0,r1 ; r0 := r1 if Z flag set MOVS r0, r1, LSR #1 ; C(flag) := r1[0]
MOVCC r0, #10 ; if C=0 then r0:=10
MOVCS r0, #11 ;if C=1 then r0:=11
S flag: determines if the flag fields are affected or not
MOV r1,#10loop
ADD R3, R3,#3
SUBS r1,r1,#1
BNE loopif Z flag clear then branch
decrement r1 and set flags
8/4/2019 ASM session1
32/32
Conditional execution oring
; if ((a==0) || (b==1))
c = d + e;
CMP r0,#0CMPNE r1, #1ADDEQ r2, r3, r4
Use conditional compare instruction
if (a==4 || a==10) x=0;
CMP r0,#4
CMPNE r0,#10
MOVEQ r1,#0
Recommended